DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election without traverse of Group I (Claims 1-13) in the reply filed on April 20, 2026, is acknowledged. The election of Species I-1 (Claim 9) was made by Gary McFaline on April 21, 2026.
3. Claims 10-12 and 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species I-2, I-3, I-4 and Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 20, 2026. Therefore, Claims 1-9 and 13 are pending in this office action.
Priority
4. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d) or (f), which papers have been placed of record in the file.
Information Disclosure Statement
5. Information disclosure statement (IDS), submitted February 28, 2023, and September 24, 2024, has been received and considered by the examiner.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 1-9 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Worry et al. (US 2016/0261127 A1).
With regard to Claim 1, Worry et al. disclose a battery assembly, called a battery management system (100), comprising: an enclosure including a plurality of battery cells (110a-n) in a battery stack (111) (paragraph 0038); a sensor, including a temperature sensor (418) and cell voltage taps (412), within the enclosure, the sensor configured to measure a parameter within the enclosure, and generate a sense signal sent to analog front end (410) (paragraphs 0074, 0083-0084); a processor, called a stack controller (150), within the enclosure, the processor (150) configured to process the sense signal and generate information associated with the sense signal (paragraphs 0053, 0055, 0081); a first communication link, called a stack bus (155), configured to transmit, from the enclosure to a system (290) that is external to the enclosure (paragraph 0065), a discrete signal indicative of whether the sense signal indicates a fault condition; and a second communication link, also part of the stack bus (155), configured to transmit, from the enclosure to the system, a digital signal including the information associated with the sense signal (paragraph 0065).
With regard to Claim 2, Worry et al. disclose wherein the sensor is a first sensor, the parameter is a first parameter, the sense signal is a first sense signal, the discrete signal is a first discrete signal, the information is a first information, and wherein the battery assembly (100) further comprises: a second sensor, including a temperature sensor (418) and cell voltage taps (412) (plurality of sensors), within the enclosure, the second sensor configured to measure a second parameter within the enclosure, and generate a second sense signal; wherein the processor (150) is configured to process the second sense signal, and generate second information that is associated with the second sense signal; wherein the first communication link (155) is configured to transmit, from the enclosure to the system, a second discrete signal indicative of whether the second sense signal indicates a fault condition; and wherein the second communication link (155) is configured to transmit, from the enclosure to the system, the digital signal that includes the second information associated with the second sense signal (paragraphs 0065, 0085, 0240).
With regard to Claim 3, Worry et al. disclose wherein the first communication link (155) is an analog communication link between the processor and the system (paragraph 0087), and the second communication link (155) is a digital communication link between the processor and the system, wherein the stack bus (155) communicatively connects the stack controller (150) to the power interface and may also include a CAN bus used as digital communication channels (paragraph 0054).
With regard to Claim 4, Worry et al. disclose wherein the second communication link is a Controller Area Network (CAN) bus between the processor (150) and the system (paragraph 0054).
With regard to Claim 5, Worry et al. further disclose a comparator (U1 999) configured to compare the sense signal with a threshold value (a reference voltage V_ave) of the parameter, and generate the discrete signal based on the comparison (paragraph 0228).
With regard to Claim 6, Worry et al. disclose wherein the comparator (U1 999) is a part of the processor (150) since the stack controller (150) includes a fault pilot detector (900c) (paragraph 0118) and the fault pilot signal detector includes the comparator (U1 999) (paragraphs 0221, 0028).
With regard to Claim 7, Worry et al. disclose wherein: the first communication link is between the comparator and the system, bypassing the processor (FIG. 13C shows a diagram 1300 C of another connection between the external equipment 1330 and the external control connector 1302 [first communication link to external device], connecting the drive terminal 1304 b and common terminal 1304 c, to enable and disable control of the switches, while permitting direct de-energizing of the coils in response to the fault signal independent of the microcontroller 640 or 963 [bypassing the digital processor], (paragraph 0307); and the second communication link is a digital communication link between the processor and the system (stack bus 155 is a cable that communicatively connects the stack controller 150 to the power interface. The stack bus 155 may also include a CAN bus used as a digital communication channel (paragraph 0054); the stack controller 150 generates control instructions based on data received from cell interfaces 120 a-n the stack controller 150 transmits the control instructions and the information via the stack bus 155 to the power interface 160 (paragraph 0240); adding the use of coded signals over communication channels to acquire information about the status of the battery stacks (paragraph 0065)).
With regard to Claim 8, Worry et al. disclose wherein the information associated with the sense signal includes a value of the parameter (signal GFSENS_P 951, and converted to a digital value by the analogue-to-digital converter (paragraph 0191); stack controller 150 sends the digital value through stack bus 155 (paragraph 0192)).
With regard to Claim 9, Worry et al. disclose wherein: the sensor is a voltage monitor, and the sense signal is indicative of a voltage of one or more battery cells of the plurality of battery cells (the AFE 410 receives sensing signals about the voltage and temperature of the connected battery cell(s), and sends data to the stack controller, (paragraph 0081)); and the fault condition is one of an over voltage or an under-voltage, where the monitored voltage is one of lower than a first threshold value or higher than a second threshold value, respectively (the input from the sensor…the resulting signal is compared by comparator U1 999 a to a reference voltage V_ave (paragraph 0228); the output of U1 (FAULT#) will be at a low voltage indicating detection of a fault [discrete fault signal] (paragraph 0229)).
With regard to Claim 13, Worry et al. disclose a switch within the enclosure, wherein the plurality of battery cells is coupled via the switch to a circuit external to the enclosure (battery management system 100 includes switches 140 a, 140 b, and 140 c, (paragraph 0038); switch 140 c is an electrical switch that is connected in the power line 130 for controlling the connection of the battery stack with the load (paragraph 0052)); wherein responsive to receiving a control signal generated in response to the discrete signal and/or the information indicating a fault condition, the switch is configured to disconnect the plurality of battery cells from the circuit external to the enclosure (the power interface 160 may detect fault conditions and may control the switches 140 a-c accordingly (paragraph 0055)).
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KARIE O APICELLA whose telephone number is (571)272-8614. The examiner can normally be reached Monday thru Friday; 8:00AM to 5:00PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nicole Buie-Hatcher can be reached at 571-270-3879. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KARIE O'NEILL APICELLA/Primary Examiner, Art Unit 1725
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