Prosecution Insights
Last updated: October 27, 2026
Application No. 18/115,947

LIGHT EMITTING ELEMENT, DISPLAY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE LIGHT EMITTING ELEMENT

Non-Final OA §102§103
Filed
Mar 01, 2023
Priority
Mar 02, 2022 — RE 10-2022-0026872
Examiner
KOLAHDOUZAN, HAJAR
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
277 granted / 372 resolved
+6.5% vs TC avg
Strong +23% interview lift
Without
With
+22.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
19 currently pending
Career history
389
Total Applications
across all art units

Statute-Specific Performance

§103
59.6%
+19.6% vs TC avg
§102
30.8%
-9.2% vs TC avg
§112
8.6%
-31.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 372 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/4/26. Applicant’s election without traverse of 1-17 in the reply filed on 8/4/26 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 7-9, 15 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2020/0212268 A1; hereinafter Choi). Regarding Claim 1. Choi (Figs.1-8) discloses a light emitting element comprising: a first semiconductor layer (131, Fig.5B; [0083]) including a groove (120, [0118]) and a protrusion ([0025]) disposed around the groove (120); a light emitting layer (132; [0083]) disposed on the groove of the first semiconductor layer (131), the light emitting layer (132) having a shape corresponding to the groove (120); a second semiconductor layer (133; [0083]) disposed on the light emitting layer (132); and an insulating pattern layer (134; [0089]) disposed on the protrusion of the first semiconductor layer (protrusion of 131 on the sides), the insulating pattern layer (134) surrounding the second semiconductor layer (133). Regarding Claim 2. The light emitting element according to claim 1, Choi (Figs.1-8) discloses wherein the insulating pattern layer (134) entirely surrounds the light emitting layer and the second semiconductor layer (133) in a plan view (see Fig.6A). Regarding Claim 3. The light emitting element according to claim 1, Choi (Figs.1-8) discloses wherein the light emitting layer (132) is disposed at a height equal to or less than a maximum height of the groove (120; See Fig.5B) with respect to a lower surface of the first semiconductor layer (lower surface of 131). Regarding Claim 7. The light emitting element according to claim 1, Choi (Figs.1-8) discloses wherein the first semiconductor layer (131) and the second semiconductor layer (133) are separated from each other by at least one of the light emitting layer (132) and the insulating pattern layer (134 horizontal parts on top in fig.5B) disposed between the first semiconductor layer (131) and the second semiconductor layer (133). Regarding Claim 8. The light emitting element according to claim I, Choi (Figs.1-8) discloses wherein the groove (120) comprises: a first surface (bottom surface) parallel to a lower surface of the first semiconductor layer (bottom surface of 131); and a second surface (the angled surfaces) protruding from the first surface (bottom surface) of the groove toward an upper surface of the first semiconductor layer (131). Regarding Claim 9. The light emitting element according to claim 8, Choi (Figs.1-8) discloses wherein the second surface (angled surface) of the groove includes an inclined surface inclined at an angle of less than 90 degrees with respect to the first surface of the groove (lower surface of 120). Regarding Claim 15. The light emitting element according to claim I, Choi (Figs.1-8) discloses further comprising: an electrode layer (E1; [0083]) disposed on the second semiconductor layer (133) and the insulating pattern layer (134; Fig.5A-B). Regarding Claim 17. Choi (Figs.1-8) discloses A display device comprising: a pixel including a light emitting element, wherein the light emitting element comprises: a first semiconductor layer (131) including a groove (120) and a protrusion ([0025]) disposed around the groove; a light emitting layer (132) disposed in the groove and having a shape corresponding to the groove (120); a second semiconductor layer (133) disposed around the light emitting layer (132) and separated from the first semiconductor layer (131) by the light emitting layer (132) between the first semiconductor layer (131) and the second semiconductor layer (133); and an insulating pattern layer (134) disposed at a position of the protrusion (the sidewalls and top of protrusion) and surrounding the second semiconductor layer (133). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4-6, 10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Bour et al. (US 2016/0197232 A1; hereinafter Bour). Regarding Claim 4. The light emitting element according to claim 1, Choi does not particularly disclose wherein the second semiconductor layer and the insulating pattern layer have a same height with respect to a lower surface of the first semiconductor layer. Bour (Fig.10D, 11D, 12E-F, 16D) discloses in a related art a light emitting element having a first layer (112), second layer (104), an active layer in between (108; [0101]), and insulating (122), wherein the second semiconductor layer (104) and the insulating pattern layer (122) have a same height with respect to a lower surface of the first semiconductor layer (112). Therefore, it would have been obvious in the art before the effective filing date of the application to have insulating layers with the same height as the second semiconductor layer in order to prevent any current leakage around the top part of the semiconductor layer and therefore having a more efficient LED device. Regarding Claim 5. The light emitting element according to claim 1, Choi does not particularly disclose wherein the second semiconductor layer has a height equal to or greater than a maximum height of the insulating pattern layer with respect to a lower surface of the first semiconductor layer, and a portion of the second semiconductor layer is disposed on the insulating pattern layer. Bour (Fig.9E, 10D, 11D, 12E-F, 16D) discloses in a related art a light emitting element having a first layer (112), second layer (104), an active layer in between (108; [0101]), and insulating (122), wherein the second semiconductor layer (104) has a height equal to or greater than a maximum height of the insulating pattern layer (122) with respect to a lower surface of the first semiconductor layer (112), and a portion of the second semiconductor layer (104) is disposed on the insulating pattern layer (122; Fig.9E). Therefore, it would have been obvious in the art before the effective filing date of the application to have insulating layers and the second semiconductor layer having any desired heights in order to prevent any current leakage around the unwanted parts of semiconductor layer and therefore having a more efficient LED device. Regarding Claim 6. The light emitting element of claim 5, Choi (Figs.1-8) discloses wherein the insulating pattern layer (134) entirely surrounds a remaining portion of the second semiconductor layer (133; also see Fig.5A-B). Regarding Claim 10. The light emitting element according to claim 8, Choi does not particularly disclose wherein the second surface of the groove is substantially perpendicular to the first surface of the groove. Bour (Fig.1, 4-8, 12, 15-16) discloses in a related art a light emitting element having a first layer (112) including a groove, second layer (104), an active layer in between (108; [0101]), and insulating (122), wherein the second surface of the groove (vertical surface) is substantially perpendicular to the first surface of the groove (horizontal surface). Therefore, it would have been obvious in the art before the effective filing date of the application to have a perpendicular shaped groove to have a larger surface to deposit the active layer and therefore better light extraction. Regarding Claim 14. The light emitting element according to claim 1, Choi does not particularly disclose a third semiconductor layer disposed between the first semiconductor layer and the light emitting layer; and a fourth semiconductor layer disposed between the light emitting layer and the second semiconductor layer. Bour (Fig.11A) discloses in a related art a light emitting element having a first layer (112) including a groove, second layer (104), an active layer in between (108; [0101]), and insulating (122), and a third semiconductor layer (106) disposed between the first semiconductor layer (104) and the light emitting layer (108); and a fourth semiconductor layer (1110A-C) disposed between the light emitting layer and the second semiconductor layer (112). Therefore, it would have been obvious in the art before the effective filing date of the application to have multiple semiconductor layers since it dramatically improves efficiency, confines electrical carriers, and boosts light output. Claim(s) 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of BAUMHEINRICH et al. (US 20220102583 A1; hereinafter BAUMHEINRICH). Regarding Claim 11. The light emitting element according to claim 8, Choi does not particularly disclose wherein at least one of the first surface and the second surface of the groove includes a curved surface. BAUMHEINRICH (Fig.120, 122; [1713]) discloses LED that has a first semiconductor having at least one of the first surface and the second surface of the groove includes a curved surface. Therefore, it would have been obvious in the art before the effective filing date of the application to have at least one of the first surface and the second surface of the groove includes a curved surface to spread evenly across the active light-emitting regions to maximize luminance. Regarding Claim 12. The light emitting element according to claim 1, Choi does not particularly disclose wherein the groove has a V-shaped cross section. BAUMHEINRICH (Fig.26-29) discloses LED that has a first semiconductor having a groove which has a V-shaped cross section. Therefore, it would have been obvious in the art before the effective filing date of the application to have a V-shaped grooved LEDs to present a much lower energy barrier to enable lateral carrier injection since holes can bypass the restrictive vertical stack and slip through the sides of the V-pits, spreading evenly across the active light-emitting regions to maximize luminance. Regarding Claim 13. The light emitting element according to claim 1, Choi does not particularly disclose wherein the groove has a curved shape in an entire area of the groove. BAUMHEINRICH (Fig.120, 122; [1713]) discloses LED that has a first semiconductor having wherein the groove has a curved shape in an entire area of the groove. Therefore, it would have been obvious in the art before the effective filing date of the application to have the groove with a curved shape in an entire area of the groove to spread evenly across the active light-emitting regions to maximize luminance. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAJAR KOLAHDOUZAN whose telephone number is (571)270-5842. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAJAR KOLAHDOUZAN/Examiner, Art Unit 2898 /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Mar 01, 2023
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
97%
With Interview (+22.8%)
2y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 372 resolved cases by this examiner. Grant probability derived from career allowance rate.

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