DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been examined.
Claims 1-20 have been rejected.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 16 is rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter. Below is an evaluation using the 2019 Revised Patent Subject Matter Eligibility Guidance.
As per claim 16, step 1 (Is the claim to a process, machine, manufacture, or composition of matter?) is satisfied because the claim is directed to a machine.
At step 2a prong 1 (does the claim recite an abstract idea, law of nature, or natural phenomenon?), an abstract idea is recited: steps of the claim could be performed as a mental process. These steps include
determining other far memory locations mapped to the same near memory location.
This process corresponds to evaluating the data and then making a judgment call; which are tasks that can be done in the human mind. Because an abstract idea is considered a judicial exception, the claim requires further analysis in step 2 prong 2.
At step 2a prong 2 (does the claim recite additional elements that integrate the judicial exception into a practical application?), the claim recites extra solution activity of inputting data in the following limitation:
receiving notification of a memory error at a near memory location in response to a request to access a far memory location mapped to the near memory location.
However, this limitation recites insignificant extra-solution activity as data outputting per MPEP 2106.05(g) and does not provide integration into a practical application.
Furthermore, the claim recites
a non-transitory machine-readable medium having instructions stored thereon configured to be executed on one or more processors to perform a method;
offlining the far memory location and the other far memory locations mapped to the near memory location.
However, these limitations recite mere instructions to apply an exception per MPEP 2106.05(f) and does not provide integration into a practical application.
Additional elements such as non-transitory machine-readable medium, one or more processors are a high-level recitation of generic computer components, computer elements used as a tool, and represent mere instructions to apply the abstract idea on a computer as in MPEP 2106.05(f), and does not provide integration into a practical application.
Therefore, claim 16 does not integrate the recited abstract ideas into a practical application. Because the claim does not recite additional elements that integrate the judicial exception into a practical application, the claim requires further analysis in step 2b.
At step 2b (does the claim recite additional elements that amount to significantly more than the judicial exception?), when considered individually or in combination, the additional limitations and elements of claim 16 does not amount to significantly more than the judicial exception for the same reasons discussed above as to why the additional limitations do not integrate the abstract idea into a practical application. The additional elements outlined in step 2a performs function as designed and simply accomplishes execution of the abstract ideas. The additional limitations identified as insignificant extra-solution activity in step 2a are carried over, and they do not provide significantly more. The claim language,
receiving notification of a memory error at a near memory location in response to a request to access a far memory location mapped to the near memory location,
is an example of providing input and have been found by the courts to be well understood, routine, and conventional. For Berkheimer support, see court recognized activities in MPEP 2106.05(d)(II). The additional limitations such as
a non-transitory machine-readable medium having instructions stored thereon configured to be executed on one or more processors to perform a method; offlining the far memory location and the other far memory locations mapped to the near memory location
are mere instructions to apply on a computer per MPEP 2106.05(f) and do not provide significantly more than the abstract idea. The elements reciting generic computer components that has been carried over from the previous step does not provide significantly more than the abstract idea. Because looking at the limitations in combination and the claims as a whole does not change this conclusion, the claim is ineligible. The additional limitations of claim 16 do not amount to significantly more than the judicial exception.
Claim 17 recites (2A Prong 1) a mental process in the following limitation:
determining the other far memory locations includes: checking an address map, by firmware, for the other far memory locations mapped to the near memory location.
Furthermore, (2A Prong 2) the claim recites extra solution activity of gathering data in the following limitation:
offlining the far memory location and the other far memory locations includes: providing by the firmware, an error log to an operating system to identify the far memory location and the other far memory locations to trigger offlining pages at those locations in the far memory by the operating system.
Additional elements such as firmware, operating system are high-level recitation of generic computer components, computer elements used as a tool, and represent mere instructions to apply the abstract idea on a computer as in MPEP 2106.05 (f). None of these additional limitations nor elements provide integration into practical application (it is noted that the limitations have been considered in light of all of the features of claim 16). And (2B) does not provide elements or limitations that amount to an inventive concept. Therefore, claim 17 is rejected for similar reason as claim 16.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the list.” There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-15 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Yigzaw et al (US 20180165207 A1) from henceforth referred to as Yigzaw
Per claim 1, Yigzaw teaches
A memory controller ([0146] 2LM memory controller) comprising:
input/output (1/0) interface circuitry ([0050]) to communicatively couple the memory controller with a near memory and a far memory; and ([0146])
hardware logic to:
detect an error at a near memory location in response to a request to access a far memory location mapped to the near memory location, (FIG. 20, step 2002: receive an address associated with an incoming memory access request [0137] the far memory is presented to the operating system as system memory, with the near memory acting as a transparent caching system that is managed by a collection of memory controllers and/or logic executing on a host CPU. [0139] detects an error in the address within the near memory)
in response to detection of the error at the near memory location, store information to identify the near memory location as faulty, ([0139] the faulty address in the near memory is stored in the faulty address buffer, FAB)
receive a subsequent request to access a second far memory location mapped to the same near memory location, ([0163] multiple far memory is mapped to a near memory, and thus subsequent request FIG. 20 step 2002 can represent a request to access a second far memory location mapped to the same near memory location)
check the stored information to determine whether the near memory location to which the second far memory location is mapped is faulty, and (FIG. 20, step 2006: perform parallel lookup for the address in a faulty address list)
bypass the near memory location when the near memory location is identified as faulty and send the subsequent request to the second far memory location. (FIG. 20, step 2010: satisfy the memory access request from far memory when address is cached in near memory and listed as a faulty address in the faulty address list, [0148])
Per claim 2, Yigzaw teaches
The memory controller of claim 1, wherein:
the hardware logic to identify the near memory location as faulty is to:
store the information indicative of the near memory location in a list of faulty near memory locations.
([0139] the faulty address in the near memory is stored in the faulty address buffer, FAB)
Per claim 3, Yigzaw teaches
The memory controller of claim 2, wherein:
the hardware logic is to store the information in one or more registers. ([0068] “The registers described herein can be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc.”)
Per claim 4, Yigzaw teaches
The memory controller of claim 1, wherein:
the hardware logic to bypass the near memory location is to:
return a miss for a fetch attempt to the near memory location when the near memory location is identified as faulty even when requested data is stored at the near memory location.
([0141] "If the FAB 1802 returns a hit, suggesting that the address in question has been previously marked as a bad address, the lookup to near memory 1420 is forced to a miss via the AND gate 1806, even if the lookup to near memory 1420 is a hit.")
Per claim 5, Yigzaw teaches
The memory controller of claim 1, wherein:
the hardware logic to bypass the near memory location is to:
skip an attempt to fetch from the near memory location when the near memory location is identified as faulty. ([0116] "The cache can then be used to filter out bad locations for future accesses, such that an access to far memory location that is aliased to a faulty location in near memory can be re-routed to far memory, bypassing the faulty cache location in near memory" if the near memory is faulty, the faulty cache location in near memory is skipped and the data is accessed from the far memory)
Per claim 6, Yigzaw teaches
The memory controller of claim 1, wherein:
the hardware logic is to indicate successful completion of the request to firmware despite the error at the near memory location. ([0128]-[0129] when an error is found in the near memory, the request is filled by finding the mapped far memory through the use of tag table and the “transfer complete” message is sent to the controller)
Per claim 7, Yigzaw teaches
The memory controller of claim 6, wherein:
the firmware is to provide a log to an operating system to indicate successful completion of the request to the far memory location, preventing offlining of the far memory location. ([0128]-[0129] when an error is found in the near memory, the request is filled by finding the mapped far memory through the use of tag table and the “transfer complete” message is sent to the controller; [0146] firmware is used to handle the logic regarding the hit/miss logic)
Per claim 8, Yigzaw teaches
The memory controller of claim 1, wherein: the hardware logic is to:
track a count of accesses to a near memory location identified as faulty, and
provide a notification when the count of accesses to the near memory location in the list exceeds a threshold.
([0144] firmware can observe a corrected error rate for certain addresses. Since the error is corrected by accessing the data from the far memory, this is equivalent of keeping track of accesses to the near memory identified as faulty. If enough count is detected -- i.e, error rate -- the system triggers a response)
Per claim 9, Yigzaw teaches
The memory controller of claim 1, wherein:
the 1/O interface circuitry is to communicatively couple the memory controller with the near memory via a controller for the near memory and communicatively couple the memory controller with the far memory via a second controller for the far memory. ([0050])
Per claim 10, Yigzaw teaches
A system comprising:
a memory hierarchy including a near memory and a far memory, wherein multiple locations in the far memory are mapped to a single location in the near memory; and ([0146])
a memory controller to:
store a near memory location in a list in response to detection of an error at the near memory location, the error encountered in response to a request to access a far memory location mapped to the near memory location, (FIG. 20, step 2002: receive an address associated with an incoming memory access request in which [0137] the far memory is mapped to a near memory and [0139] when an error is detected during the access of the near memory, the faulty address is stored in the faulty address buffer)
receive a subsequent request to access a second far memory location mapped to the same near memory location, ([0163] multiple far memory is mapped to a near memory, and thus subsequent request FIG. 20 step 2002 can represent a request to access a second far memory location mapped to the same near memory location)
check the list for the near memory location to which the second far memory location is mapped, and (FIG. 20, step 2006: perform parallel lookup for the address in a faulty address list)
bypass the near memory location when the near memory location is in the list and send the subsequent request to the second far memory location. (FIG. 20, step 2010: satisfy the memory access request from far memory when address is cached in near memory and listed as a faulty address in the faulty address list, [0148])
Per claim 11, Yigzaw teaches
The system of claim 10, wherein:
the memory controller to bypass the near memory location is to:
return a miss for a fetch attempt to the near memory location when the near memory location is in the list even when requested data is stored at the near memory location.
([0141] "If the FAB 1802 returns a hit, suggesting that the address in question has been previously marked as a bad address, the lookup to near memory 1420 is forced to a miss via the AND gate 1806, even if the lookup to near memory 1420 is a hit.")
Per claim 12, Yigzaw teaches
The system of claim 10, wherein: the memory controller includes a two-level memory (2LM) memory controller. ([0088])
Per claim 13, Yigzaw teaches
The system of claim 12, wherein: the 2LM memory controller is coupled with a first controller for the near memory and a second controller for the far memory. ([0146])
Per claim 14, Yigzaw teaches
The system of claim 10, wherein:
the memory controller includes control logic for both the near memory and the far memory. ([0146])
Per claim 15, Yigzaw teaches
The system of claim 10, further comprising:
one or more of: a processor including or coupled with the memory controller, a display, and a power source. ([0089])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yigzaw in view of Costa et al (A System Software Approach to Proactive Memory-Error Avoidance, SC14: International Conference for High Performance Computing, Networking, Storage and Analysis); from henceforth referred to as Costa.
Per claim 16, Yigzaw teaches
A non-transitory machine-readable medium having instructions stored thereon configured to be executed on one or more processors to perform a method ([0158]), the method comprising:
receiving notification of a memory error at a near memory location in response to a request to access a far memory location mapped to the near memory location; (FIG. 20, step 2002, receive an address associated with an incoming memory access request; [0137] far memory location is mapped to the near memory location; FIG 20, step 2006, parallel lookup is performed to check whether the address is in the faulty address list)
other far memory locations mapped to the same near memory ([0163] multiple far memory can be mapped to a near memory)
Yigzaw fails to teach, but Costa teaches
determining [the addresses that are affected by the error]; and offlining the far memory location and the other far memory locations mapped to the near memory location. (page 712, right column, bottom of the page, offlining error-prone page)
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the prior art because once a non-correctable error is found, offlining the affected pages can aid in avoiding the use of faulty memory (Costa, page 712, right column, bottom of the page).
Per claim 17, Yigzaw in view of Costa teaches
The non-transitory machine-readable medium of claim 16, wherein:
determining the other far memory locations includes: checking an address map, by firmware, for the other far memory locations mapped to the near memory location; and (Yigzaw, [0163] multiple far memory can be mapped to a near memory; [0146] firmware can be used to implement the handling of fault address list logic)
offlining the far memory location and the other far memory locations includes: providing, by the firmware, an error log to an operating system to identify the far memory location and the other far memory locations to trigger offlining pages at those locations in the far memory by the operating system. (Costa, page 712, the error is reported to the RAS infrastructure and logged to a database by the firmware handler; page 713, error can be handled by offlining affected pages at those far memory locations )
Per claim 18, Yigzaw in view of Costa teaches
The non-transitory machine-readable medium of claim 17, wherein:
offlining pages at those locations in the far memory by the operating system includes:
copying data at the far memory location and the other far memory locations to other locations in the far memory, and making the far memory location and the other far memory locations unavailable for access.
(Costa [page 713] Page migration is implemented in the following steps: (1) allocate a new page, …. (3) invalidate the Page Table Entry (PTE) descriptors pointing to the old page, and (4) copy page contents from the old page to the new page.)
Per claim 19, Yigzaw in view of Costa teaches
The non-transitory machine-readable medium of claim 16, wherein:
determining the other far memory locations includes: checking an address map, by an operating system, for the other far memory locations mapped to the near memory location; and (Yigzaw, [0129] a tag table is used to determine which data segments are included in the near memory; [0152] the operating system handles error logic for uncorrectable errors)
offlining the far memory location and the other far memory locations includes:
copying data at the far memory location and the other far memory locations to other locations in the far memory, and making the far memory location and the other far memory locations unavailable for access. (Costa [page 713] Page migration is implemented in the following steps: (1) allocate a new page, …. (3) invalidate the Page Table Entry (PTE) descriptors pointing to the old page, and (4) copy page contents from the old page to the new page.)
Per claim 20, Yigzaw in view of Costa teaches
The non-transitory machine-readable medium of claim 19,
Yigzaw in view of Costa fails to explicitly teach
determining a mapping ratio of near memory locations to far memory locations; and
determining a number of pages to offline based on the mapping ratio.
However, Costa teaches that when an error is detected through an interrupt, the PFN (page frame number) is calculated for the reported address which is used to calculate the number of pages to offline during page migration. Because the number of pages to offline is related to how many addresses to offline – i.e, if there are x number of far memory addresses mapped to the single near memory that is causing an uncorrectable error, then the PFN for each of those x number of far memory addresses would need to be calculated to determine a number of pages to offline – the number of pages to offline is based on the mapping ratio, and thus the determination of the mapping ratio is implicit within the process of page migration (Costa, page 711, right clumn).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ramanujan et al (Pub No. US 2014/0304475) teaches current memory and storage configurations including utilizing integrated memory controller (IMC) that is coupled to memory-side cache (MSC) controller for near memory access and a NVRAM controller to access NVRAM (which stores the far memory).
Guthrie et al (Pub No. US 2010/0268984) teaches determining a method to calculate the frequency of the correctable error to determine whether it is occurring too frequently or not.
Penton et al (Pub No. US 2009/0164727) teaches a data processing apparatus utilizing cache storage and address storage.
Gille et al (Pub No. US 2011/0047411) teaches utilizing a cache location avoid storage to store the cache record identifier for the accessed cache record upon detecting an error.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAYO LISA RUSIN whose telephone number is (703)756-1679. The examiner can normally be reached Monday-Friday 8:30 - 5:00 EST.
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/K.L.R./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
