DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Responsive to the communication dated 03/03/2023
Claims 1-11 are presented for examination
Information Disclosure Statement
The IDS dated 03/03/2023 and 05/15/2025 has been reviewed. See attached.
Drawings
The drawings dated 03/03/2023 have been reviewed. They are accepted.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Abstract
The abstract dated 03/03/2023 has been reviewed. It has 127 words, and contains no legal phraseology. It is accepted.
Claim Objections
The claims have numerous issues with antecedent basis and readability. The Examiner suggests amending the claims such that the first recitation of each distinct element uses articles such as “a”/”an”, later recitations referring back to the same distinct element use articles such as “the”/”said”, to use disambiguating modifiers (e.g., first, second, etc.) when there are multiple distinct elements with the same base term, and that the use of modifiers for each distinct element are kept consistent. Additionally, significant readability issues are present in the claims with excessively ambiguous or difficult-to-follow language Below is a non-exhaustive list of examples of these issues:
Claims 1 and 10-11 recite both “an element value” and “at least one value of a current value and a voltage value,” with the claim itself and later claims later reciting “the at least one value.” Along with the other “value” terms used in the claims, the term referring to the current or voltage value at the predetermined portion within the equivalent circuit being referred to as “the at least one value” makes keeping track of which values correspond to what difficult. It is recommended to rename this term, for example as “the at least one electrical value” or “the at least one I-V value corresponding to a current value or voltage value at a predetermined portion within the equivalent circuit;”
Claims 1 and 10-11 “a deterioration degree of an electric characteristic of the transistor…” It is clear from the specification that this does not actually refer to an electrical characteristic and rather refers to a predicted lifetime of the transistor ([Par 51] “The deterioration degree of the electrical characteristic is, for example, a lifetime (e.g., mean time to failure (MTTF)) at an operating temperature of the transistor.”) While the applicant may act as their own lexicographer and freely redefine terms so long as they are sufficiently explained to be redefined in the speciation, it is highly recommended to amend to swap the term “a deterioration degree of an electric characteristic of the transistor” for a more fitting term, such as “a lifetime of the transistor,” as the current language hampers readability.
Claim 2 recites “…determines whether the calculated deterioration degree is the desired deterioration degree…” when checking for the second time after adjustments. As this clearly refers to the newly calculated degree rather than the deterioration degree introduced in claim 1. To avoid protentional issues with antecedent basis, it is recommended to identify this second calculated degree with a modifier such as “second.”
Claim 3 recites “a current source and a voltage value across both ends of the current source…” That the current source has an “end,” let alone two, was not previously introduced. To avoid protentional issues with antecedent basis, it is recommended to introduce these ends prior to this recitation of “both ends” or alternatively refer to these ends as “across a first and second end of the current source…”
Claim 4 recites “the first value being at least one of a voltage value and a current value at a first end portion at which a load line has a minimum voltage value in a current- voltage characteristic for a current value at an end of a current source and a voltage value across both ends of the current source within the equivalent circuit.” This limitation is structured very confusingly and does not properly articulate which elements are alternative to each other and which elements are part of the same alternative, i.e. which must go together.
Further, to the same limitation of claim 4 above, the phrasing of “…at a first end portion at which a load line has a minimum voltage value” does not clearly convey the intended interpretation, i.e. that the voltage/current value is taken at a first end portion when the load line has a minimum voltage value, rather than the end physically moving based on load line voltage.
The same suggestion above also applies to the claim 4 limitation “the second value being at least one of a voltage value and a current value at a second end portion at which the load line has a maximum voltage value”
Claim 4 recites “in calculating of the deterioration degree, the processor calculates, based on the at least two values, at least two deterioration degrees…” However, claim 1 recites the deterioration degree with language that specifies only one degree is calculated (i.e. “a deterioration degree of an electric characteristic of the transistor”) It is recommended to amend the claims to properly include the possibility of plurality to avoid potential issues with antecedent basis, such as by introducing deterioration degrees as “at least one” in the independent claims.
Claim 6 recites “in calculating of the deterioration degree, the processor calculates, … three deterioration degrees…” However, claim 1 recites the deterioration degree with language that specifies only one degree is calculated (i.e. “a deterioration degree of an electric characteristic of the transistor”) It is recommended to amend the claims to properly include the possibility of plurality to avoid potential issues with antecedent basis, such as by introducing deterioration degrees as “at least one” in the independent claims.
Claim 8 recites “a current value” and later “the current value.” However, several of the claims on which claim 8 depends also recite “a current value.” To avoid potential issues with antecedent basis, it is suggested to give each recitation a unique identifier; e.g. the current value introduced in claim 8 in reference to the diode could be referred to as a “diode current.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-8 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the phrase “the processor calculates at least two values of a first value, a second value, and a third value.” renders the claim indefinite because it is unclear which limitation(s) are part of the claimed invention. See MPEP § 2173.05(d). It is somewhat ambiguous how many values are actually being calculated here, as this language could mean that two values each of the first, second, and third value are being calculated, i.e. a total of 6 values, or two values out of the first, second, and third value are being calculated, i.e. a total of 2 values are required, such as a value for the first value and a value for a second value. For the purposes of this examination, this is interpreted as meaning that two values out of the first, second, and third value are being calculated.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-11 are rejected under 35 U.S.C. 101 because they are directed to an abstract idea without significantly more.
Claim 1 (Statutory Category – Process)
Step 2A – Prong 1: Judicial Exception Recited?
Yes, the claim recites a mental process, specifically:
MPEP 2106.04(a)(2)(Ill): “Accordingly, the "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, Judgments, and opinions.”
Further, the MPEP recites “The courts do not distinguish between mental processes that are performed entirely in the human mind and mental processes that require a human to use a physical aid (e.g., pen and paper or a slide rule) to perform the claim limitation.”
if the calculated radio frequency characteristic of the amplifier circuit is a desired characteristic, …
Determining if a calculated quantity matches a desired value for that quantity is a mental process equivalent to observing both the calculated quantity and the desired value, and judging whether the numbers match. For example, if a desired power level is 30dBm and the calculated radio frequency characteristic is a power level of 30dBm, a person could reasonably mentally compare the values and determine that the desired level has been reached.
The claim also recites a mathematic concept, specifically:
in an amplifier circuit including an input terminal to which a radio frequency signal is input, a transistor configured to amplify the input radio frequency signal, an output terminal from which the amplified radio frequency signal is output, and a matching circuit connected between the transistor and the output terminal, calculate, based on an element value of the matching circuit and using an equivalent circuit of the transistor, a radio frequency characteristic of the amplifier circuit;
Performing this operation is a combination mental process/mathematic concept. Creating an equivalent circuit of a transistor is a mental process equivalent to creating a circuit diagram representative of the features of that transistor e.g. using a pencil and paper. This kind of circuit decomposition and analysis is common amongst electronics designers and electrical engineers. Further, this diagram could be extended to include the matching circuit, terminals, etc.
Given this representation, which provides the electrical features of the circuit (i.e. voltages across components, amperages, impedances, etc.), mathematically calculating a particular value using this data, such as a radio frequency characteristic of the amplifier circuit, merely amounts to a mathematic calculation, and is therefore merely a mathematic concept.
calculate, based on the element value and using the equivalent circuit, at least one value of a current value and a voltage value at a predetermined portion within the equivalent circuit; and
Mathematically calculating a voltage or current value in such a manner amounts to no more than a mathematic calculation, and is therefore merely a mathematic concept.
calculate, based on the at least one value and using data in which the at least one value and a deterioration degree of an electric characteristic of the transistor are associated with each other, the deterioration degree of the electric characteristic of the transistor.
Mathematically calculating a deterioration value in such a manner amounts to no more than a mathematic calculation, and is therefore merely a mathematic concept.
Step 2A – Prong 2: Integrated into a Practical Solution?
Insignificant Extra-Solution Activity (MPEP 2106.05(g)) has found mere data gathering and post solution activity to be insignificant extra-solution activity.
Data gathering:
in an amplifier circuit including an input terminal to which a radio frequency signal is input, a transistor configured to amplify the input radio frequency signal, an output terminal from which the amplified radio frequency signal is output, and a matching circuit connected between the transistor and the output terminal, calculate, based on an element value of the matching circuit…
Obtaining information from the circuit, such as electrical characteristics and component values, recited at such a high level of generality and without any specificity as to how these values are actually obtained, amounts to no more than mere data gathering.
Note that the calculation of data based on these values is a mathematic concept, as analyzed above.
Moreover, Mere Instructions To Apply An Exception (MPEP 2106.05(f)) has found that simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. In light of this, the additional generic computer component elements of “A calculation device comprising: a memory; and a processor coupled to the memory, the processor being configured to:…” are not sufficient to integrate a judicial exception into a practical application nor provide evidence of an inventive concept.
Step 2B: Claim provides an Inventive Concept?
No, as discussed with respect to Step 2A, the additional limitations are Insignificant Extra-Solution Activity and Mere Instructions To Apply and do not impose any meaningful limits on practicing the abstract idea and therefore the claim does not provide an inventive concept in Step 2B.
Insignificant Extra-Solution Activity (MPEP 2106.05(g)) has found mere data gathering and post solution activity to be insignificant extra-solution activity.
Data gathering:
in an amplifier circuit including an input terminal to which a radio frequency signal is input, a transistor configured to amplify the input radio frequency signal, an output terminal from which the amplified radio frequency signal is output, and a matching circuit connected between the transistor and the output terminal, calculate, based on an element value of the matching circuit…
Obtaining information from the circuit, such as electrical characteristics and component values, recited at such a high level of generality and without any specificity as to how these values are actually obtained, amounts to no more than mere data gathering.
Note that the calculation of data based on these values is a mathematic concept, as analyzed above.
A claim element that amounts to merely gathering data is not indicative of integration into a practical solution nor evidence that the claim provides an inventive concept or significantly more, as exemplified by ((MPEP 2106.05)(g)(Mere Data Gathering) i. Performing clinical tests on individuals to obtain input for an equation, In re Grams, 888 F.2d 835, 839-40; 12 USPQ2d 1824, 1827-28 (Fed. Cir. 1989); iv. Obtaining information about transactions using the Internet to verify credit card transactions, CyberSource v. Retail Decisions, Inc., 654 F.3d 1366, 1375, 99 USPQ2d 1690, 1694 (Fed. Cir. 2011);
Moreover, Mere Instructions To Apply An Exception (MPEP 2106.05(f)) has found that simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. In light of this, the additional generic computer component elements of “A calculation device comprising: a memory; and a processor coupled to the memory, the processor being configured to:…” are not sufficient to integrate a judicial exception into a practical application nor provide evidence of an inventive concept.
The additional elements have been considered both individually and as an ordered combination in the consideration of whether they constitute significantly more, and have been determined not to constitute such.
The claim is ineligible.
Claim 10. The elements of claim 10 are substantially the same as those of claim 1. Therefore, the elements of claim 10 are rejected due to the same reasons as outlined above for claim 1.
Claim 11. The elements of claim 11 are substantially the same as those of claim 1. Therefore, the elements of claim 11 are rejected due to the same reasons as outlined above for claim 1.
Moreover, Mere Instructions To Apply An Exception (MPEP 2106.05(f)) has found that simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. In light of this, the additional generic computer component elements of “A non-transitory computer-readable recording medium storing a program that causes a computer to execute a process, the process comprising:…” are not sufficient to integrate a judicial exception into a practical application nor provide evidence of an inventive concept.
Claim 2 recites “wherein the processor determines whether the calculated deterioration degree is a desired deterioration degree, and if it is determined that the calculated deterioration degree is not the desired deterioration degree , the processor changes the element value, calculates, based on the changed element value, the radio frequency characteristic, calculates the at least one value, calculates the deterioration degree, and determines whether the calculated deterioration degree is the desired deterioration degree.”
Determining if a calculated quantity matches a desired value for that quantity is a mental process equivalent to observing both the calculated quantity and the desired value, and judging whether the numbers match.
Changing a value of a particular feature of a circuit component within a diagram is a mental process equivalent to redrawing or rewriting the details of the diagram indicating those features. For example, if an inductor in the matching circuit has an indicated inductance of 20mH, changing this to 40mH is merely equivalent to erasing the “20mH” and replacing it with “40mH,” as well as carrying this change over to any further calculations using the inductance of that inductor.
Mathematically calculating numeric values, such as the radio frequency characteristic, at least one value, deterioration degree, etc. amounts to no more than a mathematic concept. See (MPEP 2106.04(a)(2)(I)(C) “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation such as exponentiation.”)
Once again determining if the new deterioration degree matches the desired degree a mental process equivalent to observing both the newly calculated degree and the desired degree, and judging whether the numbers match.
Claim 3 recites “wherein, in calculating of at least one value, the processor calculates at least one value of a current value at an end of a current source and a voltage value across both ends of the current source within the equivalent circuit as the at least one value.”
Mathematically calculating numeric values, such as the current at a particular point in a circuit of the voltage across a component amounts to no more than a mathematic concept. See (MPEP 2106.04(a)(2)(I)(C) “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation such as exponentiation.”)
Claim 4 recites “wherein, in calculating of at least one value, the processor calculates at least two values of a first value, a second value, and a third value, the first value being at least one of a voltage value and a current value at a first end portion at which a load line has a minimum voltage value in a current- voltage characteristic for a current value at an end of a current source and a voltage value across both ends of the current source within the equivalent circuit, the second value being at least one of a voltage value and a current value at a second end portion at which the load line has a maximum voltage value, the third value being at least one of a direct current component and a direct voltage component in the load line, and, in calculating of the deterioration degree, the processor calculates, based on the at least two values, at least two deterioration degrees of the electric characteristic of the transistor, respectively.”
Mathematically calculating numeric values, such as current or voltage under certain conditions or deterioration degree amounts to no more than a mathematic concept. See (MPEP 2106.04(a)(2)(I)(C) “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation such as exponentiation.”)
Claim 5 recites “wherein, in calculating of the deterioration degree, the processor calculates, as the deterioration degree of the electric characteristic of the transistor, a worst deterioration degree of the electric characteristic of the at least two deterioration degrees of the electric characteristic.”
Mathematically calculating numeric values, such as deterioration degree amounts to no more than a mathematic concept. See (MPEP 2106.04(a)(2)(I)(C) “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation such as exponentiation.”)
Claim 6 recites “wherein, in calculating of at least one value, the processor calculates the first value, the second value, and the third value, and, in calculating of the deterioration degree, the processor calculates, based on the first value, the second value, and the third value, three deterioration degrees of the electric characteristic of the transistor, respectively.”
This merely clarifies that all three values are calculated rather than “at least two values” out of the three. As such, this is merely an extension of the mathematic concept.
Claim 7 recites “wherein the transistor is a field effect transistor (FET) having a gate connected to the input terminal and a drain connected to the matching circuit, and the current source is a drain current source within the FET.”
This merely further clarifies the structure of the circuit, and therefore is merely an extension of the mental process, mathematic concept, and mere data gathering.
Claim 8 recites “wherein, in calculating of at least one value, the processor calculates a fourth value that is at least one of a current value and a voltage value, the current value being a current value at an end of at least one diode of a diode between the gate and a source and a diode between the gate and the drain within the equivalent circuit, the voltage value being a voltage value across both ends of the at least one diode, and, in calculating of the deterioration degree, the processor calculates, based on the fourth value, a deterioration degree of an electric characteristic of the FET.
Mathematically calculating numeric values, such as current or voltage at a particular point or across a particular component, or deterioration degree, amounts to no more than a mathematic concept. See (MPEP 2106.04(a)(2)(I)(C) “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation such as exponentiation.”)
Claim 9 recites “wherein the calculation device acquires an operation temperature of the transistor, and, in calculating of the deterioration degree of the electric characteristic of the transistor, the processor calculates, based on the at least one value and the operation temperature and using data in which the at least one value, the operation temperature, and the deterioration degree of the electric characteristic of the transistor are associated with each other, the deterioration degree of the electric characteristic of the transistor.”
Acquiring an operation temperature of a transistor, recited at a such a high level of generality and without any specificity as to how this temperature is actually acquired, amounts to no more than mere data gathering.
Mathematically calculating numeric values, such as a deterioration degree, amounts to no more than a mathematic concept. See (MPEP 2106.04(a)(2)(I)(C) “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation such as exponentiation.”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
(1) Claims 1-3, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Tanomura (JP 2010257043 A) in view of Model-Based GaN PA Design Basics: The What and Why of Intrinsic I-V Waveforms (Hereinafter Qorvo)
Claim 1. Tanomura teaches A calculation device comprising: a memory; and a processor coupled to the memory, the processor being configured to: in an amplifier circuit ([Page 2 Par 12- 18] “The simulation system of the present embodiment is a circuit simulator realized by a computer that operates according to a program, and is used for designing a high-frequency power amplifier. … includes a transistor model input unit 111, a transistor model parameter input unit 112, a reliability information input unit 113, and an operating voltage input unit 14. The simulation unit 12 includes an output power simulation unit 121 and a life simulation unit 122. Hereinafter, a simulation method by the simulation system of the present embodiment will be described with reference to FIG. As shown in FIG. 2, first, in step A1, a transistor model is input to the transistor model input unit 111. Subsequently, in step A2, a transistor model parameter is input to the transistor model parameter input unit 112. The transistor model is a general transistor model such as BSIM (Berkeley Short-channel IGFET Model, IGFET = Insulated-Gate Field-Effect Transistor) or HiSIM (Hiroshima-university STARC IGFET Model, STARC = Semiconductor Technology Academic Research Center).” [Page 4 Par 3] “The simulation system of the present embodiment is a circuit simulator realized by a computer that operates according to a program, and is used for designing a high-frequency power amplifier.”) an output terminal from which the amplified ([Page 3 Par 8] “Next, in step A5, the output power simulation unit 121 refers to the transistor model, the transistor model parameter, and the operating voltage, calculates the output power of the transistor by changing the load impedance of the matching circuit of the transistor, and calculates the result. This is supplied to the display unit 13.”) and a matching circuit ([Page 3 Par 10] “The matching circuit is a circuit configured using one or more resistors, capacitors, inductors, and transmission lines.”) ([Abstract] “a simulation unit that refers to the transistor model, the transistor model parameter, and the operating voltage to calculate the output power of the transistor by changing the load impedance of a matching circuit of the transistor” [Page 4 Par 15] “Next, in step B7, the output power simulation unit 221 refers to the transistor model, transistor model parameters, matching circuit information, and operating voltage, calculates the output power of the transistor, and supplies the result to the display unit 23.” [Page 2 Par 18] “The transistor model is a general transistor model such as BSIM (Berkeley Short-channel IGFET Model, IGFET = Insulated-Gate Field-Effect Transistor) or HiSIM (Hiroshima-university STARC IGFET Model, STARC = Semiconductor Technology Academic Research Center).” [Examiner’s note: a BSIM transistor model is a type of equivalent circuit model]) ([Page 4 Par 15] “Next, in step B7, the output power simulation unit 221 refers to the transistor model, transistor model parameters, matching circuit information, and operating voltage, calculates the output power of the transistor, and supplies the result to the display unit 23.” ([Page 4 Par 8] “In B3, the desired output power value Ps of the high frequency power amplifier is input to the amplifier target performance input unit 213, and subsequently, the matching circuit information of the transistor is input to the matching circuit information input unit 214 in Step B4.”) ([Abstract] “a simulation unit that refers to the transistor model, the transistor model parameter, and the operating voltage to calculate the output power of the transistor by changing the load impedance of a matching circuit of the transistor”) and using the equivalent circuit, ([Page 2 Par 18] “The transistor model is a general transistor model such as BSIM (Berkeley Short-channel IGFET Model, IGFET = Insulated-Gate Field-Effect Transistor) or HiSIM (Hiroshima-university STARC IGFET Model, STARC = Semiconductor Technology Academic Research Center).” [Examiner’s note: a BSIM transistor model is a type of equivalent circuit model])at least one value of a current value and a voltage value at a predetermined portion within the equivalent circuit; and calculate, based on the at least one value and using data in which the at least one value and a deterioration degree of an electric characteristic of the transistor are associated with each other, the deterioration degree of the electric characteristic of the transistor. (([Page 3 Par 1-3] “The reliability information is information depending on the transistor structure, and is, for example, a relational expression between the voltage applied to the transistor and the lifetime. The reliability information may be a relational expression between the substrate current and the lifetime of the transistor. By using the relational expression between the transistor substrate current and the lifetime, the lifetime of the CMOS due to the HCI can be easily and accurately calculated. This is because the lifetime of the CMOS has a strong correlation with the substrate current. The relational expression between the substrate current and the lifetime is, for example, lifetime = α × (substrate current) β. However, α and β are parameters depending on the transistor structure.” [Page 4 Par 16-17] “On the other hand, in step B8, the lifetime simulation unit 222 refers to the transistor model, transistor model parameters, matching circuit information, operating voltage, and reliability information, calculates the lifetime of the transistor, and supplies the result to the display unit 23. . Next, the display part 23 displays the output power and lifetime of a transistor on a Smith chart figure in step B9, and supplies the result to the determination part 24. FIG” [Examiner’s note: the specification clarifies that “a deterioration degree of an electric characteristic of the transistor” refers to a general lifetime metric of the transistor, not to any change in any particular characteristic of the transistor due to aging. [Par 51] “Computer 20 calculates the deterioration degree of the electrical characteristic of the transistor based on the data. The deterioration degree of the electrical characteristic is, for example, a lifetime (e.g., mean time to failure (MTTF))”] [Page 2 Par 18] “The transistor model is a general transistor model such as BSIM (Berkeley Short-channel IGFET Model, IGFET = Insulated-Gate Field-Effect Transistor) or HiSIM (Hiroshima-university STARC IGFET Model, STARC = Semiconductor Technology Academic Research Center).” [Examiner’s note: a BSIM transistor model is a type of equivalent circuit model])
Tanomura does not explicitly teach an amplifier circuit including an input terminal to which a radio frequency signal is input, a transistor configured to amplify the input radio frequency signal, an output terminal from which the amplified radio frequency signal is output, and a matching component connected between the transistor and the output terminal; calculate a radio-frequency characteristic of the amplifier circuit; if the calculated radio frequency characteristic of the amplifier circuit is a desired characteristic, calculate, based on a matching circuit element value, at least one value of a current value and a voltage value.
Qorvo teaches an amplifier circuit including an input terminal to which a radio frequency signal is input, a transistor configured to amplify the input radio frequency signal, an output terminal from which the amplified radio frequency signal is output, and a matching component connected between the transistor and the output terminal; ([Page 10 Par 2] “Harmonic Tuning to Illustrate Waveform Engineering for Class F Design: The following figure shows the schematic setup used to simulate intrinsic and extrinsic waveforms as well as power and efficiency under swept input power at a 2 GHz fundamental frequency. These simulations were performed using NI AWR and the Modelithics Qorvo GaN Library model for QPD0060.” [Page 11 Figure] Shows a schematic for an amplifier circuit that includes: an input terminal for a radio frequency signal that is input to a transistor (See component labeled {P=1} at the left of the figure. Note that the previous paragraph describing the figure explains that the input is a 2GHz frequency, which is an RF frequency. {Port1} is connected to the input of amplifier transistor {S1} through first matching component {SourceTuner1}), an output terminal to output the amplified signal (see the second port labeled {P=2} at the right of the figure), and a matching component between the transistor and the output terminal (see the matching component labeled {LoadTuner1} connected between the drain of the transistor {S1} and the output terminal {P=2})
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calculate a radio-frequency characteristic of the amplifier circuit; ([Page 10 Par 2] “Harmonic Tuning to Illustrate Waveform Engineering for Class F Design: The following figure shows the schematic setup used to simulate intrinsic and extrinsic waveforms as well as power and efficiency under swept input power at a 2 GHz fundamental frequency” [Examiner’s note: this passage is describing the above figure on page 11]) if a calculated radio frequency characteristic of the amplifier circuit is a desired characteristic, calculate, based on a matching circuit element value, at least one value of a current value and a voltage value. ([Page 7 Par 1-5] “But what if your intrinsic waveforms don’t reflect the desired I‐V waveforms for your operating class? Harmonic tuning may be the answer. All of the Modelithics Qorvo GaN Library models allow the circuit designer to monitor the intrinsic voltage and current waveforms while tuning or optimizing the load matching circuit until the desired waveform shaping is achieved. This is sometimes called the “waveform engineering” approach to PA design. To demonstrate this concept of waveform engineering, the next figure shows power sweep results for the intrinsic I‐V waveforms both before and after harmonic tuning. Compared to the initial Class F waveform plots shown in the previous section, I tuned the fundamental load impedance to optimize efficiency to a value of 71.5%. When comparing the bottom two plots, note the following: We see nine points of improved efficiency to 80.5% after also tuning the third harmonic and “squaring the voltage.” The efficiency improvement was done at no change to the achieved power level of 34.9 dBm” [Page 8 Figures] Show the current and voltage curves of the transistor before and after tuning the load matching circuit)
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Qorvo is analogous art because it is within the field of RF amplifier design and optimization. It would have been obvious to one of ordinary skill in the art to combine Qorvo with Tanomura before the effective filing date. One of ordinary skill in the art would have been motivated to make this combination in order to better capture the behaviors of the designed amplifier, specifically to better capture the behavior at intrinsic ports, locations within the transistor itself. Qorvo notes the importance of location when simulating and optimizing amplifier circuits, particularly the importance of being able to accurately simulate at intrinsic rather than extrinsic ports. ([Page 5 Par 4 – 6] “The previous figure showed the waveforms for ideal PA classes. But there’s a catch: It makes a difference where you effectively simulate the I‐V waveforms — at the intrinsic or extrinsic port. It matters because of the device’s parasitics, which could include pad capacitances, bond wires, package parasitics and other factors that impact the performance and design of the device. The next figure and table illustrate the difference between intrinsic and extrinsic gate, drain and source ports.” [Page 5 Table])
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It should be noted that the measurement of intrinsic vs extrinsic ports within the circuit is not discussed in Tanomura. To this end, Qorvo presents a simulation system that allows for simulation at intrinsic ports and demonstrates the use of such intrinsic waveform simulation to produce improved amplifier designs using their software ([Page 8 Par 1-8] “The takeaway: Simulate at intrinsic nodes to maximize your GaN PA design In summary, extrinsic waveforms aren’t useful for design because they aren’t constrained by the limits of the I‐V curves — and it is precisely these current/voltage constraints that determine the power capability of a device at a given set of bias/current/matching conditions. It’s better to simulate I‐V waveforms for your design at the intrinsic ports. Simulating the intrinsic I‐V waveforms is key to: Optimizing matching networks Compensating for distortions caused by device parasitics Achieving optimal power and efficiency Attaining first-pass design success You can then use waveform engineering to further fine-tune the design and performance of your device for your specific application.” [Page 7 Par 1-5] “But what if your intrinsic waveforms don’t reflect the desired I‐V waveforms for your operating class? Harmonic tuning may be the answer. All of the Modelithics Qorvo GaN Library models allow the circuit designer to monitor the intrinsic voltage and current waveforms while tuning or optimizing the load matching circuit until the desired waveform shaping is achieved. This is sometimes called the “waveform engineering” approach to PA design. To demonstrate this concept of waveform engineering, the next figure shows power sweep results for the intrinsic I‐V waveforms both before and after harmonic tuning. Compared to the initial Class F waveform plots shown in the previous section, I tuned the fundamental load impedance to optimize efficiency to a value of 71.5%. When comparing the bottom two plots, note the following: We see nine points of improved efficiency to 80.5% after also tuning the third harmonic and “squaring the voltage.” The efficiency improvement was done at no change to the achieved power level of 34.9 dBm” [Page 8 Figures] Show the current and voltage curves of the transistor before and after tuning the load matching circuit) Overall, one of ordinary skill in the art would have recognized that combining Qorvo with Tanomura would result in a more detailed amplifier analysis and optimization process, ultimately leading to better, more efficient designs.
Claim 10. The elements of claim 10 are substantially the same as those of claim 1. Therefore, the elements of claim 10 are rejected due to the same reasons as outlined above for claim 1.
Claim 11. The elements of claim 11 are substantially the same as those of claim 1. Therefore, the elements of claim 11 are rejected due to the same reasons as outlined above for claim 1. Further, Tanomura makes obvious the additional elements of “A non-transitory computer-readable recording medium storing a program that causes a computer to execute a process, the process comprising:” ([Page 2 Par 12] “The simulation system of the present embodiment is a circuit simulator realized by a computer that operates according to a program, and is used for designing a high-frequency power amplifier”)
Claim 2. Tanomura teaches wherein the processor determines whether the calculated deterioration degree is a desired deterioration degree, and if it is determined that the calculated deterioration degree is not the desired deterioration degree, the processor changes the element value, ([Page 5 Par 1-2] “Thereafter, in step B10, the determination unit 24 determines whether or not the desired output power value Ps exists in the load impedance region that satisfies the life based on the output power and life of the transistor displayed on the display unit 23. The determination unit 24 ends the simulation when the desired output power Ps exists in the load impedance region where the lifetime can be obtained. On the other hand, when the desired output power Ps does not exist in the load impedance region where the lifetime can be obtained, the determination unit 24 returns to the process of step B3 and thereafter re-inputs the value of Ps, the matching circuit information, and the operating voltage.” [Abstract] “a simulation unit that refers to the transistor model, the transistor model parameter, and the operating voltage to calculate the output power of the transistor by changing the load impedance of a matching circuit of the transistor, and refers to the transistor model, the transistor model parameter, the operating voltage, and the reliability information to calculate the life of the transistor by changing the load impedance of the matching circuit of the transistor;” [If the life requirement (i.e. the desired deterioration degree) is not met given the output power, change circuit features such as the load impedance of the matching circuit and re-evaluate]) calculates, based on the changed element value, the ([Page 4 Par 15] “Next, in step B7, the output power simulation unit 221 refers to the transistor model, transistor model parameters, matching circuit information, and operating voltage, calculates the output power of the transistor, and supplies the result to the display unit 23.”) ([Page 4 Par 16-17] “On the other hand, in step B8, the lifetime simulation unit 222 refers to the transistor model, transistor model parameters, matching circuit information, operating voltage, and reliability information, calculates the lifetime of the transistor, and supplies the result to the display unit 23. . Next, the display part 23 displays the output power and lifetime of a transistor on a Smith chart figure in step B9, and supplies the result to the determination part 24. FIG”) determines whether the calculated deterioration degree is the desired deterioration degree. ([Page 5 Par 1-2] “Thereafter, in step B10, the determination unit 24 determines whether or not the desired output power value Ps exists in the load impedance region that satisfies the life based on the output power and life of the transistor displayed on the display unit 23. The determination unit 24 ends the simulation when the desired output power Ps exists in the load impedance region where the lifetime can be obtained. On the other hand, when the desired output power Ps does not exist in the load impedance region where the lifetime can be obtained, the determination unit 24 returns to the process of step B3 and thereafter re-inputs the value of Ps, the matching circuit information, and the operating voltage.”)
Qorvo makes obvious calculates, based on the changed element value, the radio frequency characteristic, calculates the at least one value ([Page 7 Par 1-5] “But what if your intrinsic waveforms don’t reflect the desired I‐V waveforms for your operating class? Harmonic tuning may be the answer. All of the Modelithics Qorvo GaN Library models allow the circuit designer to monitor the intrinsic voltage and current waveforms while tuning or optimizing the load matching circuit until the desired waveform shaping is achieved. This is sometimes called the “waveform engineering” approach to PA design. To demonstrate this concept of waveform engineering, the next figure shows power sweep results for the intrinsic I‐V waveforms both before and after harmonic tuning. Compared to the initial Class F waveform plots shown in the previous section, I tuned the fundamental load impedance to optimize efficiency to a value of 71.5%. When comparing the bottom two plots, note the following: We see nine points of improved efficiency to 80.5% after also tuning the third harmonic and “squaring the voltage.” The efficiency improvement was done at no change to the achieved power level of 34.9 dBm” [Page 8 Figures] Show the current and voltage curves of the transistor before and after tuning the load matching circuit)
Claim 3. Tanomura teaches ([Page 2 Par 12] “The simulation system of the present embodiment is a circuit simulator realized by a computer that operates according to a program, and is used for designing a high-frequency power amplifier”) ([Page 2 Par 18] “The transistor model is a general transistor model such as BSIM (Berkeley Short-channel IGFET Model, IGFET = Insulated-Gate Field-Effect Transistor) or HiSIM (Hiroshima-university STARC IGFET Model, STARC = Semiconductor Technology Academic Research Center).” [Examiner’s note: a BSIM transistor model is a type of equivalent circuit model])
Qorvo makes obvious wherein, in calculating of at least one value, the system calculates at least one value of a current value at an end of a current source and a voltage value across both ends of the current source within the circuit as the at least one value. ([Page 11 Figure] Shows a simulated current meter connected to the drain of the transistor i.e. at the end of a current source)
Claim 9. Tanomura teaches wherein the calculation device acquires an operation temperature of the transistor, and, in calculating of the deterioration degree of the electric characteristic of the transistor, the processor calculates, based on the at least one value and the operation temperature and using data in which the at least one value, the operation temperature, and the deterioration degree of the electric characteristic of the transistor are associated with each other, the deterioration degree of the electric characteristic of the transistor. ([Page 3 Par 4-5] “The reliability information may be a relational expression between the junction temperature and the lifetime of the transistor. By using the relational expression between the junction temperature and the lifetime of the transistor, it is possible to calculate the lifetime of not only a CMOS but also a semiconductor such as GaAs or GaN. The relational expression between the junction temperature and the lifetime is, for example, lifetime = a × exp (b / junction temperature). However, a and b are parameters depending on the transistor structure.”)
(2) Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Tanomura (JP 2010257043 A) in view of Model-Based GaN PA Design Basics: The What and Why of Intrinsic I-V Waveforms (Hereinafter Qorvo) in further view of Long-Term Degradation Effects in Power Amplifiers: Analysis, Modelling and Remedies (Hereinafter Eslahi)
Claim 4. Tanomura teaches ([Page 2 Par 12] “The simulation system of the present embodiment is a circuit simulator realized by a computer that operates according to a program, and is used for designing a high-frequency power amplifier”) ([Page 2 Par 18] “The transistor model is a general transistor model such as BSIM (Berkeley Short-channel IGFET Model, IGFET = Insulated-Gate Field-Effect Transistor) or HiSIM (Hiroshima-university STARC IGFET Model, STARC = Semiconductor Technology Academic Research Center).” [Examiner’s note: a BSIM transistor model is a type of equivalent circuit model]) (([Page 3 Par 1-3] “The reliability information is information depending on the transistor structure, and is, for example, a relational expression between the voltage applied to the transistor and the lifetime. The reliability information may be a relational expression between the substrate current and the lifetime of the transistor. By using the relational expression between the transistor substrate current and the lifetime, the lifetime of the CMOS due to the HCI can be easily and accurately calculated. This is because the lifetime of the CMOS has a strong correlation with the substrate current. The relational expression between the substrate current and the lifetime is, for example, lifetime = α × (substrate current) β. However, α and β are parameters depending on the transistor structure.” [Page 4 Par 16-17] “On the other hand, in step B8, the lifetime simulation unit 222 refers to the transistor model, transistor model parameters, matching circuit information, operating voltage, and reliability information, calculates the lifetime of the transistor, and supplies the result to the display unit 23. . Next, the display part 23 displays the output power and lifetime of a transistor on a Smith chart figure in step B9, and supplies the result to the determination part 24. FIG”)
Qorvo makes obvious wherein, in calculating of at least one value, the system calculates at least two values of a first value, a second value, and a third value, the first value being at least one of a voltage value and a current value at a first end portion at which a load line has a minimum voltage value in a current- voltage characteristic for a current value at an end of a current source and a([Page 5 Figure] Shows the ports at which I-V (current and voltage) data can be simulated. [Page 5 Par 7] “The next figure and table illustrate the difference between intrinsic and extrinsic gate, drain and source ports” [Page 6 Figure] Shows a graph of the I-V characteristics at the intrinsic and extrinsic drain ports, including the values of both current and voltage when voltage is at a minimum and maximum value. It is clear from the figure that many voltage and current values are calculated. Further, while the example graph is measured from the drain, it is clear based on the preceding paragraphs [Page 5 Par 7 – Page 6 Par 1] and particularly [Page 5 Figure] which shows measuring locations that the system can also perform measurements at the intrinsic and extrinsic source and gate ports [Page 3 Figure] Shows an I-V curve for Vds and Ids, i.e. the voltage and current across the drain and source, i.e. the current and voltage values across both ends of the current source)
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the third value being at least one of a direct current component and a direct voltage component in the load line, and ([Page 2 Par 6] “Three of the most basic classes are Class A, Class AB and Class B. As shown in the following figure, these modes correspond to biasing the transistor at the quiescent voltage-current points indicated by markers m2, m3 and m4 for PA classes A, AB and B, respectively” [Page 3 Figure] The figure also shows the quiescent voltage-current points on the various load lines, which are the points where the circuit is under DC conditions) ([Page 5 Figure] Shows the ports at which I-V (current and voltage) data can be simulated. [Page 5 Par 7] “The next figure and table illustrate the difference between intrinsic and extrinsic gate, drain and source ports” [Page 6 Figure] Shows a graph of the I-V characteristics at the intrinsic and extrinsic drain ports, including the values of both current and voltage when voltage is at a minimum and maximum value. Further, while the example graph is measured from the drain, it is clear based on the preceding paragraphs [Page 5 Par 7 – Page 6 Par 1] and particularly [Page 5 Figure] which shows measuring locations that the system can also perform measurements at the intrinsic and extrinsic source and gate ports [Page 3 Figure] Shows an I-V curve for Vds and Ids, i.e. the voltage and current across the drain and source, i.e. the current and voltage values across both ends of the current source)
The combination of Tanomura and Qorvo does not explicitly teach calculates, based at least two voltage or current values, at least two deterioration degrees of the electric characteristic of the transistor, respectively.
Eslahi makes obvious calculates, based on at least two voltage or current values, at least two deterioration degrees of the electric characteristic of the transistor, respectively. ([Figure 4.6] Shows a plot of various calculated age values, i.e. deterioration degrees, based on a varied series of voltages under RF conditions. Each position along the x axis of the graph can be considered a different deterioration degree corresponding to a respective voltage [Figure 4.5] Shows a similar plot, but under DC conditions.)
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Eslahi is analogous art because it is within the field of RF amplifier degradation and lifetime prediction. It would have been obvious to one of ordinary skill in the art to combine it with Tanomura and Qorvo before the effective filing date. One of ordinary skill in the art would have been motivated to make this combination in order to better predict rf amplifier reliability and design more reliable amplifiers. Firstly, Eslahi notes the importance of ensuring RF systems are maximally reliable due to many of the life-saving systems that rely on their operation. ([Page 2 Par 4 – Page 3 Par 1] “The automotive industry has recently become one of the main areas for making use of RF integrated circuits (RFICs). Almost all electrical systems in smart cars, such as engine controllers, air bags and assistance systems utilise ICs. In addition, safety and convenience are two important issues that should be met in this new generation of cars so automotive electronics requires a high level of reliability. Air bags, for instance, are critical for occupant safety, making their reliability vital. This problem becomes more critical when an inordinate number of cars are fabricated annually and a simple failure in device operation, induced by ageing and/or stress, may cause heavy economic-loss. Clearly, considering device and circuit reliability during the design process can enhance the quality of products and decrease the economic losses. Besides, since there is little research in the field of circuit reliability modelling, it seems clear that much further research is needed on this topic.”) Further, Eslahi notes the limitations of previous prediction systems and the need for improved systems that take aspects ignored by the previous ones into account ([Page 27 Par 1] “Of all RF circuits, the power amplifier is more vulnerable to degradation because of its high peak output voltages, and degradation of a PA, being a main part of a transceiver chain, can affect the overall performance of a transceiver. [5-7, 11, 12, 39]. However, research in the field of PA reliability is restricted to these three main areas: (i) the effect of DC/RF stress on a device and, subsequently, on circuit performance, (ii) the effect of higher temperatures on a device, and (iii) circuit modification approaches to mitigate long-term degradation in RF devices and circuits [6, 12-20]. Clearly, none of the studies published up till now have compared the classic classes of a PA in terms of degradation. In addition, the correlation between the conduction angle and reliability is not apparently studied and only a few studies have been performed to evaluate PA reliability from this point of view.”) To this end, Eslahi presents an improved prediction method that is capable of taking other important amplifier design features, such as conduction angle, into account, allowing for improved amplifiers to be designed ([Page 39] “An analytical model for age is presented in this chapter which predicts very well HCI-induced degradation in power amplifiers. This model gives an expression for age versus conduction angle. Utilizing this model, all the classic classes of PA were compared in terms of reliability. A new trade-off for PA design was introduced by introducing reliability as a figure of merit at the beginning steps of the design phase. It was proved in this chapter that whereas a class-A power amplifier shows reasonable normalized maximum output power, it suffers from the highest degradation. It was further shown that the lower is the conduction angle, the lower is the age, and the higher is the maximum efficiency of a PA.”) Overall, one of ordinary skill in the art would have recognized that combining Eslahi with Qorvo would result in a more accurate amplifier lifetime prediction system that enables the design of more reliable, longer lasting amplifiers.
Claim 5. Tanomura teaches wherein, in calculating of the deterioration degree, the processor calculates, as the deterioration degree of the electric characteristic of the transistor, ([Page 2 Par 12] “The simulation system of the present embodiment is a circuit simulator realized by a computer that operates according to a program, and is used for designing a high-frequency power amplifier” [Page 3 Par 1-3] “The reliability information is information depending on the transistor structure, and is, for example, a relational expression between the voltage applied to the transistor and the lifetime. The reliability information may be a relational expression between the substrate current and the lifetime of the transistor. By using the relational expression between the transistor substrate current and the lifetime, the lifetime of the CMOS due to the HCI can be easily and accurately calculated. This is because the lifetime of the CMOS has a strong correlation with the substrate current. The relational expression between the substrate current and the lifetime is, for example, lifetime = α × (substrate current) β. However, α and β are parameters depending on the transistor structure.” [Page 4 Par 16-17] “On the other hand, in step B8, the lifetime simulation unit 222 refers to the transistor model, transistor model parameters, matching circuit information, operating voltage, and reliability information, calculates the lifetime of the transistor, and supplies the result to the display unit 23. . Next, the display part 23 displays the output power and lifetime of a transistor on a Smith chart figure in step B9, and supplies the result to the determination part 24. FIG”)
Eslahi makes obvious calculating a worst deterioration degree of the electric characteristic of the at least two deterioration degrees of the electric characteristic. ([Page 34 Par 2 – Page 35 Par 1] “To obtain the AC counterpart of Figure 4.5, we considered a constant drain-source voltage of V𝑑𝑠 = 2 V and a small AC fluctuation and performed simulations for a range of bias points for class-A, the single bias point of class-B, two bias points for class-AB (𝑉𝑔 = 0.7 V and 0.67 V, corresponding to 𝜃 = 250° and 290° respectively), and four bias points for class-C (𝑉𝑔 = 0.5 V, 0.4 V, 0.25 V, 0 V, corresponding to 𝜃 = 140°, 123°, 106°, and 90°, respectively). Figure 4.6 shows the results of age calculation and simulation plotted versus gate bias point. As illustrated, the fit is excellent.” [Figure 4.6] Shows a plot of various calculated age values, i.e. deterioration degrees, based on a varied series of voltages. Each position along the x axis of the graph can be considered a different deterioration degree. This clearly involves the calculation of a worst degradation degree (i.e. the determination of highest age value) [Page 37 Par 1] “Besides the excellent fit of the proposed model to the simulation results of RelXpert, this figure shows clearly that a class-A PA exhibits the worst performance as compared to Class-AB, -B and -C PAs in terms of reliability.” [Examiner’s note: The current language of this claim merely specifies that a worst deterioration degree is calculated, not any comparison of the calculated degrees, e.g. the determination of which of the calculated degrees is worse. As such, any system that calculates at least two degrees with different values is calculating one that is worse than the other.])
Claim 6. Tanomura teaches wherein, in calculating of at least one value, the processor ([Page 2 Par 12] “The simulation system of the present embodiment is a circuit simulator realized by a computer that operates according to a program, and is used for designing a high-frequency power amplifier”) (([Page 3 Par 1-3] “The reliability information is information depending on the transistor structure, and is, for example, a relational expression between the voltage applied to the transistor and the lifetime. The reliability information may be a relational expression between the substrate current and the lifetime of the transistor. By using the relational expression between the transistor substrate current and the lifetime, the lifetime of the CMOS due to the HCI can be easily and accurately calculated. This is because the lifetime of the CMOS has a strong correlation with the substrate current. The relational expression between the substrate current and the lifetime is, for example, lifetime = α × (substrate current) β. However, α and β are parameters depending on the transistor structure.” [Page 4 Par 16-17] “On the other hand, in step B8, the lifetime simulation unit 222 refers to the transistor model, transistor model parameters, matching circuit information, operating voltage, and reliability information, calculates the lifetime of the transistor, and supplies the result to the display unit 23. . Next, the display part 23 displays the output power and lifetime of a transistor on a Smith chart figure in step B9, and supplies the result to the determination part 24. FIG”)
Qorvo makes obvious calculates the first value, the second value, and the third value, and, based on the first value, the second value, ([Page 5 Figure] Shows the ports at which I-V (current and voltage) data can be simulated. [Page 5 Par 7] “The next figure and table illustrate the difference between intrinsic and extrinsic gate, drain and source ports” [Page 6 Figure] Shows a graph of the I-V characteristics at the intrinsic and extrinsic drain ports, including the values of both current and voltage when voltage is at a minimum and maximum value. Further, while the example graph is measured from the drain, it is clear based on the preceding paragraphs [Page 5 Par 7 – Page 6 Par 1] and particularly [Page 5 Figure] which shows measuring locations that the system can also perform measurements at the intrinsic and extrinsic source and gate ports [Page 3 Figure] Shows an I-V curve for Vds and Ids, i.e. the voltage and current across the drain and source, i.e. the current and voltage values across both ends of the current source)
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and the third value, ([Page 2 Par 6] “Three of the most basic classes are Class A, Class AB and Class B. As shown in the following figure, these modes correspond to biasing the transistor at the quiescent voltage-current points indicated by markers m2, m3 and m4 for PA classes A, AB and B, respectively” [Page 3 Figure] The figure also shows the quiescent voltage-current points on the various load lines, which are the points where the circuit is under DC conditions)
Eslahi makes obvious calculates, based on first, second, and third voltage or current values, three deterioration degrees of the electric characteristic of the transistor, respectively. ([Figure 4.6] Shows a plot of various calculated age values, i.e. deterioration degrees, based on a varied series of voltages under RF conditions. Each position along the x axis of the graph can be considered a different deterioration degree corresponding to a respective voltage [Figure 4.5] Shows a similar plot, but under DC conditions.)
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Claim 7. Tanomura teaches wherein the transistor is a field effect transistor (FET) ([Page 2 Par 18] “The transistor model is a general transistor model such as BSIM (Berkeley Short-channel IGFET Model, IGFET = Insulated-Gate Field-Effect Transistor) or HiSIM (Hiroshima-university STARC IGFET Model, STARC = Semiconductor Technology Academic Research Center).”)
Qorvo makes obvious the transistor having a gate connected to the input terminal and a drain connected to the matching circuit, and the current source is a drain current source within the transistor ([Page 11 Figure] Shows a schematic for an amplifier circuit that includes: an input terminal for a radio frequency signal that is input to a transistor (See component labeled {P=1} at the left of the figure) and the drain of the transistor is connected to the matching unit (see the matching component labeled {LoadTuner1} connected between the drain of the transistor {S1} and the output terminal {P=2}). Note that this type of circuit layout makes the drain of the transistor a current source)
(3) Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tanomura (JP 2010257043 A) in view of Model-Based GaN PA Design Basics: The What and Why of Intrinsic I-V Waveforms (Hereinafter Qorvo) in further view of Long-Term Degradation Effects in Power Amplifiers: Analysis, Modelling and Remedies (Hereinafter Eslahi) in addition to A Wideband Multiharmonic Empirical Large-Signal Model for High-Power GaN HEMTs With Self-Heating and Charge-Trapping Effects (Hereinafter Yuk)
Claim 8. Tanomura teaches ([Page 2 Par 12] “The simulation system of the present embodiment is a circuit simulator realized by a computer that operates according to a program, and is used for designing a high-frequency power amplifier”) (([Page 3 Par 1-3] “The reliability information is information depending on the transistor structure, and is, for example, a relational expression between the voltage applied to the transistor and the lifetime. The reliability information may be a relational expression between the substrate current and the lifetime of the transistor. By using the relational expression between the transistor substrate current and the lifetime, the lifetime of the CMOS due to the HCI can be easily and accurately calculated. This is because the lifetime of the CMOS has a strong correlation with the substrate current. The relational expression between the substrate current and the lifetime is, for example, lifetime = α × (substrate current) β. However, α and β are parameters depending on the transistor structure.” [Page 4 Par 16-17] “On the other hand, in step B8, the lifetime simulation unit 222 refers to the transistor model, transistor model parameters, matching circuit information, operating voltage, and reliability information, calculates the lifetime of the transistor, and supplies the result to the display unit 23. . Next, the display part 23 displays the output power and lifetime of a transistor on a Smith chart figure in step B9, and supplies the result to the determination part 24. FIG” [Page 2 Par 18] “The transistor model is a general transistor model such as BSIM (Berkeley Short-channel IGFET Model, IGFET = Insulated-Gate Field-Effect Transistor) or HiSIM (Hiroshima-university STARC IGFET Model, STARC = Semiconductor Technology Academic Research Center).”)
Qorvo makes obvious wherein, in calculating of at least one value, calculates a fourth value that is at least one of a current value and a voltage value, ([Page 6 Figure] Shows a graph of the I-V characteristics at the intrinsic and extrinsic drain ports, including the values of both current and voltage when voltage is at a minimum and maximum value. It is clear from the figure that many voltage and current values are calculated.)
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based on the fourth value, ([Page 6 Figure] Shows a graph of the I-V characteristics at the intrinsic and extrinsic drain ports, including the values of both current and voltage when voltage is at a minimum and maximum value. It is clear from the figure that many voltage and current values are calculated.)
Eslahi makes obvious ([Figure 4.6] Shows a plot of various calculated age values, i.e. deterioration degrees, based on a varied series of voltages. Each position along the x axis of the graph can be considered a different deterioration degree corresponding to a respective voltage; as can be seen, many deterioration degrees are calculated using many voltage values.
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The combination of Tanomura, Qorvo, and Eslahi does not explicitly teach calculates at least one of a current value and a voltage value, the current value being a current value at an end of at least one diode of a diode between the gate and a source and a diode between the gate and the drain within the equivalent circuit, the voltage value being a voltage value across both ends of the at least one diode
Yuk makes obvious calculates at least one of a current value and a voltage value, the current value being a current value at an end of at least one diode of a diode between the gate and a source and a diode between the gate and the drain within the equivalent circuit, the voltage value being a voltage value across both ends of the at least one diode ([Fig. 1] Shows the equivalent circuit used to model the GaN HEMT (note that a GaN HEMT is a type of FET). As can be seen, the equivalent circuit includes a diode between the gate and the source labeled {Dgs} with a labeled voltage across it labeled {Vgs} [Fig. 3] Shows simulation data, as can be seen Vgs is included in the simulation calculations)
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Yuk is analogous art because it is within the field of RF amplifier simulation. It would have been obvious to one of ordinary skill in the art to combine it with Tanomura, Qorvo, and Eslahi before the effective filing date. One of ordinary skill in the art would have been motivated to make this combination in order to more accurately simulate certain amplifier types with unique characteristics that would otherwise be difficult to model, such as GaN HEMTs. Yuk notes the difficulties and limitations of previous modelling attempts for such amplifier types ([Page 3322 Col 2 Par 2] “As a relatively immature, high power density device technology GaN HEMTs can exhibit significant self-heating and trapping effects which introduce anomalies and performance degradations at RF. Among recently reported analytical, large-signal models for GaN HEMTs [6]–[15], a majority focus on characterizing drain–source current (Ids) dispersion from self-heating using dissipated power computations [7]–[10] and charge-trapping effects using transient delay networks [7], [9]. Furthermore, advanced studies on the complex thermal behavior of GaN HEMTs have also been conducted and implemented in large-signal models with good results [11], [12]. However, few report Ids predictions valid beyond 1 A and only a handful report predictions of higher order harmonics [10], [13].”) To this end, Yuk presents a system for the accurate simulation and modelling of GaN HEMTs. ([Page 3322 Col 2 Par 2] “Using techniques presented in [14]–[16], we develop an improved Ids formulation for modeling the unique transconductance (gm) characteristics of high power GaN HEMTs. Extensive use of dynamic IV measurements can be used to characterize the device performance and exploit thermal and trapping effects with great success [17], [18]. Accurate self-heating and charge-trapping models due to dissipated power and the applied quiescent biases are integrated into the model in a complete modeling methodology. The resulting general-purpose nonlinear model accurately predicts pulsed behavior up to 2.3 A at drain–source voltages up to 56 V,-parameters up to 10 GHz and large-signal output (Pout) and input reflected power (Prefl) up to 39 dBm incident power for three harmonics. This work represents a significant expansion of [15] in terms of power, bias, large-signal frequency response and optimal load validity.”) Overall, one of ordinary skill in the art would have recognized that combining Yuk with Tanomura, Qorvo, and Eslahi would produce a simulation system capable of accurately simulating a wider range of RF amplifier types, including types with unique characteristics that typical simulation methods would be unsuitable for.
Conclusion
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/M.P.M./Examiner, Art Unit 2187
/EMERSON C PUENTE/Supervisory Patent Examiner, Art Unit 2187
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