Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
In the communication filed on 04/30/2026, claims 1-20 are pending. Claims 1-4, 6, 8, 10-11, 13-14, and 19 are amended. No claims are new. No claims are presently cancelled.
Allowable Subject Matter
For the reasons detailed in the prior action (section 20 of the Non-Final Rejection, 02/05/2026), the amended dependent Claims 2-5 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
The prior drawing objections for not depicting claim 1’s “combination logic circuit” and claim 5’s “logic circuit” are maintained. The applicant’s remarks (pp. 7, 2nd-3rd para.) identify item “410” in Fig. 4 as being the “combination logic circuit” and the “logic circuit”. However, the specification ¶ [73] simply defines “circuit 410” and never refers to a “combinational logic circuit” or a “logic circuit”. It is suggested to revise the specification and/or claims to use consistent language for the claimed terms. Further, claims 2 and 5 require the “combinational logic circuit” to comprise “a first logic-AND gate”, “a second logic-AND gate”, “a first logic-OR gate”, and “a second logic-OR gate”. Thus, it is impossible for “410” to fully represent the “combinational logic circuit”.
The prior drawing objection regarding the depiction of claim 5’s “second logic-OR gate having a first input configured to receive the second logic signal” is withdrawn. The applicant’s remarks clarify that Fig. 4’s “DET_HIGH” represents the claimed “second logic signal”, which is input to “409”, representing the claimed “second logic-OR gate”.
However, this definition results in a new drawing objection included infra for not depicting claim 2’s “a first logic-AND gate having a first input configured to receive the second logic signal” because the “second logic signal” (identified by applicant as “DET_HIGH”) is not input to the “first logic-AND gate” (identified by applicant as “410-1” on pp. 10, 1st para.). Another new drawing objection is included infra for not depicting claim 2’s “a second logic-AND gate having a first input configured to receive the third logic signal” because the “third logic signal” (identified by applicant as “CNT_LOW”) is not input to the “second logic-AND gate” (identified by applicant as 410-2). To overcome these drawing objections for claim 2’s subject matter, it is suggested to incorporate claim language for the Fig. 4 features of the AND-gate “408”, the AND-gate “405”, and the associated signal interfaces.
The prior objection to Fig. 3B for “lacking a label for the horizonal axis” is withdrawn due to the replacement drawing provided.
The replacement drawings filed 04/30/2026 are attached to indicate Figs. 1, 2A-2B, & 5 as “approved” and Figs. 3-4 as “not approved”. These drawing approval decisions may be superseded in a future action if appropriate changes are made to the drawings, claims, and/or specification to overcome the drawing objections.
The prior objections to the Specification are maintained. To overcome, it is suggested to revise the specification to clearly define each of the objected-to claim terms as being alternative terms for the disclosed features. For example, one may include specification language such as “a comparison voltage VBAT_LEVEL (i.e., the first comparison logic signal)”, and so forth. This would ensure that one could easily understand the claims in light of the specification.
The prior objections to the Claims are withdrawn due to the amendments.
The prior rejections under 35 U.S.C. 112(b) are withdrawn due to the amendments.
Applicant’s arguments with respect to the prior art rejection of independent claim 8 and its dependent claims 9-20 have fully been considered but are not persuasive.
The applicant makes no arguments regarding claim 8 with respect to the prior action’s rejection (section 13 of the Non-Final Rejection, 02/05/2026) under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Morishita (JP 2007-288860 A; hereinafter “Mori”). The applicant’s arguments regarding claim 8, detailed infra, are all with respect to the prior action’s rejection under 35 U.S.C. 102(a)(2) as being anticipated by Heo et al. (US 2023/0276367 A1).
Firstly, the applicant argues (pp. 12, 3rd para.) that “claim 8 requires that the counter be configured to "start counting each time the comparator indicates that the first voltage is smaller than the second voltage." Heo does not describe the counter 226-1 for logic 226 operating in this manner”. The examiner respectfully disagrees.
The examiner interprets from Heo’s Figs. 10-11 and ¶ [79-83] that Heo’s counter (226-1) is configured to start counting each time the comparator (225) indicates that the first voltage (Vin) is smaller than the second voltage (REF). When “Vin” transitions to be less than “REF”, the comparator output “CMP_OUT” changes state. In response to the change in state of “CMP_OUT”, the counter (226-1) starts counting the number of clock cycles until the “debounce time” is reached.
Secondly, the applicant argues (pp. 12, 4th para. – pp. 13, 1st para.) that “Examiner's interpretation therefore improperly conflates alarm generation in the PMIC with interrupt generation in the SoC” and thus Heo does not teach "a logic circuit configured to generate an interruption signal"”. The examiner respectfully disagrees.
The examiner interprets that Heo’s logic circuit (226-2, 226-3, and 227) generates the interruption signal “SVD alarm signal”. The examiner interprets that the “SVD alarm signal” is a type of interruption signal because it interrupts the operation of the “SoC 230” circuitry to indicate a change of state (voltage droop exceeding the “debounce time”) and necessitating a time-sensitive response of adjusting a CPU clock frequency (¶ [89]). The examiner’s opinion is further supported by the applicant’s remark that this signal is “an alarm that is later treated as an interrupt by separate circuitry”. Because the separate circuitry treats the alarm as an interrupt, the examiner’s interpretation of the “SVD alarm signal” as being an interruption signal is reasonable.
Thirdly, the applicant argues (pp. 13, 2nd para.) that Heo does not teach “wherein said interruption signal is generated when a value of the counter during said counting exceeds a limiting value” because the “Examiner's position again depends on interpreting Heo's debounce mechanism as equivalent to the claimed counter-limit relationship, rather than on a disclosure of the claimed behavior”. The examiner respectfully disagrees.
The examiner interprets from Heo’s Figs. 10-11 and ¶ [79-83] that Heo’s counter (226-1) is configured to start counting each time the comparator (225) indicates that the first voltage (Vin) is smaller than the second voltage (REF) until the limiting value “debounce time”. When “Vin” transitions to be less than “REF”, the comparator output “CMP_OUT” changes state. In response to the change in state of “CMP_OUT”, the counter (226-1) starts counting the number of clock cycles until the limiting value “debounce time” (input to the “target_counter” interface of “counter 226-1”) is reached. In order for the interruption signal “SVD alarm signal” to be generated, the time duration of the “CMP_OUT” signal state (input to the “count_in” interface of “counter 226-1) needs to reach the “debounce time” (indicated by the output from the “match” interface of “counter 226-1”).
Fourthly, the applicant argues (pp. 14, 1st-2nd para.) that Heo does not teach “and wherein said interruption signal is generated when the comparator indicates that the first voltage is greater than the second voltage” because Heo “instead teaches maintaining or restoring normal operation when Vin exceeds REF”. The examiner respectfully disagrees.
The examiner agrees with the applicant that Heo discloses “restoring normal operation when Vin exceeds REF”. However, the examiner interprets that Heo discloses the interruption signal “SVD” is still generated in this scenario. Any signal that is output from a device is considered to be generated by that device. This is true regardless of whether the generated signal is in a steady logic Low state, steady logic High state, open-drain/collector, or time-varying. In the scenario when Vin exceeds REF for at least the “debounce time”, the interruption signal “SVD” is pulled to “GND” by “transistor MT”, thus generating “SVD” in a low-voltage output state, causing the “SoC 230” to increase its clock frequency.
Thus, the applicant’s arguments with respect to claims 8-20 are not persuasive.
Applicant’s arguments with respect to the prior art rejection of independent claim 1 and its dependent claims 2-7 have fully been considered but are not persuasive.
Firstly, the applicant argues (pp. 15, 1st-2nd para.) that Mori does not teach “a comparator configured to compare the first voltage with a second voltage and generate a first logic signal having a logic state dependent on the comparison” because “Mori 's output is a processed version of the comparison result rather than the comparator's direct output, and the Examiner's mapping reads the claim's "first logic signal" onto downstream conditioning logic rather than onto the comparator's own output”. The examiner respectfully disagrees.
The examiner interprets that Mori’s comparator (mapped as combo of “120” and “125”) directly produces the first logic signal (“output (d)”), as depicted in Mori’s Fig. 1. Though the applicant argues the prior action’s mapping of Mori’s comparator (combo of “120” and “125”), the examiner interprets that these features perform the claimed functions of the claimed comparator and are thus reasonably interpreted as a comparator. The fact that Mori’s comparator (“120” & “125”) includes an additional delay functionality does not preclude it from being interpreted as a comparator.
Secondly, the applicant argues (pp. 15, 3rd para. – pp. 16, 2nd para.) that Mori does not teach “an edge detector configured to receive the first logic signal and assert a second logic signal in response to detection of an edge of the first signal indicating that the first voltage has exceeded the second voltage” because “the Examiner's mapped element (control logic circuit 155 and its delayed output (i)) is described as delayed control timing, not as an edge detector that asserts a signal in response to edge detection in the manner recited in claim 1”. The examiner respectfully disagrees.
The examiner interprets that Mori’s “control logic circuit 155” performs all claimed functions of the edge detector and is thus interpreted as the claimed edge detector. A change in state of a logic signal always includes an edge as the signal slopes up or down. Thus, the detection of a change in state of a logic signal includes the detection of an edge. The prior action (pp. 17, 3rd para. – pp. 18, 1st para.) includes detailed explanation of the edge detection function based on Mori’s Fig. 2 and ¶ [44].
Thirdly, the applicant argues (pp. 16, 3rd-4th para.) that Mori does not teach “and a combinational logic circuit configured to logically combine the second logic signal and the third logic signal to generate a fourth logic signal” because “Mori's cited path explicitly uses latching and holding (memory), the cited circuitry cannot be considered to be "combinational" in the ordinary sense”. The examiner respectfully disagrees.
The examiner interprets the claim feature “combinational logic circuit” and associated limitations do not specifically exclude sequential logic features. Mori’s “combinational logic circuit (mapped to combo of “D flip-flop 145” and “interface circuit 165”) includes combinational features as the fundamental building blocks of a D flip flop. Further, the instant application’s “reset circuit 409” of Fig. 4 is the “second logic-OR gate” within the “combinational logic circuit” per claim 5. The examiner interprets the “reset circuit 409” and its effects on the rest of the “combinational logic circuit” to conventionally be a type of sequential logic, rather than combinational logic, further supporting the examiner’s interpretation.
Finally, the applicant argues (pp. 17, 1st-2nd para.) that the combo of Mori & Heo does not teach “wherein logic state transitions of the fourth logic signal control modification of an operating mode of an electronic device comprising said battery between a high performance operating mode and a low performance operating mode” because “the Examiner’s rationale depends on treating these different signals as interchangeable control signals without a clear explanation of how Mori's instantaneous interruption interrupt (m) would be used to drive the particular high/low performance mode behavior described in Heo” and because there is “a basis to argue that the proposed combination would be inoperable, and would not yield the claimed relationship in which "logic state transitions of the fourth logic signal" themselves control the operating mode transitions between high and low performance”. The examiner respectfully disagrees.
The examiner asserts that even though there are different meanings associated with Mori’s “fourth logic signal” (“interrupt signal (m)”) and Heo’s analogous output logic signal (“sudden voltage drop (SVD) alarm signal”), each is indicative of a first voltage delivered by a battery dropping below a predetermined second voltage for more or less than a predetermined time period. Similar conclusions regarding the behavior of the battery’s voltage can be made from observing and understanding the meaning of each reference’s interrupt/alarm signal. Thus, the interrupt/alarm signals taught by each of Mori and Heo are analogous. The examiner’s conclusion of obviousness is valid even without each reference’s interrupt/alarm signals being interchangeable.
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Heo simply teaches additional functionality that can be incorporated into Mori’s circuit to reduce power consumption during low battery conditions (Heo ¶ [3, 51-52, 89]). Incorporating these functionalities based on the teachings of Heo does not require undoing any functionality of Mori’s circuit.
Thus, the applicant’s arguments with respect to claims 1-7 are not persuasive.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
“combinational logic circuit” (claim 1)
“logic circuit” (claim 8)
“a first logic-AND gate having a first input configured to receive the second logic signal” (claim 2) – This connection does not appear to be drawn. The “first logic-AND gate” is interpreted to be “410-1” (per applicant’s remarks on pp. 10, 1st para.). The “second logic signal” is interpreted to be the “DET_HIGH” (per applicant’s remarks on pp. 7, 4th para. and pp. 9, 2nd para.). Fig. 4 does not show the “second logic signal” (i.e., “DET_HIGH”) being input to the “first logic-AND gate” (i.e., “410-1”). The unclaimed AND-gate “408” is drawn between these features.
“a second logic-AND gate having a first input configured to receive the third logic signal” (claim 2) – This connection does not appear to be drawn. The “second logic-AND gate” is interpreted to be “410-2” (per applicant’s remarks on pp. 10, 5th para.). The “third logic signal” is interpreted to be “CNT_LOW” (per applicant’s remarks on pp. 9, 3rd para.). Fig. 4 does not show the “third logic signal” (i.e., “CNT_LOW”) being input to the “second logic-AND gate” (i.e., “410-2”). The unclaimed AND-gate “405” is drawn between these features.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) and/or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). The specification lacks antecedent basis for the following claim terms:
“first logic signal” (claim 1) – interpreted as equivalent to “comparison voltage VBAT_LEVEL”
“second logic signal” (claim 1) – interpreted as equivalent to “edge detection voltage LEVEL_HIGH” (Fig. 3) and “DET_HIGH” (Fig. 4)
“third logic signal” (claim 1) – interpreted as equivalent to “output voltage LEVEL_LOW” (Fig. 3) and “LOW_IRQ” (Fig. 4)
“combinational logic circuit” (claim 1)
“fourth logic signal” (claim 1) – interpreted as equivalent to “interruption signal IT” (Fig. 3) and “interruption signal IRQ” (Fig. 4)
“first logic-AND gate” (claim 2) – interpreted as equivalent to “"AND"-type logic gate 410-1” (Fig. 4)
“fifth logic signal” (claim 2) – interpreted as equivalent to “HIGH_IRQ_2” (Fig. 4)
“sixth logic signal” (claim 2) – interpreted as equivalent to “LOW_IRQ_2” (Fig. 4)
“first enable signal” (claim 2) – interpreted as equivalent to “LOW_IRQ_EN” (Fig. 4)
“second logic-AND gate” (claim 2) – interp. as equiv. to “"AND"-type logic gate 410-2”
“second enable signal” (claim 2) – interpreted as equivalent to “HIGH_IRQ_EN”
“first logic-OR gate” (claim 2) – interp. as equiv. to “interruption generation circuit 411”
“second logic-OR gate” (claim 5) – inter. as equiv. to “reset circuit 409” (Fig. 4)
“counter reset signal” (claim 5) – interp. as equiv. to “CNT_RST” (Fig. 4)
“logic circuit” (claim 8)
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-15 and 17-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Heo et al. (US 2023/0276367 A1).
Regarding Claim 8, Heo discloses a circuit (“power management integrated circuit (PMIC) 220”; see annotated Figs. 9-10, included infra) for monitoring a first voltage (“power supply voltage Vin”; Figs. 9-10) delivered by a battery (“battery 210”; Fig. 9), wherein the circuit (220) comprises the following features.
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Heo further discloses a comparator (“comparator 225”; Fig. 10; ¶ [79]: “225 compares the power supply voltage Vin provided to the battery power pad (VBAT) with the reference voltage REF”) configured to compare the first voltage (“Vin”) with a second voltage (“reference voltage REF”; Fig. 10).
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Heo further discloses a counter (“counter 226-1” within “debounce logic 226”; Figs. 10-11; ¶ [82-83]) configured to start counting (¶ [83]: “226-1 counts the comparison signal using a counter responsive to the target counter bit data. In this manner, different debounce times may be applied to the counter(s).”) each time the comparator (“225” with output “CMP_OUT” to “226”; Figs. 10-11) indicates that the first voltage (“Vin”) is smaller than the second voltage (“REF”).
Heo further discloses a logic circuit (combination of “AND logic gate 226-2”, “flip-flop 226-3”, and “open drain pad 227”; Figs. 10-11) configured to generate an interruption signal (“sudden voltage drop (SVD) alarm signal”; Figs. 9-11; ¶ [81]: “227 outputs the SVD alarm signal to a signal pad (LOWBAT), for example, in response to the debounced comparison signal provided by the debounce logic 226”).
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NOTE: The word “generate” can be interpreted broadly. Any signal that comes from a device is considered to be generated by that device. This is true regardless of whether the generated signal is in a steady logic Low state, steady logic High state, open-drain/collector, or time-varying.
Heo further discloses said interruption signal (“SVD alarm signal”, output of “227” per ¶ [81]; Fig. 10) is generated when a value of the counter (226-1) during said counting exceeds a limiting value (when voltage droop time exceeds the “debounce time”, “SVD” is pulled to “GND” by “transistor MT”, thus generating a low-voltage output signal).
Heo further discloses said interruption signal (“SVD alarm signal”, output of “227” per ¶ [81]; Fig. 10) is generated when the comparator (225) indicates that the first voltage is greater than the second voltage (when “Vin” exceeds “REF” for shorter than “debounce time”, “SVD” is maintained at “GND” level, thus generating a low-voltage output signal; when “Vin” exceeds “REF” for longer than “debounce time”, “SVD” is changed to an open drain state, thus generating an open drain output signal).
Regarding Claim 9, Heo discloses the circuit according to claim 8.
Heo further discloses the interruption signal (“sudden voltage drop (SVD) alarm signal”; Figs. 9-11; ¶ [81]: “227 outputs the SVD alarm signal to a signal pad (LOWBAT)”) is configured to modify an operating mode (¶ [89]: “adjusting the frequency of an operating clock provided to a CPU in response to an SVD alarm signal”; Fig. 12, step S330: “adjust CLK”) of an electronic device (“mobile device 200”; Fig. 9) comprising said battery (“battery 210”; Fig. 9).
Regarding Claim 10, Heo discloses the circuit according to claim 9.
Heo further discloses that when the interruption signal (“SVD alarm signal”) is generated because said value of the counter (226-1) exceeds the limiting value (“debounce time”), then said electronic device (200) switches to a low-consumption mode (¶ [5]: “operating clock has a … second frequency lower than the first frequency in response to the positive alarm signal”; ¶ [86]: “in response to the SVD alarm signal, the clock divider 232 adjusts the frequency of the operating clock CLK provided to the CPU 234”).
Regarding Claim 11, Heo discloses the circuit according to claim 10.
NOTE: The rejection hereinafter relies on a broad interpretation of “generating”. Because Heo teaches the interruption signal (“SVD alarm signal”) is output as either a grounded state (pulled to “GND” by “transistor MT”) or an open drain state (“MT” in off-state), one could interpret either of these states as being generated. In this case, the interruption signal (“SVD”) is considered to be generated (i.e., placed in the open drain state) when “Vin” > “REF” and considered to be disabled (i.e., placed in the ground state) when “Vin” < “REF”.
Heo further discloses that when the electronic device (200) is in a low-consumption mode (¶ [5]: “operating clock has a … second frequency lower than the first frequency in response to the positive alarm signal”; ¶ [86]: “in response to the SVD alarm signal, the clock divider 232 adjusts the frequency of the operating clock CLK provided to the CPU 234”), then generating (“generating” is interpreted as the open drain state, as discussed in the note included supra) the interruption signal (“SVD alarm signal”) as a result of the value of said counter (226-1) is greater than said limiting value (“debounce time”) is disabled (if already operating with the “second frequency”, then “SVD” maintains the grounded state until the “Vin” rises to “REF” again).
Regarding Claim 12, Heo discloses the circuit according to claim 11.
Heo further discloses modifying the operating mode comprises decreasing a clock frequency for a processor (“CPU 234”; Fig. 9) during the low-consumption mode (¶ [5]: “operating clock has a … second frequency lower than the first frequency in response to the positive alarm signal”; ¶ [86]: “in response to the SVD alarm signal, the clock divider 232 adjusts the frequency of the operating clock CLK provided to the CPU 234”).
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Regarding Claim 13, Heo discloses the circuit according to claim 9.
Heo further discloses that when the interruption signal (“SVD alarm signal”) is generated because said first voltage (“Vin”) is greater than the second voltage (“REF”; when “Vin” exceeds “REF” for longer than “debounce time”, “SVD” is changed to an open drain state) then said electronic device (200) switches to a full power mode (¶ [5]: “operating clock has a first frequency in response to the negative alarm signal”; ¶ [86]: “the operating clock frequency may be maintained at a given (e.g., default) frequency when the power supply voltage Vin is higher than the reference voltage REF”).
Regarding Claim 14, Heo discloses the circuit according to claim 13.
NOTE: The rejection hereinafter relies on a broad interpretation of “generation”. Because Heo teaches the interruption signal (“SVD alarm signal”) is output as either a grounded state (pulled to “GND” by “transistor MT”) or an open drain state (“MT” in off-state), one could interpret either of these states as being generated. In this case, the interruption signal (“SVD”) is considered to be generated (i.e., placed in the ground state) when “Vin” < “REF”. and considered to be disabled (i.e., placed in the open drain state) when “Vin” > “REF”.
Heo further discloses that when the electronic device (200) is in a full power mode (¶ [5]: “operating clock has a first frequency in response to the negative alarm signal”; ¶ [86]: “the operating clock frequency may be maintained at a given (e.g., default) frequency when the power supply voltage Vin is higher than the reference voltage REF”), then generation (“generation” is interpreted as the grounded state, as discussed in the note included supra) of the interruption signal (“SVD alarm signal”) because said first voltage (“Vin”) is greater than said second voltage (“REF”) is disabled (if already operating with the “first frequency”, then “SVD” maintains the open drain state until the “Vin” droops below “REF” again).
Regarding Claim 15, Heo discloses the circuit according to claim 8.
Heo further discloses the counter (226-1) is configured to be reset (“226-1” starts counting each time the “CMP_out” signal changes state; “CMP_out” is the output of the comparator “225”, which compares “Vin” vs. “REF”) each time the first voltage (“Vin”) is greater than the second voltage (“REF”)
Regarding Claim 17, Heo discloses the circuit according to claim 8.
Heo further discloses the second voltage (“reference voltage REF”; Fig. 10) is configurable (programmable via I2C through “PMIC interface 221” of Figs. 9-10; ¶ [77]: “221 receives power management information (e.g., information defining one or more reference voltage levels) via a serial data communication protocol from an external device”).
Regarding Claim 18, Heo discloses the circuit according to claim 8.
Heo further discloses the limiting value (“debounce time”; Fig. 10-11) is configurable (programmable via I2C through “PMIC interface 221” of Figs. 9-10; ¶ [77]: “221 receives power management information … via a serial data communication protocol from an external device”; ¶ [78]: “power management information is assumed to include … a third part (e.g., 6 bits) provided to debounce logic 226”; ¶ [80]: “debounce times selected by the third part of the power management information”).
Regarding Claim 19, Heo discloses an electronic device (“mobile device 200”; Fig. 9), comprising a battery (210) and said circuit (220) according to claim 8.
Claims 8 and 19 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Morishita (JP 2007-288860 A; hereinafter “Mori”).
Regarding Claim 8, Mori discloses a circuit (“system power supply IC 100”; see annotated Fig. 1, included infra) for monitoring a first voltage (¶ [35]: “power supply voltage (a) of the battery 200”; ¶ [39]: “detection voltage (a)”; Figs. 1-2) delivered by a battery (“battery 200”; Fig. 1), wherein the circuit (100) comprises the following features.
Mori further discloses a comparator (combo of “power supply voltage detection circuit 120” and “delay circuit 125”; Fig. 1; ¶ [25]: “120 includes … a comparator that compares the detection voltage with a predetermined reference value”) configured to compare the first voltage (“(a)”) with a second voltage (“reference value (Th1)”; Fig. 2).
Mori further discloses a counter (combination of “counter circuit 150”, “inverter 130”, and “D flip-flops 135, 140”; Fig. 1) configured to start counting (signal “(e)” shows the start of the counting/timing of the voltage dropout on the transition of “(d)” to logic Low; Figs. 1-2) each time the comparator (120, 125) indicates (via signal “(d)”) that the first voltage (“(a)”) is smaller than the second voltage (“Th1”).
Mori further discloses a logic circuit (combination of “D flip-flop 145”, and “interface circuit 165”; Fig. 1) configured to generate an interruption signal (“interrupt signal (m)”; Fig. 1; ¶ [34]: “165 generates an interrupt signal (m) … to inform the CPU 400 that the power supply voltage drop is an instantaneous interruption”; ¶ [66]).
NOTE: The word “generate” can be interpreted broadly. Any signal that comes from a device is considered to be generated by that device. This is true regardless of whether the generated signal is in a steady logic Low state, steady logic High state, open-drain/collector, or time-varying.
Mori further discloses said interruption signal (“(m)”) is generated (per the interpretation of “generate” discussed in the note supra, the signal “(m)” is generated for the entirety of the sequence shown in Fig. 2; see annotated Fig. 2, included infra) when a value (dropout time, evaluated by comparing signal “(e)” with “(d)”) of the counter (130, 135, 140, 150) during said counting exceeds a limiting value (“instantaneous interruption determination reference period (T0)”; Fig. 2; ¶ [34]: “165 generates an interrupt signal (m) … to inform the CPU 400 that the power supply voltage drop is an instantaneous interruption”; ¶ [66]).
Mori further discloses said interruption signal (“(m)”) is generated (per the interpretation of “generate” discussed in the note supra, the signal “(m)” is generated for the entirety of the sequence shown in Fig. 2; see annotated Fig. 2, included infra) when the comparator (120, 125) indicates that the first voltage (“(a)”) is greater than the second voltage (“Th1”).
Regarding Claim 19, Mori discloses an electronic device (“electronic device 50”; Fig. 1), comprising a battery (200) and said circuit (100) according to claim 8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Morishita (JP 2007-288860 A; hereinafter “Mori”) in view of Heo et al. (US 2023/0276367 A1).
Regarding Claim 1, Mori discloses a circuit (“system power supply IC 100”; see annotated Fig. 1, included infra) for monitoring a first voltage (¶ [35]: “power supply voltage (a) of the battery 200”; ¶ [39]: “detection voltage (a)”; Figs. 1-2) delivered by a battery (“battery 200”; Fig. 1), the circuit (100) comprising the following features.
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Mori further discloses a comparator (combo of “power supply voltage detection circuit 120” and “delay circuit 125”; Fig. 1; ¶ [25]: “120 includes … a comparator that compares the detection voltage with a predetermined reference value”) configured to compare the first voltage (“(a)”) with a second voltage (“reference value (Th1)”; Fig. 2) and generate a first logic signal (“output (d) of the delay circuit 125”; Figs. 1-2; ¶ [39-43]) having a logic state dependent on the comparison (Fig. 2 shows “(d)” is dependent on comparison of “(a)” versus “Th1”, with delay “T3”; see annotated Fig. 2, included infra).
Mori further discloses an edge detector (“control logic circuit 155” in Fig. 1) configured to receive the first logic signal (“(d)” is input to “155”) and assert a second logic signal (“output (i)”; Figs. 1-2) in response to detection of an edge (annotated Fig. 2 shows rising edge of “(a)” results in “(i)” changing logic states to High; ¶ [44]: “When the output (d) of the delay circuit 125 changes from Low to High at timing (3), the output (i) of the control logic circuit 155 changes from Low to High”) of the first logic signal (“(d)”) indicating that the first voltage (“(a)”) has exceeded the second voltage (“Th1”).
Mori further discloses a counter (combination of “counter circuit 150”, “inverter 130”, and “D flip-flops 135, 140”; Fig. 1) configured to start counting (signal “(e)” shows the start of the counting/timing of the voltage dropout on the transition of “(d)” to logic Low; Figs. 1-2) each time the logic state of the first logic signal (“(d)”) indicates that the first voltage (“(a)”) is less than the second voltage (“Th1”).
Mori further discloses the counter (130, 135, 140, 150) is configured to generate a third logic signal (“output (h) of the D flip flop 140”; Figs. 1-2) having a logic state dependent (Fig. 2 shows output “(h)” becomes logic High in response to the dropout time < T0, but stays logic Low in response to dropout time > T0; ¶ [74]: “output of the D flip-flop 140 can be used as the instantaneous interruption determination result”) on whether a value of the counter exceeds a count limit (“instantaneous interruption determination reference period (T0)”; Fig. 2).
Mori further discloses a combinational logic circuit (combination of “D flip-flop 145”, and “interface circuit 165”; Fig. 1) configured to logically combine the second logic signal (“(i)” is input to “CK” terminal of “145”) and the third logic signal (“(h)” is input to “D” terminal of “145”) to generate a fourth logic signal (“interrupt signal (m)”; Fig. 1; ¶ [34]: “165 generates an interrupt signal (m) … to inform the CPU 400 that the power supply voltage drop is an instantaneous interruption”; ¶ [66]).
Mori further discloses logic state transitions of the fourth logic signal (“interrupt signal (m)”, indicative of whether the dropout time of “(a)” exceeds “T0” or not; logic transitions depicted in Fig. 2).
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Mori further discloses an electronic device (“electronic device 50”; Fig. 1) comprising said battery (200).
Mori does not disclose “logic state transitions of the fourth logic signal control modification of an operating mode of an electronic device comprising said battery between a high performance operating mode and a low performance operating mode”.
Heo teaches logic state transitions of the logic signal (“sudden voltage drop (SVD) alarm signal”; Figs. 9-11; ¶ [81]: “227 outputs the SVD alarm signal to a signal pad (LOWBAT), for example, in response to the debounced comparison signal provided by the debounce logic 226”) control modification of an operating mode (¶ [89]: “adjusting the frequency of an operating clock provided to a CPU in response to an SVD alarm signal”; Fig. 12, step S330: “adjust CLK”) of an electronic device (“mobile device 200”; Fig. 9) comprising said battery (“battery 210”; Fig. 9) between a high performance operating mode (¶ [5]: “operating clock has a first frequency in response to the negative alarm signal”; ¶ [86]: “the operating clock frequency may be maintained at a given (e.g., default) frequency when the power supply voltage Vin is higher than the reference voltage REF”) and a low performance operating mode (¶ [5]: “operating clock has a … second frequency lower than the first frequency in response to the positive alarm signal”; ¶ [86]: “in response to the SVD alarm signal, the clock divider 232 adjusts the frequency of the operating clock CLK provided to the CPU 234”).
NOTE: The logic state of the logic signal (“SVD alarm signal”) taught by Heo is indicative of whether a detected battery voltage (“Vin”; Figs. 9-10, 12) has drooped below a reference voltage (“REF”; Fig. 10) for a duration that exceeds a limit (“debounce time”; ¶ [80]; Figs. 10-11). Thus, the logic signal taught by Heo is analogous to the fourth logic signal taught by Mori.
Heo further teaches switching between high/low performance operating modes (by controlling clock frequency) to effectively manage the mobile device’s power (¶ [89]) and extend battery life by reducing power consumption during low-battery conditions (¶ [3, 51-52]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the electronic device disclosed by Mori to switch between high/low performance operating modes in response to logic state transitions of the fourth logic signal, as taught by Heo, to extend the battery life of the electronic device by reducing power consumption during low-battery conditions.
Regarding Claim 6, the combination of Mori and Heo discloses an electronic device (Mori’s “50” with modifications from Heo’s “mobile device 200”, as detailed supra), comprising: a battery (Mori: “200”; Heo equivalent: “210”) and the circuit according to claim 1 (Mori’s “100” with modifications from Heo).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Morishita (JP 2007-288860 A; hereinafter “Mori”) in view of Heo et al. (US 2023/0276367 A1) and Saarisalo et al. (US 2009/0023476 A1; hereinafter “Saar”).
Regarding Claim 7, the combo of Mori & Heo teaches the electronic device of claim 6 (Mori’s “50” with modifications from Heo’s “mobile device 200”, as detailed supra).
Mori does not disclose the electronic device further comprises “a near-field communication circuit”.
Saar teaches the electronic device (“mobile terminal 10”; Fig. 1) further comprises a near-field communication circuit (combination of “antenna 12”, “transmitter 14”, “receiver 16”, and “controller 20”; Fig. 1; ¶ [4]: “communicate with other devices using short-range wireless technology, such as Near Field Communication (NFC)”).
Saar further teaches the near-field communication circuit to enable the electronic device to perform near-field communications, which improves convenience for the user to complete consumer transactions and communicate with other nearby devices (¶ [4]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the electronic device disclosed by the combination of Mori and Heo to incorporate a near-field communication circuit, as taught by Saar, to improve convenience for the user to complete consumer transactions and communicate with other nearby devices.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Heo et al. (US 2023/0276367 A1) in view of Hong (KR 2003-0083071 A).
Regarding Claim 16, Heo discloses the circuit according to claim 8.
Heo discloses the counter (226-1) and said limiting value (“debounce time”).
Heo does not disclose “the counter is configured to be reset each time said value of the counter is greater than said limiting value.”
Hong teaches the counter (“counter 210”; Fig. 3) is configured to be reset each time said value of the counter is greater than said limiting value (annotated Fig. 5, included infra, shows the counter value is reset after it reaches the limiting value “N”).
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Hong further teaches resetting the counter each time the count is greater than the limiting value as a hardware implementation of a counter circuit that reduces power consumption compared to other possible implementations (¶ [17]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the counter disclosed by Heo to be reset each time the count is greater than the limiting value, as taught by Hong, as a simple hardware implementation of a counter circuit that has reduced power consumption compared to other possible implementations. It is further noted the reset functionality incorporated into Heo would not prevent the Heo circuit from operating.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Heo et al. (US 2023/0276367 A1) in view of Saarisalo et al. (US 2009/0023476 A1; hereinafter “Saar”).
Regarding Claim 20, Heo discloses the electronic device (200) according to claim 19.
Heo does not disclose the electronic device comprises “a near-field communication circuit”.
Saar teaches the electronic device (“mobile terminal 10”; Fig. 1) further comprises a near-field communication circuit (combination of “antenna 12”, “transmitter 14”, “receiver 16”, and “controller 20”; Fig. 1; ¶ [4]: “communicate with other devices using short-range wireless technology, such as Near Field Communication (NFC)”).
Saar further teaches the near-field communication circuit to enable the electronic device to perform near-field communications, which improves convenience for the user to complete consumer transactions and communicate with other nearby devices (¶ [4]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the electronic device disclosed by Heo to incorporate a near-field communication circuit, as taught by Saar, to improve convenience for the user to complete consumer transactions and communicate with other nearby devices.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Morishita (JP 2007-288860 A; hereinafter “Mori”) in view of Saarisalo et al. (US 2009/0023476 A1; hereinafter “Saar”).
Regarding Claim 20, Mori discloses the electronic device (50) according to claim 19.
Mori does not disclose the electronic device comprises “a near-field communication circuit”.
Saar teaches the electronic device (“mobile terminal 10”; Fig. 1) further comprises a near-field communication circuit (combination of “antenna 12”, “transmitter 14”, “receiver 16”, and “controller 20”; Fig. 1; ¶ [4]: “communicate with other devices using short-range wireless technology, such as Near Field Communication (NFC)”).
Saar further teaches the near-field communication circuit to enable the electronic device to perform near-field communications, which improves convenience for the user to complete consumer transactions and communicate with other nearby devices (¶ [4]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the electronic device disclosed by Mori to incorporate a near-field communication circuit, as taught by Saar, to improve convenience for the user to complete consumer transactions and communicate with other nearby devices.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DANIEL P MCFARLAND/ Examiner, Art Unit 2859
/DREW A DUNN/ Supervisory Patent Examiner, Art Unit 2859
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