DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is a response to the election of species filed on 2/20/2026.
Election/Restrictions
Applicant’s election of Species B, sub-species BA, claims 1-3, 5-8 and 10-14, in the reply filed on 2/20/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 4 and 9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/20/2026.
Claim Objections
Claims 1-3 and 5-8 are objected to because of the following informalities:
Re. claim 1: The phrase “100% to 200% of width w2” as recited in line 6 appears to be --100% to 200% of the width w2--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 5, 7, 8 and 10-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re. claim 3: The phrase “the micro semiconductor chip” as recited in line 1 lacks antecedent basis.
Re. claim 5: The phrase “the micro semiconductor chip” as recited in line 2 lacks antecedent basis.
Re. claim 7: The phrase “the micro semiconductor chip” as recited in line 3 lacks antecedent basis.
Re. claim 10: The phrase “the groove” as recited in line 4 lacks antecedent basis.
Re. claim 12: The phrase “the micro semiconductor chip” as recited in lines 6-7 lacks antecedent basis.
Re. claim 13: The phrase “the requirement of Equation 2” as recited in line 2 lacks antecedent basis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 6, 7 and 10-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hwang et al. (PGPub 2022/0013400 A1) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Hwang et al. teach a transferring structure comprising: a transfer substrate (4120, Fig. 37, paragraphs [0151]-[0154]) having a plurality of grooves (4111, Fig. 37); and a plurality of micro semiconductor chips (4130, Fig. 37) transferred to the plurality of grooves, respectively, each of the plurality of micro semiconductor chips having a width, wherein a minimum space between adjacent two of the plurality of micro semiconductor chips transferred to the plurality of grooves is 100% to 200% of the width as shown in Fig. 37.
Re. claim 2: A width of each of the plurality of grooves is greater than 100% and less than 150% of the width of each of the plurality of micro semiconductor chips as shown in Fig. 37.
Re. claim 6: Each of the plurality of grooves has a size such that each of the plurality of micro semiconductor chips is accommodated therein as shown in Fig. 37.
Re. claim 7: A bottom surface of each of the plurality of grooves has a planar shape with a short side and a long side that is perpendicular to the short side as shown in Figs. 29 and 37-38, the short side is greater than the width of the micro semiconductor chip and less than or equal to two times the width of the micro semiconductor chip as shown in Figs. 29 and 37-38, and the long side is greater than two times the width of the micro semiconductor chip as shown in Fig. 38 (see also paragraph [0156]).
Re. claim 10: A distance between adjacent two of the plurality of grooves is 80% to 170% inclusive of a width of a bottom surface of the groove as shown in Fig. 37.
Re. claim 11: The distance between adjacent two of the plurality of grooves is 100% to 130% inclusive of the width of the bottom surface of the groove as shown in Fig. 37.
Re. claim 12: A spacing of the plurality of micro semiconductor chips satisfy Equation 1: 100(%)≤a/b×100(%)≤200(%), where a denotes a minimum space between adjacent two of the plurality of micro semiconductor chips, and b denotes a size of the plurality of micro semiconductor chip3 as shown in Fig. 37.
Re. claim 13: The spacing of the plurality of micro semiconductor chips satisfy the requirement of Equation 2: 120(%)≤a/b×100(%)≤160(%).
Claims 1-3, 6 and 10-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hwang et al. (PGPub 2024/0178195 A1) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Hwang et al. teach a transferring structure comprising: a transfer substrate (110, Fig. 8, paragraphs [0085]-[0086]) having a plurality of grooves (HO, Fig. 8); and a plurality of micro semiconductor chips (140, Fig. 8) transferred to the plurality of grooves, respectively, each of the plurality of micro semiconductor chips having a width, wherein a minimum space between adjacent two of the plurality of micro semiconductor chips transferred to the plurality of grooves is 100% to 200% of the width as shown in Fig. 8.
Re. claim 2: A width of each of the plurality of grooves is greater than 100% and less than 150% of the width of each of the plurality of micro semiconductor chips as shown in Fig. 8.
Re. claim 3: The micro semiconductor chip has a plurality of electrodes, and positions of the plurality of electrodes form point symmetry with reference to a central part of the micro semiconductor chip as shown in Fig. 9 (paragraph [0087]).
Re. claim 6: Each of the plurality of grooves has a size such that each of the plurality of micro semiconductor chips is accommodated therein as shown in Fig. 8.
Re. claim 10: A distance between adjacent two of the plurality of grooves is 80% to 170% inclusive of a width of a bottom surface of the groove as shown in Figs. 8-9.
Re. claim 11: The distance between adjacent two of the plurality of grooves is 100% to 130% inclusive of the width of the bottom surface of the groove as shown in Figs. 8-9.
Re. claim 12: A spacing of the plurality of micro semiconductor chips satisfy Equation 1: 100(%)≤a/b×100(%)≤200(%), where a denotes a minimum space between adjacent two of the plurality of micro semiconductor chips, and b denotes a size of the plurality of micro semiconductor chip3 as shown in Figs. 8-9.
Re. claim 13: The spacing of the plurality of micro semiconductor chips satisfy the requirement of Equation 2: 120(%)≤a/b×100(%)≤160(%) ad shown in Figs. 8-9.
Re. claim 14: The plurality of micro semiconductor chips have a diamond pentile pixel arrangement as shown in Fig. 8, 11 and 12.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6 and 10-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (PGPub 2023/0043559 A1).
Kim et al. teach a transferring structure comprising: a transfer substrate (310, Fig. 10, paragraph [122]) having a plurality of grooves (350, Fig. 10, paragraph [0127]); and a plurality of micro semiconductor chips (150, Fig. 10, paragraphs [0049]) transferred to the plurality of grooves, respectively, each of the plurality of micro semiconductor chips having a width, wherein a minimum space between adjacent two of the plurality of micro semiconductor chips transferred to the plurality of grooves is 100% to 200% of the width as shown in Fig. 10.
Re. claim 2: A width of each of the plurality of grooves is greater than 100% and less than 150% of the width of each of the plurality of micro semiconductor chips as shown in Fig. 10.
Re. claim 5: A depth of each of the plurality of grooves is less than a thickness of the micro semiconductor chip as shown in Fig. 10.
Re. claim 6: Each of the plurality of grooves has a size such that each of the plurality of micro semiconductor chips is accommodated therein as shown in Fig. 10.
Re. claim 10: A distance between adjacent two of the plurality of grooves is 80% to 170% inclusive of a width of a bottom surface of the groove as shown in Fig. 10.
Re. claim 11: The distance between adjacent two of the plurality of grooves is 100% to 130% inclusive of the width of the bottom surface of the groove as shown in Fig. 10.
Re. claim 12: A spacing of the plurality of micro semiconductor chips satisfy Equation 1: 100(%)≤a/b×100(%)≤200(%), where a denotes a minimum space between adjacent two of the plurality of micro semiconductor chips, and b denotes a size of the plurality of micro semiconductor chip3 as shown in Fig. 10.
Re. claim 13: The spacing of the plurality of micro semiconductor chips satisfy the requirement of Equation 2: 120(%)≤a/b×100(%)≤160(%) as shown in Fig. 10.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The Prior Art
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure. Kim et al. (PGPub 2024/0006199 A1), and Hong et al. (PGPub 2022/0246801 A1) are cited to further show the state of the art with respect to a transferring structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL D KIM whose telephone number is (571)272-4565. The examiner can normally be reached Monday-Friday: 6:00 AM-2:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hong can be reached at 571-272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL D KIM/Primary Examiner, Art Unit 3729
Prosecution Insights