DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is a response to the amendment filed on 5/29/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 6 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (PGPub 2023/0043559 A1) in view of Yamada et al. (US PAT. 6,548,907).
Kim et al. teach a transferring structure comprising: a transfer substrate (310, Fig. 10, paragraph [122]) having a plurality of grooves (350, Fig. 10, paragraph [0127]); and a plurality of micro semiconductor chips (150, Fig. 10, paragraphs [0049]) transferred to the plurality of grooves, respectively, each of the plurality of micro semiconductor chips having a width, wherein a minimum space between adjacent two of the plurality of micro semiconductor chips transferred to the plurality of grooves is 100% to 200% of the width as shown in Fig. 10.
However, Kim et al. silent a plurality of electrodes of the plurality of micro semiconductor chips, positioned form point symmetry with reference to a central part of the plurality of micro semiconductor chips. Yamada et al. teach a plurality of micro semiconductor chips having a plurality of electrodes positioned form point symmetry with reference to a central part of the plurality of micro semiconductor chips as shown in Fig. 4 (col. 6, lines 12-47) in order to reduce a time a cost while testing the plurality of micro semiconductor chips during a manufacturing the plurality of micro semiconductor chips. Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify a transferring structure of Kim et al. by a plurality of electrodes of the plurality of micro semiconductor chips, positioned form point symmetry with reference to a central part of the plurality of micro semiconductor chips as taught by Yamada et al. in order to reduce a time a cost while testing the plurality of micro semiconductor chips during a manufacturing the plurality of micro semiconductor chips.
Re. claim 2: Kim et al. also teach that a width of each of the plurality of grooves is greater than 100% and less than 150% of the width of each of the plurality of micro semiconductor chips as shown in Fig. 10.
Re. claim 5: Kim et al. also teach that a depth of each of the plurality of grooves is less than a thickness of the micro semiconductor chip as shown in Fig. 10.
Re. claim 6: Kim et al. also teach that each of the plurality of grooves has a size such that each of the plurality of micro semiconductor chips is accommodated therein as shown in Fig. 10.
Re. claim 10: Kim et al. also teach that a distance between adjacent two of the plurality of grooves is 80% to 170% inclusive of a width of a bottom surface of the groove as shown in Fig. 10.
Re. claim 11: Kim et al. also teach that the distance between adjacent two of the plurality of grooves is 100% to 130% inclusive of the width of the bottom surface of the groove as shown in Fig. 10.
Re. claim 12: Kim et al. also teach that a spacing of the plurality of micro semiconductor chips satisfy Equation 1: 100(%)≤a/b×100(%)≤200(%), where a denotes a minimum space between adjacent two of the plurality of micro semiconductor chips, and b denotes a size of the plurality of micro semiconductor chip3 as shown in Fig. 10.
Even though Kim et al. silent a diamond pentile pixel arrangement for the plurality of micro semiconductor chips, since such a modification would have been an obvious design consideration that is within the purview of one having ordinary skill in the art to provide the well-known benefit of obtaining desirable system as required. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable rangers involves only routine skill in the art. MPEP 2144.04 (il-A). The applicant has not disclosed any criticality for the claimed limitations.
Re. claim 13: Kim et al. also teach that tshe spacing of the plurality of micro semiconductor chips satisfy the requirement of Equation 2: 120(%)≤a/b×100(%)≤160(%) as shown in Fig. 10.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 8 is allowed.
Response to Arguments
Applicant’s arguments with respect to claims 1, 2 and 5-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL D KIM whose telephone number is (571)272-4565. The examiner can normally be reached Monday-Friday: 6:00 AM-2:00 PM.
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/PAUL D KIM/Primary Examiner, Art Unit 3729
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