DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the Applicant’s amendments filed on 12/05/2025. Claims 1-15 remain pending in the application. Claims 1-9 and 14-15 have been amended. Any examiner’s note, objection, and rejection not repeated is withdrawn due to Applicant’s amendment.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/10/2023 and 03/13/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Examiner’s Note
The Examiner cites particular columns, paragraphs, figures, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may also apply. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20190220318 A1) hereafter Yang, in view of Ramesh et al. (US 20130332942 A1) hereafter Ramesh, further in view of Kurabayashi (US 20140237108 A1).
Regarding claim 1, Yang teaches:
An electronic device, comprising:
a memory storing instructions (Paragraph 183; “The software product is stored in a storage and includes several instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to perform all or a part of the steps of the methods described in the embodiments of the present disclosure. The foregoing storage includes any medium that can store program code, such as a USB flash drive, a ROM, a RAM, a removable hard disk, a magnetic disk, or an optical disc.”); and at least one processor including a processing circuitry, (Paragraph 155; “The processor 608 is configured to read the computer program in the memory 602, and then execute a method defined in the computer program”, where a processor inherently includes circuitry configured to execute and perform logical operations, therefore it reads on the claimed processing circuitry) wherein the memory stores instructions configured to, when executed by the at least one processor, cause the electronic device to:
based on identifying that a first available capacity of the memory for allocating a process to the memory is less than a capacity threshold, perform a first memory retrieval operation that retrieves data of at least one process allocated to the memory to increase an available capacity of the memory (Paragraph 105; a low level of memory pressure corresponds to identifying that an available capacity of memory for allocating a process to memory is less than a capacity threshold. “When the current memory pressure level of the system is determined to be the low level, a policy of performing process-level compressing or process-level cache reclamation needs to be used for the process for which memory is to be reclaimed based on an application importance degree” whose operations necessarily involve retrieving and reclaiming data associated with a process. Further, “one application may have one or more processes” corresponding to at least one process allocated to the memory. The system performs memory retrieval operations based on the policy utilized when the memory pressure is at a particular level with the goal of increasing available memory capacity, corresponding to performance of first memory retrieval operations for increasing the first available capacity of the memory. “memory pressure level of the system is determined to be the low level, a policy of performing process-level compressing or process-level cache reclamation needs to be used for the process for which memory is to be reclaimed” corresponds to retrieving data of at least one process allocated to the memory to increase available memory capacity. Paragraph 6 further defines memory pressure as “a difference between the memory threshold and the current available memory of the system”. “process-level reclamation” from memory corresponds to retrieving data of at least one process allocated to the memory, based on Paragraph 51 of the instant specification, “an operation for decreasing a used capacity of the memory and increasing an available capacity in the state in which the available capacity of the memory is lacking may be referred to and described as a memory retrieval operation”);
identify an available capacity of the memory, based on an event generated by the first memory retrieval operation (Paragraphs 12-13; “the operation of determining that current available memory of a system is less than a memory threshold” describes determining current available memory of the system. “triggered when a first key event is detected” corresponds to being based on an event. “the first key even includes any one of a program start beginning event, a cleanup event, and an out of memory (OOM) event. When the first key event happens, memory reclamation needs to be performed immediately” links the generation of events to memory reclamation operations);
perform a second memory retrieval operation that terminates at least one selected process among processes allocated to the memory based on a value of the identified available capacity being less than or equal to a first threshold value and the identified available capacity being greater than a second threshold value (Paragraphs 102-104; the second memory retrieval operation corresponds to the actions taken by the system when the memory pressure is medium. “Memory pressure levels are preset as a high level, a medium level, and a low level. The high level indicates that the memory pressure is relatively large, the medium level indicates that the memory pressure is moderate, and the low level indicates that the memory pressure is relatively small. In addition, a memory pressure value range is preset as a first range, a second range, and a third range, where the first range is less than the second range, and the second range is less than the third range”. The policy takes effect when the identified available memory capacity is less than a threshold value for execution which causes the memory retrieval operations to take effect. The identified available capacity is within a range corresponding to a medium memory pressure, corresponding to being greater than a second threshold value. “memory pressure level of the system is determined to be the medium level, a policy of clearing the process for which memory is to be reclaimed”, and “the application-level memory reclamation policy, for example, kill”, where killing a process functionally corresponds to process termination. Paragraph 178 contemplates performance of steps in parallel, “according to the present disclosure, some steps may be performed in other sequences or performed simultaneously.”);
and perform a third memory retrieval operation that terminates the at least one selected process among processes allocated to the memory based on a value of the identified available capacity being less than or equal to the first threshold value and the identified available capacity being less than or equal to the second threshold value (Paragraphs 102-104; the third memory retrieval operation corresponds to the actions taken by the system when the memory pressure is high. “When the current memory pressure level of the system is determined to be the high level, a policy of clearing the process for which memory is to be reclaimed needs to be used”. The policy takes effect when the identified available memory capacity is less than a threshold value for execution which causes the memory retrieval operations to take effect. The identified available capacity is within a range corresponding to a high memory pressure, corresponding to having identified available capacity less than or equal to a second threshold value. “a resource occupied by an existing process in the terminal needs to be destroyed and reclaimed”, where destroying a resource occupied by a process forcibly ends the process, thus freeing its memory, which corresponds to terminating a selected process.);
wherein the first threshold value is greater than the second threshold value (Paragraphs 102-104; the first threshold corresponds to the transition between medium and high remaining memory, corresponding to medium and low memory pressure, while the second threshold corresponds to the transition between low and medium remaining memory, corresponding to high and medium memory pressure);
wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to, based on the third memory retrieval operation being performed (Paragraph 103; “When the current memory pressure level of the system is determined to be the high level, a policy of clearing the process for which memory is to be reclaimed needs to be used, the high level policy corresponding to the third memory retrieval operation, and the actions thereof corresponding to being based on the operation being performed):
end a first process selected from among the at least one process allocated to the memory (Paragraph 103; “When the current memory pressure level of the system is determined to be the high level, a policy of clearing the process for which memory is to be reclaimed needs to be used. According to this policy, a resource occupied by an existing process in the terminal needs to be destroyed and reclaimed in order to increase the available memory of the system”, where the operations taken when the policy for high memory pressure is active correspond to the third memory retrieval operation. The act of destroying an existing process for memory reclamation corresponds to ending a first process from among the at least one allocated process);
and end a second process selected from among the at least one process allocated to the memory (Paragraph 110; “There may be one or more processes determined for which memory is to be claimed. When one process requires sending a plurality of processing instructions, the processing instructions may be sent successively one by one for the process, without a need to check, after sending one processing instruction, a state of memory corresponding to the process for which memory is reclaimed by the system kernel before sending another processing instruction”, where the recitation of one or more processes corresponds to ending a second process selected from among the at least one process);
Yang does not teach performing actions while executing the first memory retrieval operation; while executing the first memory retrieval operation, based on identifying an event indicating that the available capacity of the memory is insufficient by the first memory retrieval operation; stand by for a first delay time; or being based on the first delay time having elapsed.
However, Ramesh teaches:
performing actions while executing the first memory retrieval operation (Paragraph 33; “if a memory pressure event notification is being handled by the lowest priority process, but the free and available memory in the memory system drops precipitously, the lowest priority process can be terminated without further notification.”, the memory pressure event notification corresponding to a part of the first memory retrieval operation, the termination corresponding to performance of an action alongside the first operation, thereby corresponding to performing further actions while executing the first memory retrieval operation.);
performing actions while executing the first memory retrieval operation, based on identifying an event indicating that the available capacity of the memory is insufficient by the first memory retrieval operation (Paragraph 33; “if a memory pressure event notification is being handled by the lowest priority process, but the free and available memory in the memory system drops precipitously, the lowest priority process can be terminated without further notification.”, the memory pressure event notification corresponding to a part of the first memory retrieval operation, the free and available memory dropping corresponding to identifying that the available capacity of the memory is insufficient by the first memory retrieval operation.).
Yang and Ramesh are considered to be analogous to the claimed invention because they are in the same field of memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yang to incorporate the teachings of Ramesh and have performed the first and second memory retrieval operations during execution of the first memory retrieval operation, and identified an event indicating that the available memory is insufficient during execution of the first memory retrieval operation. A person of ordinary skill in the art would have recognized that Yang explicitly discloses “some steps may be performed in other sequences or performed simultaneously” (Paragraph 178), and that parallel computation is a known concept in the art, the implementation of which would allow for the second memory retrieval and third memory retrieval operations to execute in parallel alongside the first memory retrieval operations, yielding the predictable result of properly responding to situations where the first memory retrieval operation does not clear enough memory. Further, a person of ordinary skill in the art would have recognized backup logic to be a known method in the art and would recognize that backup logic of Ramesh applied to the memory reclamation techniques of Yang would yield the predictable result of providing the capability to properly respond to situations in which the first memory reclamation operation alone is insufficient to clear enough memory.
Yang in view of Ramesh does not teach stand by for a first delay time; or being based on the first delay time having elapsed.
However, Kurabayashi teaches:
stand by for a first delay time (Paragraph 51; “in some embodiments, the second process wait time interval may be longer than the first process wait time interval”);
based on the first delay time having elapsed (Paragraph 42; “when delaying the processing of the first and/or second processes 222 and 224, may schedule other processes before the first and/or second processes 222 and 224. By executing processes based on the processing capacity information, the computing device 220 may execute processes that communicate with cloud processing systems with higher capabilities for receiving service requests more frequently than cloud processing systems with lower capabilities for receiving service requests”, where the execution in response to the delay time having elapsed corresponds to an action being performed in response to a first delay time having elapsed.).
Yang, Ramesh, and Kurabayashi are considered to be analogous to the claimed invention because they are in the same field of process management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yang in view of Ramesh to incorporate the teachings of Kurabayashi and have stood by for a first delay time, and perform actions based on the first delay time having elapsed. A person of ordinary skill in the art would recognize the use of a time-based scheduling/delay mechanism to be a known method in the art in which the implementation on the system of Yang in view of Ramesh would yield the predictable result of ensuring that actions occur after a controlled delay, thus ensuring proper sequencing.
Claim 8 recites similar limitations as those of claim 1. Claim 8 is rejected for similar reasons as those of claim 1.
Claim 15 recites similar limitations as those of claim 1, additionally reciting a non-transitory computer-readable storage medium. Yang teaches:
A non-transitory computer-readable storage medium (Paragraph 184; “A person of ordinary skill in the art may understand that all or some of the steps of the methods in the embodiments may be implemented by a program instructing relevant hardware. The program may be stored in a computer readable storage. The storage may include a flash memory, a ROM, a RAM, a magnetic disk, or an optical disc”, where storage media correspond to non-transitory computer-readable storage mediums).
Claim 15 is rejected for similar reasons as those of claim 1.
Regarding claim 2, Yang in view of Ramesh, further in view of Kurabayashi teaches the electronic device of claim 1. Yang teaches:
a memory retrieval operation (Paragraphs 102-105; the operations taken when memory pressure is low, medium, or high, correspond to memory retrieval operations.);
and wherein the third memory retrieval operation secures the available capacity of the memory faster than the second memory retrieval operation (Paragraphs 103-104; “When the current memory pressure of the system is determined to be high… a resource occupied by an existing process in the terminal needs to be destroyed and reclaimed”, and “when the current memory pressure level of the system is determined to be the medium level… the application-level memory reclamation policy [may perform steps of] kill, compress, or drop cache”. At high pressure, corresponding to the third memory retrieval operation, the system reclaims memory by immediately destroying processes to free memory, which is inherently faster because termination and reclamation occur directly without intermediate processing. At medium pressure, corresponding to the second memory retrieval operation, the system relies on cache reclamation or compression which require additional processing overhead and is therefore slower).
Kurabayashi teaches:
a first delay time shorter than a second delay time (Paragraph 51; “in some embodiments, the second process wait time interval may be longer than the first process wait time interval”).
Claim 9 recites similar limitations as those of claim 2. Claim 9 is rejected for similar reasons as those of claim 2.
Regarding claim 3, Yang in view of Ramesh, further in view of Kurabayashi teaches the electronic device of claim 1. Yang teaches:
stop performing the third memory retrieval operation when an available capacity of the memory identified during the performing of the third memory retrieval operation is greater than the second threshold value (Paragraphs 102-103; “when the memory pressure value is in the third range, the current memory pressure level [is] the high level” which results in a policy where “a resource occupied by an existing process needs to be destroyed and reclaimed to increase the available memory”. The third memory retrieval operation corresponds to the actions taken when memory pressure level is high. The prior art implies that performance of the operation is stopped because once the destruction/reclamation “increases the available memory” enough to move out of the third range, and therefore out of the high memory pressure threshold, corresponding to having available capacity greater than a second threshold value, the third operation is implied to stop because the high level policy no longer applies);
and stop performing the second memory retrieval operation when an available capacity of the memory identified during the performing of the second memory retrieval operation is greater than the first threshold value (Paragraphs 102 and 104; “when the memory pressure is in the second range, the current memory pressure [is] the medium level” which results in a policy where the system “may reclaim system cache… [or] kill, compress, or drop cache” in order to increase idle memory. The second memory retrieval operation corresponds to the actions taken when memory pressure is medium. The prior art implies that performance of the operation is stopped because once the actions increase idle memory enough to exceed the second range, thereby making the memory capacity greater than the first threshold value, the second operation is implied to stop because the medium pressure policy no longer applies).
Claim 10 recites similar limitations as those of claim 3. Claim 10 is rejected for similar reasons as those of claim 3.
Regarding claim 7, Yang in view of Ramesh, further in view of Kurabayashi teaches the electronic device of claim 1. Yang teaches:
based on the second memory retrieval operation being performed, select one or more processes to be ended from among the at least one process allocated to the memory, based on a specified process end condition and specified importance (Paragraph 104; “policy for clearing the process for which memory is to be reclaimed on a system or an application level” when the memory pressure is at a medium level corresponds to the second memory retrieval operation and the actions taken thereof correspond to the actions taken based on the second memory retrieval operation being performed. The operation selects processes for termination “based on an importance degree” and “application-level memory reclamation policy, for example, kill, compress, or drop cache” supports selection from at least one process);
and end at least one of the one or more processes to be ended (Paragraph 104; “kill” corresponds to ending at least one selected process).
Claims 4 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Ramesh, further in view of Kurabayashi, further in view of Shahane et al. (US 11714682 B1) hereafter Shahane.
Regarding claim 4, Yang in view of Ramesh, further in view of Kurabayashi teaches the electronic device of claim 1. Yang teaches:
identify that the identified available capacity of the memory is less than the capacity threshold, and perform the first memory retrieval operation based on identifying that an available capacity of the memory identified by a request for allocating a process is less than or equal to a third threshold value (Paragraphs 101-102; “the memory pressure value is a difference between the memory threshold and the current available memory of the system” and “memory pressure values are preset at a high level, a medium level, and a low level” where memory pressure is identified based on the memory pressure value range, corresponding to an identified available capacity being less than the capacity threshold. The actions taken when the memory pressure is low corresponds to the first memory retrieval operation based on identifying that memory capacity for a request is less than or equal to a third threshold, corresponding to the range for low level memory pressure).
Yang in view of Ramesh, further in view of Kurabayashi does not teach performing the third memory retrieval operation before a second operation.
However, Shahane teaches:
perform the third memory retrieval operation before a second operation (Col. 16, line 57 – Col. 17, line 5; “the resource allocation manager 162 may determine that specific memory pages can be reallocated based on performance considerations” such as whether it would be more efficient to reclaim the memory page now and restore it later corresponds determining the order between the operations).
Yang, Ramesh, Kurabayashi and Shahane are considered to be analogous to the claimed invention because they are in the same field of memory management. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Yang in view of Ramesh, further in view of Kurabayashi and Shahane to have reversed the order of the memory reclamation steps of Yang to immediately reclaim the memory page based on performance considerations. Shahane explicitly teaches reordering memory reclamation operations based on efficiency and performance considerations. Combining the disclosure of Yang’s third operation with Shahane’s dynamic reordering of reclamation steps suggests execution of the third memory retrieval operation before the second operation when efficiency dictates.
Claims 11 and 12 in combination recite similar limitations as those of claim 4. Claim 4 is dependent on claim 1. Claims 11 and 12 are dependent on claim 8. Claims 1 and 8 recite similar limitations. Therefore, claims 11 and 12 are rejected for similar reasons as those of claim 4.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Ramesh, further in view of Kurabayashi, further in view of Shahane, further in view of Mathur et al. (US 8056081 B2) hereafter Mathur.
Regarding claim 5, Yang in view of Ramesh, further in view of Kurabayashi, further in view of Shahane teach the electronic device of claim 4. Yang teaches:
perform the first operation based on the identified available capacity, identified by the request for allocating the requested process, being less than or equal to the third threshold value (Paragraph 105; “process-level compressing may be performed… using a swap partition in order to reduce occupation of physical memory” corresponds to performing the first operation when available memory capacity is less than or equal to the threshold because Yang discloses performance of process-level compression under low memory pressure, whose threshold corresponds to being less than or equal to the third threshold value);
perform the second operation based on an available capacity of the memory identified during the performing of the first operation being less than or equal to a fourth threshold value (Paragraph 105; “process-level cache reclamation… [performs] release memory space occupied by a cache in the terminal” corresponds to performing the second operation when available memory capacity is less than or equal to a threshold value. Cache reclamation is a distinct action on cache memory invoked under low memory pressure, corresponding to the second operation);
stop the performing of the first operation based on the available capacity identified during the performing of the first operation being greater than a fifth threshold value (Paragraph 102; “when the memory pressure value is in the first range, the current memory pressure of the system may be determined to be the low level” corresponds to stopping performance of the memory reclamation operations. Paragraphs 103-105 further disclose the policies taken when the memory pressure falls within a given range of values, corresponding to being within a threshold. If memory capacity increases, the memory pressure drops below the policy range which implies that the policy would no longer apply and thus would cease);
and stop the performing of the second operation based on an available capacity identified during the performing of the second operation being greater than the fourth threshold value, wherein the third threshold value is greater than the second threshold value, and wherein the fourth threshold value is less than the second threshold value (Paragraph 102; “when the memory pressure value is in the first range, the current memory pressure of the system may be determined to be the low level” corresponds to stopping performance of the memory reclamation operations. Paragraphs 103-105 further disclose the policies taken when the memory pressure falls within a given range of values, corresponding to being within a threshold. If memory capacity increases, the memory pressure drops below the policy range which implies that the policy would no longer apply and thus would cease.).
Yang in view of Ramesh, further in view of Kurabayashi, further in view of Shahane does not teach multiple threshold values corresponding to the fourth and fifth thresholds.
However, Mathur teaches:
Fourth and fifth memory usage thresholds (Col. 4, lines 25-29; “Generally, operating system 44 monitors memory usage and sets a plurality of memory usage thresholds at which different actions are taken to reduce or minimize current and future memory usage.”, where the plurality of memory usage thresholds correspond to the fourth and fifth memory usage thresholds from which different actions are taken).
Yang, Ramesh, Kurabayashi, Shahane, and Mathur are considered to be analogous to the claimed invention because they are in the same field of memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yang in view of Ramesh, further in view of Kurabayashi, further in view of Shahane to incorporate the teachings of Mathur and have extended the thresholds of Yang to include fourth and fifth memory usage thresholds at which different actions are taken for memory reclamation operations. A person of ordinary skill in the art would have been motivated by system stability and predictability. The use of multiple thresholds allows finer granularity of memory management, thus allowing lighter reclamation actions such as cache trimming at low risk levels, and more aggressive actions such as process termination at high risk levels.
Claim 13 recites similar limitations as those of claim 5. Claim 13 is rejected for similar reasons as those of claim 5.
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Ramesh, further in view of Kurabayashi, further in view of Wang et al. (US 20140032559 A1) hereafter Wang.
Regarding claim 6, Yang in view of Ramesh, further in view of Kurabayashi teach the electronic device of claim 1. Yang teaches:
based on the third memory retrieval operation being performed, select one or more processes to be ended from among the at least one process allocated to the memory, based on an importance value (Paragraphs 102-103; where the policy that causes actions when the memory pressure is high corresponds to the third memory retrieval operation, the actions of the third memory retrieval operation corresponding to being based on the third memory retrieval operation being performed. “a policy of clearing the process for which memory needs to be reclaimed directly needs to be used”, where a resource occupied by an existing process in the terminal is destroyed and reclaimed. Paragraph 100 further discloses “a process that is in the important process list and whose importance is not high enough may be degraded and included in the killable list”, implying that the processes to be ended is based on its importance value as processes with a sufficiently high importance will not be included in the killable list);
and end at least one of the one or more processes to be ended without identifying a specified process end condition (Paragraph 103; “a resource occupied by an existing process… needs to be destroyed and reclaimed” corresponds to ending at least one selected processes because the disclosure explicitly teaches process termination to free memory. The phrase “needs to be destroyed and reclaimed” disclosure of destroying a resource reflects a mandatory action triggered by the memory state, not by any independent process-specific exit condition, which corresponds to ending processes without identifying a specified process end condition.).
Yang in view of Ramesh, further in view of Kurabayashi does not teach that the operations are based on at least one of a process size or a memory occupancy.
However, Wang teaches:
at least one of a process size or a memory occupancy (Paragraph 251; “It should be noted that the description information 1131 refers to running process B1 and it also includes the size of memory occupied by B1. In FIG. 11B, the running processes are ranked by their memory occupancy and listed in such a manner.”, where size of memory related to a running process corresponds to process size, and each process being ranked by their memory occupancy corresponds to the memory occupancy).
Yang, Ramesh, Kurabayashi, and Wang are considered to be analogous to the claimed invention because they are in the same field of memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yang in view of Ramesh further in view of Kurabayashi to incorporate the teachings of Wang and base selecting processes for termination based additionally on a process size or a memory occupancy. A person of ordinary skill in the art would recognize that by prioritizing processes that consume more memory, the system can more efficiently free a larger amount of memory with fewer termination actions, thereby minimizing disruption to the system while maximizing reclaimed resources.
Claim 14 recites similar limitations as those of claim 6. Claim 14 is rejected for similar reasons as those of claim 6.
Response to Arguments
Applicant's arguments filed 12/05/2025 have been fully considered but they are not persuasive. Applicant’s arguments are summarized below:
Claim 1 is patentable because Yang in view of Deng does not disclose or suggest the newly amended limitations.
Yang does not disclose, teach, or suggest performance “while executing the first memory retrieval operation” as recited in amended independent claim 1.
Deng does not disclose or suggest the “first delay time” as recited in amended independent claim 1.
Dependent claims are patentable at least for the reasons stated above.
Examiner’s response:
The Examiner agrees that Yang in view of Deng does not disclose or suggest all features recited in amended claim 1. Therefore, the previous rejection of claim 1 under 35 U.S.C. 102(a)(1) and 102(a)(2) has been withdrawn. However, upon further consideration, a new ground(s) of rejection has been made in view of Yang, Ramesh, and Kurabayashi, under 35 U.S.C. 103.
The Examiner agrees that Yang alone does not fully disclose the amended limitation portion of “while executing the first memory retrieval operation”. Therefore, the previous rejection of claim 1 under 35 U.S.C. 102(a)(1) and 102(a)(2) has been withdrawn. However, upon further consideration, a new ground(s) of rejection has been made in view of Yang, Ramesh, and Kurabayashi, under 35 U.S.C. 103. In particular, Yang discloses “some steps may be performed in other sequences or performed simultaneously” (Paragraph 178), therefore parallel execution is at least contemplated by the disclosure. In combination with Ramesh teaching performing actions in parallel with a first memory retrieval operation, a person of ordinary skill in the art would recognize the combination as teaching or at least suggesting parallel execution of the second and third memory retrieval operations of Yang “while executing the first memory retrieval operation”.
While the Examiner does not agree with Applicant’s arguments that Deng fails to disclose or suggest a “first delay time”, the amendments to independent claim 1 necessitated a new ground(s) of rejection. Thus, the rejection has been updated to rely on Kurabayashi for the specific limitation challenged in the argument. Accordingly, the arguments directed to Deng are moot.
Independent claims 1, 8, and 15 remain rejected for the reasons stated above. Therefore, contrary to Applicant's arguments, because the dependent claims depend from an unpatentable claim and does not add limitations that overcome the rejection, it likewise remains rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Watson et al. (US 7827358 B2) discusses memory reduction operations based on memory usage levels, corresponding to the applicant’s thresholds for memory retrieval.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH P TRAN whose telephone number is (571)272-6926. The examiner can normally be reached M-TH 4:30 a.m. - 12:30 p.m. PT, F 4:30 a.m. - 8:30 a.m. PT, or at Kenneth.Tran@uspto.gov.
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/KENNETH P TRAN/ Examiner, Art Unit 2196
/APRIL Y BLAIR/ Supervisory Patent Examiner, Art Unit 2196