Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18/120,910 filed on July 23, 2026.
Claims Corrections
The objections of claims 14, 15, 19 have been withdrawn, per the response dated on 07/23/2026.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
7. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
8. Claims 1-3, 5, 9-13, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes et al. (US 2020/0211970 A1) in view of Tsai et al. (US 2020/0075350 A1).
Regarding independent claim 1, Gomes et al. teaches a multi-die module, comprising (Fig. 2D):
an interposer (201a/201b), wherein the interposer comprises:
a first region (201a); and
a second region (201b), wherein the first region (201a) is laterally (side-by-side) spaced apart from the second region (201b);
a first die (221) over the interposer (201a/201b), wherein the first die (221) is positioned over the first region (201a) and the second region (201b) of the interposer;
a second die (203a) adjacent to a first end (left end) of the first die (221); and
a third die (203b) adjacent to a second end (right end) of the first die (221) opposite from the first end.
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Gomes et al. is silent to explicitly disclose wherein, an overmold laterally between the first die and the second die, and laterally between the first die and the third die, the overmold on the first region and the second region of the interposer.
Tsai et al. teaches wherein (Fig. 1H, upside down), an overmold (190/210) laterally between the first die (174) and the second die (172), and laterally between the first die (174) and the third die (176), the overmold (190/210) on the first region and the second region of the interposer (160).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Tsai et al. and modify the package structure of Gomes et al., incorporating molding/underfill material on the chips, in order to protect the integrated chips, secure and robust electrical connections, and improved reliability.
Regarding claim 2, Gomes et al. and Tsai et al. teach all of the limitations of claim 1 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the first region is laterally spaced apart from the second region by saw street (see figure in claim 1), and wherein, within the interposer (201a/201b), electrical routing in the first region (201a) is electrically isolated from electrical routing in the second region (201b) by the saw street.
Regarding claim 3, Gomes et al. and Tsai et al. teach all of the limitations of claim 2 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the first die (221) provides a bridge between the electrical routing in the first region (201a) and the electrical routing in the second region (201b).
Regarding claim 5, Gomes et al. and Tsai et al. teach all of the limitations of claim 1 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the first region (201a) is a mirror image of the second region (201b).
Regarding claim 9, Gomes et al. and Tsai et al. teach all of the limitations of claim 1 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the first region is laterally (side-by-side) spaced apart from the second region by a saw street (see figure in claim 1), and wherein no interconnect is provided over the saw street between the interposer (201a/201b) and the first die (221).
Regarding claim 10, Gomes et al. and Tsai et al. teach all of the limitations of claim 1 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the interposer (201a/201b) is coupled to a package substrate (223) and a board (802).
Regarding claim 11, Gomes et al. and Tsai et al. teach all of the limitations of claim 1 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the multi-die module is part of a personal computer, a server (see para [0058]), a mobile device, a tablet, or an automobile.
Regarding independent claim 12, Gomes et al. teaches an electronic package, comprising (Fig. 2D):
a package substrate (223);
an interposer (201a/201b- see the figure below) coupled to the package substrate (223), wherein the interposer has a first region (201a) and a second region (201b) that is laterally (side-by-side) separated from the first region by a saw street (see the annotated figure below), wherein the first region (201a) is a mirror image (i.e. duplicate or replica) of the second region (201b);
a die (221) coupled to the interposer (201a/201b), wherein the die (221) spans across a region between the first region (201a) and the second region (201b) of the interposer.
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Gomes et al. is silent to explicitly disclose wherein, an overmold laterally adjacent to sides of the first die, the overmold on the first region and the second region of the interposer.
Tsai et al. teaches wherein (Fig. 1H, upside down), an overmold (190/210) laterally adjacent to sides (left and right) of the first die (174), the overmold (190/210) on the first region and the second region of the interposer (160).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Tsai et al. and modify the package structure of Gomes et al., incorporating molding/underfill material on the chips, in order to protect the integrated chips, secure and robust electrical connections, and improved reliability.
Regarding claim 13, Gomes et al. and Tsai et al. teach all of the limitations of claim 12 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the interposer comprises silicon (see para [0043]).
Regarding independent claim 18, Gomes et al. teaches a computing system, comprising (Figs. 2D, 8):
a board (802, see Fig. 8, para [0052]);
a package substrate (223) coupled to the board (802); and
a multi-die module (203a/221/203b) coupled to the package substrate (223), wherein the multi-die module comprises:
an interposer (201a/201b) with a multi-reticle form factor (1st and 2nd regions), wherein a saw street (see the annotated figure below) is provided between each reticle region (201a, 201b);
a first die (221 bridge die, para [0027]) over the interposer (201a/201b), wherein the first die (221) spans across the saw street;
a second die (203a) adjacent to the first die (221) on the interposer (201a/201b); and
a third die (203b) adjacent to the first die (221) on the interposer (201a/201b).
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Gomes et al. is silent to explicitly disclose wherein, an overmold laterally between the first die and the second die, and laterally between the first die and the third die, the overmold on the first region and the second region of the interposer.
Tsai et al. teaches wherein (Fig. 1H, upside down), an overmold (190/210) laterally between the first die (174) and the second die (172), and laterally between the first die (174) and the third die (176), the overmold (190/210) on the first region and the second region of the interposer (160).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Tsai et al. and modify the package structure of Gomes et al., incorporating molding/underfill material on the chips, in order to protect the integrated chips, secure and robust electrical connections, and improved reliability.
9. Claims 14-15, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes et al. (US 2020/0211970 A1) in view of Tsai et al. (US 2020/0075350 A1) as applied to claims 12, 19 above.
Regarding claim 14, Gomes et al. and Tsai et al. teach all of the limitations of claim 12 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the first region (201a) and the second region (201b) have certain footprints or areas with length or height form factor, as shown in the following figure.
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However, Gomes et al. is explicitly silent of disclosing wherein, the first region and the second region have footprints with 26 mm by 33 mm form factor. It would have been obvious to select intended ‘form factor of the first and second regions’ so that the form factor to be within the quoted range, to optimize/miniature of the device shape/size. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed form factor or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen form factor or upon another variable recited in a claim, the Applicant must show that the chosen form factor is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 15, Gomes et al. and Tsai et al. teach all of the limitations of claim 12 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the first region is laterally (side-by-side) spaced apart from the second region by a saw street (see figure in claim 12), and a width of the saw street has certain width, as shown in the following figure.
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However, Gomes et al. is explicitly silent of disclosing wherein, the width of the saw street is 10 μm or less. It would have been obvious to select intended ‘width of the saw street’ to be within the quoted range, to fabricate more individual devices in the wafer by saving the space. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed width or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen width or upon another variable recited in a claim, the Applicant must show that the chosen width is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 19, Gomes et al. and Tsai et al. teach all of the limitations of claim 18 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), a first or second region/reticle (201a or 201b) has certain form factor or area, as shown in the following figure.
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However, Gomes et al. is explicitly silent of disclosing wherein, the reticle form factor is 26 mm by 33 mm. It would have been obvious to select intended ‘form factor of the first and second regions’ so that the form factor to be within the quoted range, to optimize/miniature of the device shape/size. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed form factor or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen form factor or upon another variable recited in a claim, the Applicant must show that the chosen form factor is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
10. Claims 4, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes et al. (US 2020/0211970 A1) in view of Tsai et al. (US 2020/0075350 A1) as applied to claims 1 and 12 above, and further in view of Nangalia et al. (US 2023/0245985 A1).
Regarding claim 4, Gomes et al. and Tsai et al. teach all of the limitations of claim 1 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the first region is laterally (side-by-side) spaced apart from the second region by a saw street (see figure in claim 12).
Gomes et al. and Tsai et al. are silent to explicitly disclose wherein, the saw street is lined by a seal ring.
Nangalia et al. teaches wherein (Fig. 7A), the saw street (17’) is lined by a seal ring (26B, para [0052]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Nangalia et al. and modify the saw street of Gomes et al. and Tsai et al., incorporate the seal ring around the saw street, in order to safeguard the integrated circuitrys of the wafer from physical, mechanical and environmental stresses/damages of during dicing process.
Regarding claim 16, Gomes et al. and Tsai et al. teach all of the limitations of claim 12 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the first region is laterally (side-by-side) spaced apart from the second region by a saw street (see figure in claim 12).
Gomes et al. is silent to explicitly disclose wherein, the saw street is lined by a seal ring.
Nangalia et al. teaches wherein (Fig. 7A), the saw street (17’) is lined by a seal ring (26B, para [0052]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Nangalia et al. and modify the saw street of Gomes et al. and Tsai et al., incorporate the seal ring around the saw street, in order to safeguard the integrated circuitrys of the wafer from physical, mechanical and environmental stresses/damages of during dicing process.
11. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gomes et al. (US 2020/0211970 A1) in view of Tsai et al. (US 2020/0075350 A1) as applied to claim 1 above, and further in view of Braunisch et al. (US 2010/0327424 A1).
Regarding claim 6, Gomes et al. and Tsai et al. teach all of the limitations of claim 1 from which this claim depends.
Gomes et al. and Tsai et al. are silent to explicitly disclose wherein, the first region has a different layout than the second region.
Braunisch et al. teaches wherein (Fig. 6), the first region (520) has a different layout than the second region (530).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Braunisch et al. as an alternative structure having potential advantage of readily scalable to multiple bridges on a package and many substrates on a panel.
12. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Gomes et al. (US 2020/0211970 A1) in view of Tsai et al. (US 2020/0075350 A1) as applied to claim 1 above, and further in view of Qian et al. (US 2021/0398906 A1).
Regarding claim 8, Gomes et al. and Tsai et al. teach all of the limitations of claim 1 from which this claim depends.
Gomes et al. and Tsai et al. are silent to explicitly disclose wherein, the first die is a compute die, and wherein the second die and the third die are systems on a chip (SoCs).
Qian et al. teaches wherein (Fig. 3A), the first die (340) is a compute die, and wherein the second die (3301) and the third die (3302) are systems on a chip (SoCs) (see para [0038]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Qian et al. and modify compute dies of Gomes et al. and Tsai et al. along with the system-on-chip dies, in order to provide a shorter electrical connection path between the overlying structure, suitable for forming high density routing of channels in order to communicatively couple a first die 3301 to a second die 3302 (para [0037]).
13. Claims 7, 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes et al. (US 2020/0211970 A1) in view of Tsai et al. (US 2020/0075350 A1) as applied to claims 1, 12, 18 above, and further in view of Yu et al. (US 2023/0009553 A1).
Regarding claim 7, Gomes et al. and Tsai et al. teach all of the limitations of claim 1 from which this claim depends.
Gomes et al. teaches wherein (Fig. 2D), the second die (203a) and the third die (203b) are compute dies (computation die, para [0026]).
Gomes et al. and Tsai et al. are silent to explicitly disclose wherein, the first die is a system on a chip (SoC).
Yu et al. teaches wherein (Fig. 2), the bridge die (120) is a system on a chip (SoC) (para [0023] the interconnect die 120 are both system on chip (SoC) die).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yu et al. and modify the bridge die of Gomes et al. and Tsai et al. along with the system-on-chip die, in order to provide a shorter electrical connection path between the overlying structure, subsequently formed on the back surface of the interconnect die 120 and the underlying structure subsequently formed on the front surface of the interconnect die 120 (para [0022]).
Regarding claim 17, Gomes et al. and Tsai et al. teach all of the limitations of claim 12 from which this claim depends.
Gomes et al. and Tsai et al. are silent to explicitly disclose wherein, the die is a system on a chip (SoC) or a compute die.
Yu et al. teaches wherein (Fig. 2), the bridge die (120) is a system on a chip (SoC) (para [0023] the interconnect die 120 are both system on chip (SoC) die).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yu et al. and modify the bridge die of Gomes et al. and Tsai et al. along with the system-on-chip die, in order to provide a shorter electrical connection path between the overlying structure, subsequently formed on the back surface of the interconnect die 120 and the underlying structure subsequently formed on the front surface of the interconnect die 120 (para [0022]).
Regarding claim 20, Gomes et al. and Tsai et al. teach all of the limitations of claim 18 from which this claim depends.
Gomes et al. is silent to explicitly disclose wherein, wherein the first die is a compute die or a system on a chip (SoC).
Yu et al. teaches wherein (Fig. 2), the bridge die (120) is a system on a chip (SoC) (para [0023] the interconnect die 120 are both system on chip (SoC) die).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yu et al. and modify the bridge die of Gomes et al. along with the system-on-chip die, in order to provide a shorter electrical connection path between the overlying structure, subsequently formed on the back surface of the interconnect die 120 and the underlying structure subsequently formed on the front surface of the interconnect die 120 (para [0022]).
Examiner’s Note
14. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
15. It has been acknowledged that the applicant amended claims 1-2, 4, 9, 12, 14-16, 18-19, per the response dated on 07/23/2026.
Applicant’s remarks in pages 8-10 have been considered, but they are moot because of new grounds of rejection in the current office action.
Conclusion
16. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
18. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
