DETAILED ACTION
Claims 1 through 16 originally filed 14 March 2023. By amendment received 19 March 2026; claims 1, 3 through 5, and 7 through 9 are amended, claims 2, 6, and 10 through 16 are cancelled, and claims 17 through 22 are added. Claims 1, 3 through 5, 7 through 9, and 17 through 22 are addressed by this action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments have been fully considered; they are addressed below.
Applicant argues that the amendments to the drawings and disclosure resolve the previous drawing objections. This argument is persuasive and the corresponding objections are withdrawn.
Applicant argues that the claim amendments resolve the previous rejections under 35 U.S.C. 112(b). This argument is persuasive and the corresponding rejections are withdrawn.
Applicant argues that the amendments to the claims overcome the previously cited art. This argument is persuasive. However, upon further search and consideration, new art has been located which renders obvious that which is now claimed. As such, new rejections are set forth below.
As such, all claims are addressed as follows:
Information Disclosure Statement
The information disclosure statement filed 2 December 2025 fails to comply with the provisions of 37 CFR 1.98(a)(4) because it lacks the appropriate size fee assertion. It has been placed in the application file, but the information referred to therein has not been considered as to the merits.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3 through 5, 7, 9, 17 through 19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Iga et al. (I421a, US Pub. 2010/0254421) in view of Egawa et al. (Egawa, US Pub. 2008/0232419).
I421a was initially cited in the IDS received 14 March 2023.
Regarding claim 1, I421a discloses, "A first edge-emitting semiconductor laser chip" (p. [0027], [0046], and Fig. 7, pt. 8). "A predetermined number of electrodes located between the submount and the first edge-emitting semiconductor laser chip and or between the submount and the second edge-emitting semiconductor laser chip" (p. [0047] and Fig. 7, pts. 3 and 8). "[The stacked growth layer] including a first conductive cladding layer" (p. [0030] and Fig. 2, pt. 15). "A light-emitting layer" (p. [0030] and Fig. 2, pt. 16). "A second conductive cladding layer formed on the semiconductor substrate" (p. [0030] and Fig. 2, pt. 17). "The first edge-emitting semiconductor laser chip includes m laser resonators (m > 1) extending in a second direction orthogonal to the first direction are formed" (p. [0046] and Fig. 7, pts. 7 and 8). "The predetermined number of the electrodes is larger than m + n for providing additional mechanical support for the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip on the submount" (p. [0047] and Fig. 7, pts. 3 and 7). I421a does not explicitly disclose, "A second edge-emitting semiconductor laser chip." "A single submount for supporting the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip." "Wherein the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are located on the electrodes." "[The first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are located] adjacently to each other in a first direction." "The first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip each include a semiconductor substrate and a stacked growth layer." "The second edge-emitting semiconductor laser chip includes n laser resonators (n > 1) extending in the second direction." Egawa discloses, "A second edge-emitting semiconductor laser chip" (p. [0232] and Fig. 13A, pt. 65). "A single submount for supporting the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip" (p. [0232] and Fig. 13A, pts. 65 and 80). "Wherein the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are located on the electrodes" (p. [0232] and Fig. 13A, pt. 65, where splitting chip 8 of I421a into two chips as with Egawa results in the two chips reflecting the arrangement of Figure 7 of Egawa except being separated into two chips at the center of chip 8). "[The first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are located] adjacently to each other in a first direction" (p. [0232] and Fig. 13A, pt. 65). "The first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip each include a semiconductor substrate and a stacked growth layer" (p. [0237] and Fig. 13A, pts. 66 and 70). "The second edge-emitting semiconductor laser chip includes n laser resonators (n > 1) extending in the second direction" (p. [0235] and Fig. 13A, pts. 65 and 70). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of I421a with the teachings of Egawa. In view of the teachings of I421a regarding a laser array mounted to a submount, the alternate construction of the laser array by splitting the emitters across several chips as taught by Egawa would enhance the teachings of I421a by allowing stress within the laser chips to be reduced.
Regarding claim 3, I421a does not explicitly disclose, "Wherein the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are mounted on the submount with a junction-down method." Egawa discloses, "Wherein the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are mounted on the submount with a junction-down method" (p. [0232] and Fig. 13A, pts. 70 and 80). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of I421a with the teachings of Egawa for the reasons provided above regarding claim 1.
Regarding claim 4, I421a discloses, "Wherein the m laser resonators (m ≥ 2) are configured to be electrically and independently driven by the separate electrodes" (p. [0048] and Fig. 7, pts. 3 and 7).
Regarding claim 5, I421a does not explicitly disclose, "Wherein the semiconductor substrate of the first edge-emitting semiconductor laser chip has a tilted substrate with a tilted side face located on a side of the second edge-emitting semiconductor laser chip." Egawa discloses, "Wherein the semiconductor substrate of the first edge-emitting semiconductor laser chip has a tilted substrate with a tilted side face located on a side of the second edge-emitting semiconductor laser chip" (p. [0268], [0276], and Figs. 13A, 15C, and 17C, pts. C1, C2, 65, and 69). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of I421a with the teachings of Egawa for the reasons provided above regarding claim 1.
Regarding claim 7, I421a does not explicitly disclose, "Wherein four or more of the (m + n) laser resonators in the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are formed with substantially equal intervals." Egawa discloses, "Wherein four or more of the (m + n) laser resonators in the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are formed with substantially equal intervals" (p. [0232] and Fig. 13A, pt. 65, where splitting chip 8 of I421a into two chips as with Egawa results in the two chips reflecting the arrangement of Figure 7 and described in p. [0035] of Egawa except being separated into two chips at the center of chip 8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of I421a with the teachings of Egawa for the reasons provided above regarding claim 1.
Regarding claim 9, I421a does not explicitly disclose, "Wherein the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are placed with a gap that separates them." Egawa discloses, "Wherein the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are placed with a gap that separates them" (p. [0232] and Fig. 13A, pts. 61 and 65). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of I421a with the teachings of Egawa for the reasons provided above regarding claim 1.
Regarding claim 17, The combination of I421a and Egawa does not explicitly disclose, "Wherein any two adjacent ones of the (m + n) laser resonators are located with an interval between 10 µm and 40 µm." It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the distance between resonators to within the claimed distance so as to allow the footprint of the device to be reduced, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 18, I421a does not explicitly disclose, "The first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip both have a tilted substrate that face with each other." Egawa discloses, "The first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip both have a tilted substrate that face with each other" (p. [0268], [0276], and Figs. 13A, 15C, and 17C, pts. C1, C2, 65, and 69). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of I421a with the teachings of Egawa for the reasons provided above regarding claim 1.
Regarding claim 19, I421a discloses, "At least m + n ones of the electrodes have a shorter length in the first direction than the remaining one of the electrodes" (Fig. 7, pt. 3).
Regarding claim 22, I421a discloses, "At least one of the electrodes has a longer length in the first direction than the remaining one of the electrodes" (Fig. 7, pt. 3).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over I421a, in view of Egawa, and further in view of Paoli et al. (Paoli, US Patent 4,831,629).
Regarding claim 8, I421a does not explicitly disclose, "Wherein at least one of the (m + n) laser resonators formed in the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip." Egawa discloses, "Wherein at least one of the (m + n) laser resonators formed in the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip" (p. [0237] and Fig. 13A, pts. 65 and 70). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of I421a with the teachings of Egawa for the reasons provided above regarding claim 1.
The combination of I421a and Egawa does not explicitly disclose, "[At least one of the laser resonators] has an oscillation wavelength different from that of at least another one of the resonators." Paoli discloses, "[At least one of the laser resonators] has an oscillation wavelength different from that of at least another one of the resonators" (col. 4, lines 19-28 and Fig. 1, pt. 11). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of I421a and Egawa with the teachings of Paoli. In view of the teachings of I421a regarding a laser array mounted to a submount, the alternate construction of the laser resonators to emit different wavelengths as taught by Paoli would enhance the teachings of I421a and Egawa by allowing the array to provide a broader spectrum emission.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Iga et al. (I816b, US Pub. 2009/0147816) in view of Egawa.
Regarding claim 20, I816b discloses, "A first edge-emitting semiconductor laser chip" (p. [0004] and Fig. 12, pt. 8). "A predetermined number of electrodes located between the submount and the first edge-emitting semiconductor laser chip and or between the submount and the second edge-emitting semiconductor laser chip" (p. [0055] and Fig. 12, pts. 8 and 14). "[The stacked growth layer] including a first conductive cladding layer" (p. [0060] and Fig. 7, pt. 15). "A light-emitting layer" (p. [0060] and Fig. 7, pt. 16). "A second conductive cladding layer formed on the semiconductor substrate" (p. [0060] and Fig. 7, pt. 17). "The first edge-emitting semiconductor laser chip includes m laser resonators (m > 1) extending in a second direction orthogonal to the first direction are formed" (p. [0069] and Fig. 12, pts. 8 and 14). "The predetermined number of electrodes is equal to m + n for providing mechanical support for the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip" (p. [0055] and Fig. 12, pts. 7 and 14). I816b does not explicitly disclose, "A second edge-emitting semiconductor laser chip." "A single submount for supporting the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip." "Wherein the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are located on the electrodes." "[The first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are located] adjacently to each other in a first direction." "The first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip each include a semiconductor substrate and a stacked growth layer." "The second edge-emitting semiconductor laser chip includes n laser resonators (n > 1) extending in the second direction." Egawa discloses, "A second edge-emitting semiconductor laser chip" (p. [0232] and Fig. 13A, pt. 65). "A single submount for supporting the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip" (p. [0232] and Fig. 13A, pts. 65 and 80). "Wherein the first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are located on the electrodes" (p. [0232] and Fig. 13A, pt. 65, where splitting chip 8 of I816b into two chips as with Egawa results in the two chips reflecting the arrangement of Figure 12 of Egawa except being separated into two chips at the center of chip 8). "[The first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip are located] adjacently to each other in a first direction" (p. [0232] and Fig. 13A, pt. 65). "The first edge-emitting semiconductor laser chip and the second edge-emitting semiconductor laser chip each include a semiconductor substrate and a stacked growth layer" (p. [0237] and Fig. 13A, pts. 66 and 70). "The second edge-emitting semiconductor laser chip includes n laser resonators (n > 1) extending in the second direction" (p. [0235] and Fig. 13A, pts. 65 and 70). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of I816b with the teachings of Egawa. In view of the teachings of I816b regarding a laser array mounted to a submount, the alternate construction of the laser array by splitting the emitters across several chips as taught by Egawa would enhance the teachings of I816b by allowing stress within the laser chips to be reduced.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over I816b, in view of Egawa, and further in view of Nakatsuka et al. (Nakatsuka, US Pub. 2002/0172245).
Regarding claim 21, The combination of I816b and Egawa does not explicitly disclose, "At least one of the electrodes has a longer length in the first direction than the remaining one of the electrodes." Nakatsuka discloses, "At least one of the electrodes has a longer length in the first direction than the remaining one of the electrodes" (p. [0036] and Fig. 1, pt. 117). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of I816b and Egawa with the teachings of Nakatsuka. In view of the teachings of I816b regarding a laser array mounted to a submount, the alternate construction of the outer electrodes to be wider than the inner electrodes as taught by Nakatsuka would enhance the teachings of I816b and Egawa by allowing the emitters to be compactly arranged while reducing fabrication constraints on the outer electrodes.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Aoki et al. (Aoki, US Patent 5,561,682) is cited for teaching a laser array in which various emitters emit at different wavelengths.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN P HAGAN/Examiner, Art Unit 2828
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