Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant' s arguments, see pages 5-21, filed on 23 September 2026, with respect to the rejections of claims 1-20 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim et al. (US 2023/0400985) for claims 1, 5, 6, 8, and 15; Kim et al. (US 2023/0400985) in view of Farahani et al. (US 2018/0081590) for claims 2, 9, and 16; and Kim et al. (US 2023/0400985) in view of Prodromou et al. (US 2018/0107598) for claims 3, 4, 7, 10, 11, 14, 17, 18, and 20.
Claim Objections
Claims 1, 8, and 15 are objected to because of the following informalities:
In claim 1, PIM is defined as “processor in memory circuitry” (emphasis added). In claims 8 and 15, PIM is defined as “processing in memory unit” and “processing in memory circuitry” respectively (emphasis added). It is suggested to choose one consistent definition for the PIM acronym and use it uniformly throughout the claim set.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 6, 8, 12, 13, 15, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2023/0400985, hereinafter Kim).
Regarding claim 1, Kim discloses
A method comprising (fig. 1-8):
in response to receiving an instruction to store data at a location in a memory (paragraph [0034]: The CPU 10 may transmit a memory request to the DMA engine 20; paragraph [0052]: The descriptor may include operation information, operand address information, and next descriptor address information … The operand address information may include a source address and a destination address; Note: Kim’s memory request transmitted from the CPU to the DMA engine, which points to a descriptor containing a destination address, reads on the claimed receiving an instruction to store data at a location in a memory),
determining, at processor in memory (PIM) circuitry of a processor external to the memory, a memory address within the location in the memory (paragraph [0014]: In an embodiment, the PIM system may perform a PIM computation offloading method using a direct memory access (DMA) engine; paragraph [0059]: The DMA engine 20 may read the descriptor from the memory 30 … the DMA engine 20 may parse the descriptor; Note: Kim’s DMA engine 20 acts as the claimed PIM circuitry. By reading and parsing the descriptor from memory to extract the operand address information/destination address, the DMA engine is determining a memory address within the location in the memory); and
issuing, by the PIM circuitry, instructions to store data in the memory address within the location in the memory to a PIM unit of the memory (paragraph [0060]: The DMA engine 20 may transmit a descriptor request and a PIM request to the PIM device 50 … The PIM device 50 may perform a PIM computation corresponding to the PIM request; paragraph [0062]: The PIM device 50 may execute a transaction corresponding to the PIM request; Note: The DMA engine 20 transmitting the PIM request to the PIM device 50 to execute the transaction at the determined destination address reads on issuing instructions to store data in the memory address to a PIM unit of the memory. Furthermore, Kim explicitly teaches receiving a singular memory request from the CPU and issuing multiple instructions, e.g., a descriptor request and a PIM request, to the PIM device).
Regarding claim 8 referring to claim 1, Kim discloses A processing system, comprising (fig. 1-8): a memory including a processing in memory (PIM) unit; and a processor coupled to the memory, the processor external to the memory (paragraph [0014]: a host device including a central processing unit (CPU) and a direct memory access (DMA) engine … and a PIM device; paragraph [0033]: The PIM system 1 may include a CPU 10, a DMA engine 20, and a memory 30; Note: Kim’s memory 30 is a PIM device that includes a PIM unit, and the CPU 10 acts as the processor external to the memory) and comprising: a plurality of processor cores (paragraph [0034]: The CPU 10 may include one or more cores; Note: Kim explicitly teaches the processor includes cores); and PIM circuitry configured to: … (See the rejection for claim 1).
Regarding claim 15 referring to claim 1, Kim discloses A processor, comprising (fig. 1-8): a plurality of processor cores (paragraph [0014]: a host device including a central processing unit (CPU); paragraph [0033]: The PIM system 1 may include a CPU 10; paragraph [0034]: The CPU 10 may include one or more cores; Note: Kim’s host CPU acts as the claimed processor and explicitly includes one or more core); and processing in memory (PIM) circuitry configured to: … (See the rejection for claim 1).
Regarding claims 5, 12, and 19, Kim discloses
wherein the location in the memory indicates a channel of the memory (paragraph [0052]: The descriptor may include operation information, operand address information, and next descriptor address information … The operand address information may include a source address and a destination address; paragraph [0022]: The memory 30 may include a plurality of memory channels, ranks, and banks; Note: Kim explicitly teaches that the memory includes multiple channels, and the operand address information (destination address) used by the DMA engine to access the memory inherently indicates the specific memory channel, rank, and bank where the data is to be stored. In particular, Kim’s DMA engine (PIM circuitry) parses the descriptor to extract the destination address (location in the memory), and in a standard multi-channel memory architecture as described by Kim, this destination address inherently indicates a channel of the memory to route the PIM request to the correct physical memory location).
Regarding claims 6 and 13, Kim discloses
wherein the PIM circuitry is included in a direct memory access (DMA) circuitry of the processor (paragraph [0014]: In an embodiment, the PIM system may perform a PIM computation offloading method using a direct memory access (DMA) engine; paragraph [0034]: The CPU 10 may transmit a memory request to the DMA engine 20; Note: Kim explicitly teaches that the system uses a DMA engine to perform the PIM computation offloading operations. In particular, the DMA engine of Kim acts as the claimed PIM circuitry that intercepts requests, determines the memory address, and issues instructions to the PIM device. Therefore, Kim explicitly teaches that the PIM circuitry is implemented as, and included in a direct memory access (DMA) circuitry of the processor).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made
Claims 2, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0400985, hereinafter Kim) in view of Farahani et al. (US 2018/0081590, hereinafter Farahani).
Regarding claims 2, 9, and 16, Kim does not explicitly disclose generating, at the PIM circuitry, a memory allocation request based on the location in the memory indicated by the instruction; and sending the memory allocation request to an operating system. Farahani discloses generating, at the PIM circuitry, a memory allocation request based on the location in the memory indicated by the instruction; and sending the memory allocation request to an operating system (fig. 1-4; paragraph [0018]: The buffer control module 125 allocates the temporary write buffer 135 by issuing a request having parameters, such as the size of the requested temporary write buffer. In at least one embodiment, the parameters may include a requested set of addresses of the entries of the fast memory 130 that are to compose the temporary write buffer 135. The buffer control module 125 issues the request and corresponding parameters to a memory management entity (not shown) for the processing system 100, such as an operating system (not shown) or a managed memory module (e.g., processing-in-memory or PIM); Note: Farahani’s buffer control module issuing a request having parameters that include a requested set of addresses to an operating system reads directly on generating a memory allocation request based on the location in the memory and sending it to an operating system).
In particular, Kim’s DMA engine acts as the claimed PIM circuitry. Farahani dislcoses an analogous hardware controller (buffer control module 125) that generates a memory allocation request for a requested set of addresses and sends it to an operating system. Applying Farahani’s hardware-to-OS allocation request logic to the DMA engine of Kim reads directly on the PIM circuitry generating a memory allocation request based on the location in the memory indicated by the instruction; and sending the memory allocation request to an operating system.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the DMA engine (i.e., PIM circuitry) of Kim to incorporate the hardware-to-OS memory allocation request mechanism of Farahani. The motivation would have been to allow the hardware to dynamically request and allocate specific memory locations from the host operating system to store temporary data or descriptors, thereby preventing buffer overflows and improving overall memory management efficiency between the host OS and the hardware (Farahani, paragraphs [0008], [0018]).
Claims 3, 4, 7, 10, 11, 14, 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0400985, hereinafter Kim) in view of Prodromou et al. (US 2018/0107598, hereinafter Prodromou).
Regarding claims 3, 10, and 17, Kim does not explicitly disclose wherein the PIM circuitry is configured to determine the memory address within the location in the memory based on a memory mapping associated with the memory. Prodromou discloses wherein the PIM circuitry is configured to determine the memory address within the location in the memory based on a memory mapping associated with the memory (fig. 1-11; paragraph [0046]: remapping record 600 includes a set of data triples in which a page ID 602 is associated with a source 604 and a destination 606 … cluster manager 124 can determine a location where the page is currently/actually stored based on the corresponding destination 606. By using the remapping record to translate locations as described, the described embodiments enable cluster manager 124 to perform migrations; paragraph [0075]: The cluster manager then determines, based on a remapping record, a portion of memory in a migration cluster in which the memory access is to be performed (step 902). For the determining, the cluster manager may use some or all of the indicator of the page to find a record for the page in the remapping record, and may acquire a current location of the page from the record of the page; Note: Prodromou’s cluster manager acts as the hardware circuitry/PIM circuitry. The use of the remapping record to translate locations and determine the current location/portion of memory for the page reads directly on determining the memory address based on a memory mapping associated with the memory).
In particular, Kim’s DMA engine acts as the claimed PIM circuitry. Prodromou discloses a hardware controller located on a processor (cluster manager 124) that utilizes a remapping record to translate locations and determine the current portion of memory for a page. Applying Prodromou’s hardware-based remapping record logic to the DMA engine of Kim reads directly on the PIM circuitry determining the memory address based on a memory mapping associated with the memory.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the DMA engine (i.e., PIM circuitry) of Kim to incorporate the memory mapping logic (remapping records) of Prodromou. The motivation would have been to allow the hardware to dynamically track and translate the current physical locations of data pages that have been migrated between different levels of the memory hierarchy, thereby ensuring memory access requests are directed to the proper portions of memory without requiring operating system involvement (Prodromou, paragraphs [0046], [0073]).
Regarding claims 4, 11, and 18, Kim does not explicitly disclose wherein the PIM circuitry is configured to hash the memory address based on the memory mapping associated with the memory. Prodromou discloses wherein the PIM circuitry is configured to hash the memory address based on the memory mapping associated with the memory (fig. 1-11; paragraph [0044]: Generally, the access record and the remapping record are data structures (lists, tables, hashes, etc.) that include information about page accesses and page locations, respectively; Note: Prodromou explicitly discloses that the data structure used for the memory mapping/remapping record can be implemented as a hash, which inherently requires hashing the memory address or identifier to perform the lookup based on the memory mapping).
In particular, Kim’s DMA engine acts as the claimed PIM circuitry. Prodromou discloses that the hardware controller (cluster manager) can utilize a hash-based data structure for its remapping records. Applying Prodromou’s hash-based mapping logic to the DMA engine of Kim reads directly on the PIM circuitry hashing the memory address based on the memory mapping associated with the memory.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the DMA engine (i.e., PIM circuitry) of Kim to incorporate the hash-based memory mapping data structures of Prodromou. The motivation would have been to enable rapid and efficient lookups of current page locations within the memory mapping data structures, thereby reducing memory access latency and computational overhead when translating physical addresses (Prodromou, paragraph [0044]).
Regarding claims 7, 14, and 20, Kim does not explicitly disclose wherein the memory comprises a stacked memory. Prodromou discloses wherein the memory comprises a stacked memory (fig. 1-11; paragraph [0031]: High-bandwidth memory 106 includes memory circuits such DRAM, DDR SDRAM, and/or other types of memory circuits … In some embodiments, high-bandwidth memory 106 includes one or more stacks of DRAM chips (or “stacked DRAM”) that are used for storing data and instructions; paragraph [0036]: computing device 100 includes a package 200 on which a processor 102 (e.g., a processor integrated circuit chip) and four stacked DRAM modules are mounted; Note: Prodromou explicitly discloses implementing the memory as a stacked memory, such as stacked DRAM modules).
In particular, Kim teaches a memory for storing data and performing PIM computations. Prodromou teaches that memory hierarchies in computing devices advantageously utilize stacked memory (e.g., stacked DRAM) to provide high-bandwidth memory access. Applying Prodromou’s stacked memory architecture to the memory system of Kim reads directly on wherein the memory comprises a stacked memory.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory of Kim to comprise a stacked memory as taught by Prodromou. The motivation would have been to provide a higher bandwidth and significantly faster data rate for data transfers between the processor and the memory, thereby improving the overall performance, speed, and efficiency of the PIM computations (Prodromou, paragraphs [0031], [0037]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yoon et al. (US 2022/0253248) discloses “the command generator 123 may identify whether an address included in a memory request corresponds to a general memory area or the PIM memory area based on an area separating bit included in the memory request” (paragraph [0047]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISLEY N. KIM whose telephone number is (571)270-7832. The examiner can normally be reached M-F 11:30AM -7:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y. Blair can be reached on (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISLEY N KIM/Primary Examiner, Art Unit 2196 10/13/2026
