Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to Applicant’s Amendment filed 03/31/2026. Claims 1-20 are pending. Claim 1 has been amended. Any examiner’s note, objection, or rejection not repeated is withdrawn due to Applicant’s amendment.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 8-10, 12, 15-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Song (US 20230033179 A1) in view of Nagarajan et al. (US 20210303978 A1), hereinafter referred to as Song and Nagarajan, respectively.
Regarding Claim 1, Song discloses A method ([0087] Various embodiments are directed to PIM systems and methods of operating the PIM systems. Please note that the method of operating the PIM systems corresponds to Applicant’s method.) comprising: determining, at processor in memory (PIM) circuitry of a processor external to the memory, a memory address within the location in the memory ( [0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500.; [0162] The PIM controller 500 may be configured to include the command queue logic 210, the scheduler 220, the memory command generator 230, a MAC command generator 540, and an address generator 550. […] The memory command generator 230 may receive the command queue related to the memory mode of the PIM device 400 from the command queue logic 210 to generate and output the memory command M_CMD.; [0164] The address generator 550 may receive address information from the command queue logic 210. The address generator 550 may generate the bank selection signal BS for selecting a memory bank where, for example, the memory bank 411 represents multiple memory banks. The address generator 550 may transmit the bank selection signal BS to the PIM device 400. In addition, the address generator 550 may generate the row address ADDR_R and the column address ADDR_C for accessing a region (e.g., memory cells) in the memory bank 411 and may transmit the row address ADDR_R and the column address ADDR_C to the PIM device 400. Please note that the PIM controller 500 with the address generator 550 generating the bank selection signal BS for selecting a memory bank that may generate the row address ADDR_R and the column address ADDR_C for accessing a region (e.g., memory cells) in the memory bank 411 to be transmitted to the PIM device 400 corresponds to Applicant’s determining a memory address within the location in the memory, i.e., ADDR_R/ADDR_C in the memory bank 411, via the PIM circuitry of a processor external to the memory, i.e., via the PIM controller 500. Furthermore, it performs this sequence in response to receiving the memory command M_CMD.);
and issuing, by the PIM circuitry, instructions to store data in the memory address within the location in the memory to a PIM unit of the memory ([0103] the memory command M_CMD may include a memory read command and a memory write command.; [0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500.; [0162] The PIM controller 500 may be configured to include the command queue logic 210, the scheduler 220, the memory command generator 230, a MAC command generator 540, and an address generator 550. […] The memory command generator 230 may receive the command queue related to the memory mode of the PIM device 400 from the command queue logic 210 to generate and output the memory command M_CMD.; [0164] The address generator 550 may receive address information from the command queue logic 210. The address generator 550 may generate the bank selection signal BS for selecting a memory bank where, for example, the memory bank 411 represents multiple memory banks. The address generator 550 may transmit the bank selection signal BS to the PIM device 400. In addition, the address generator 550 may generate the row address ADDR_R and the column address ADDR_C for accessing a region (e.g., memory cells) in the memory bank 411 and may transmit the row address ADDR_R and the column address ADDR_C to the PIM device 400. Please note that the PIM controller 500 issuing a memory command M_CMD and addresses ADDR_R and ADDR_C for a accessing a region in the memory bank 411 to a PIM device 400, where the memory command M_CMD may include a memory write command, corresponds to Applicant’s issuing instructions to store data in the memory address within the location in the memory to a PIM unit of the memory. This is because the PIM controller 500 issuing the M_CMD including a memory write command and ADDR_R/ADDR_C addresses of the memory bank 411 corresponds to the PIM circuitry issuing instructions to store data in the memory address within the location in the memory, and the PIM device 400 corresponds to the PIM unit of the memory.).
Song does not explicitly disclose in response to receiving an instruction to store data at a location in a memory, determining a memory address within the location in the memory
However, Nagarajan discloses in response to receiving an instruction to store data at a location in a memory, determining a memory address within the location in the memory ([0009] each request of the multiple requests specifying an address for a memory location that stores the input; determining, based on the dispatch algorithm, an allocation of addresses corresponding to each of the multiple requests; and distributing the multiple requests to the multiple channel controllers based on the determined allocation of addresses. Please note that a request that specifies an address for a memory location storing the input corresponds to Applicant’s receiving an instruction to store data at a location in memory, as a request corresponds to a received instruction that causes action to be taken in response. Additionally, determining an allocation of addresses corresponding to the request corresponds to Applicant’s determining a memory address within the location in the memory in response. Furthermore, it is known in the art that a memory location that stores data requires a computer operation to have been conducted to store the data within that location. Therefore, it would have been obvious to a person of ordinary skill in the art prior to the filing date of the invention to have issued a request to store data in the specified address.),
Song and Nagarajan are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Song to incorporate the teachings of Nagarajan to modify the system with a PIM determining a memory address and issuing instructions to store data in the memory address to the PIM to do so in response to receiving instructions to store data at the location in memory, allowing for improved efficiency of operation of the system, as described in Nagarajan.
Regarding Claim 2, Song-Nagarajan as described in Claim 1, Song further discloses at the PIM circuitry ([0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500. Please note that the PIM controller 500 operating with memory locations and sending memory commands corresponds to Applicant’s PIM circuitry.)
Nagarajan further discloses generating a memory allocation request based on the location in the memory indicated by the instruction ([0035] Relatedly, each channel controller may be allocated a portion of resources, such as a buffer, from a shared scratchpad memory space to perform certain operations using the retrieved data. Because the number of addresses (or requests) processed by each channel controller is different, the number of scratchpad memory/buffer locations used by each channel controller will also be quite different. Please note that allocating resources such as a buffer from a shared scratchpad memory at different locations to perform certain operations corresponds to generating a memory allocation request based on the location in the memory indicated by the instruction, as it allocates memory from a specific shared scratchpad memory at a certain location of the buffer corresponding to the location in the memory indicated by the instruction, and doing so in order to process a request corresponds to generating a request.); and sending the memory allocation request to an operating system ([0102] The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes […] an operating system. Please note that performing the allocation of resources such as a buffer (as mentioned in the previous citation) in a system containing code creating an execution environment for the computer program such as code that constitutes an operating system corresponds to sending the memory allocation request to an operating system, as it is known in the art that an operating system is the intermediary system which controls such operations as the fulfillment of allocation requests and the management of buffers required for computer programs to function.).
Regarding Claim 3, Song-Nagarajan as described in Claim 1, Song further discloses wherein the PIM circuitry is configured to ([0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500. Please note that the PIM controller 500 operating with memory locations and sending memory commands corresponds to Applicant’s PIM circuitry that is configured.)
Nagarajan further discloses determine the memory address within the location in the memory based on a memory mapping associated with the memory ([0033] each channel controller was mapped to a specific bank or channel in the large system memory, such that each channel controller could process only those addresses for memory locations to which the channel controller was mapped. Please note that each channel controller being mapped to a specific channel in the large system memory such that each channel controller can only process the addresses for memory locations to which it is mapped corresponds to Applicant’s being configured to determine the memory address within the location in the memory based on a memory mapping associated with the memory, as the specific mapping of the channel controller to a specific channel in the large system memory corresponds to a memory mapping associated with the memory, and only processing the addresses for memory locations to which it is mapped corresponds to determining the memory address within the location in the memory, as it uses the mapping to determine which addresses are available for the channel controller to process as part of its function.).
Regarding Claim 5, Song-Nagarajan as described in Claim 1, Nagarajan further discloses wherein the location in the memory indicates a channel of the memory ([0010] Each channel of the multiple channels in the memory can include a set of memory locations. Please note that each channel of the multiple channels in the memory including a set of memory locations corresponds to Applicant’s location in the memory indication a channel of the memory, as it would be obvious to utilize this mapping to determine a memory channel indicated by a particular memory location.).
Regarding Claim 8, Song discloses A processing system comprising: a memory including a processing in memory (PIM) unit ([0155] the PIM system 1-2 may be configured to include a PIM device 400 and a PIM controller 500. The PIM device 400 may be configured to include a memory bank (BANK) 411 corresponding to a storage region, a global buffer 412, a MAC operator 420, an interface (I/F) 431, and a data input/output (I/O) pad 432. Please note that the PIM device 400 including a memory bank 411 included in the PIM system corresponds to Applicant’s processing system comprising a memory including a PIM unit, with the memory bank 411 corresponding to the memory, and the PIM device 400 corresponding to the PIM unit.);
and a processor coupled to the memory, ([0160] The external device to the PIM device 400 may correspond to the PIM controller 500 of the PIM system 1-2. Please note that the PIM controller 500 that is an external device to the PIM device 400 corresponds to Applicant’s processor coupled to the memory.);
external to the memory ([0160] The external device to the PIM device 400 may correspond to the PIM controller 500 of the PIM system 1-2. Please note that the PIM controller 500 being external to the PIM device 400 corresponds to the processor being external to the memory.);
and PIM circuitry configured (([0160] The external device to the PIM device 400 may correspond to the PIM controller 500 of the PIM system 1-2.; [0161] The PIM controller 500 may control operations of the PIM device 400. Please note that the PIM controller 500 that is an external device to the PIM device 400 corresponds to Applicant’s PIM circuitry, as it contains circuitry to control the operations of the PIM device 400.);to:
determine a memory address within the location in the memory ( [0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500.; [0162] The PIM controller 500 may be configured to include the command queue logic 210, the scheduler 220, the memory command generator 230, a MAC command generator 540, and an address generator 550. […] The memory command generator 230 may receive the command queue related to the memory mode of the PIM device 400 from the command queue logic 210 to generate and output the memory command M_CMD.; [0164] The address generator 550 may receive address information from the command queue logic 210. The address generator 550 may generate the bank selection signal BS for selecting a memory bank where, for example, the memory bank 411 represents multiple memory banks. The address generator 550 may transmit the bank selection signal BS to the PIM device 400. In addition, the address generator 550 may generate the row address ADDR_R and the column address ADDR_C for accessing a region (e.g., memory cells) in the memory bank 411 and may transmit the row address ADDR_R and the column address ADDR_C to the PIM device 400. Please note that the PIM controller 500 with the address generator 550 generating the bank selection signal BS for selecting a memory bank that may generate the row address ADDR_R and the column address ADDR_C for accessing a region (e.g., memory cells) in the memory bank 411 to be transmitted to the PIM device 400 corresponds to Applicant’s determining a memory address within the location in the memory, i.e., ADDR_R/ADDR_C in the memory bank 411, via the PIM circuitry of a processor external to the memory, i.e., via the PIM controller 500. Furthermore, it performs this sequence in response to receiving the memory command M_CMD.);
and issue instructions to store data in the memory address within the location in the memory to the PIM unit of the memory ([0103] the memory command M_CMD may include a memory read command and a memory write command.; [0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500.; [0162] The PIM controller 500 may be configured to include the command queue logic 210, the scheduler 220, the memory command generator 230, a MAC command generator 540, and an address generator 550. […] The memory command generator 230 may receive the command queue related to the memory mode of the PIM device 400 from the command queue logic 210 to generate and output the memory command M_CMD.; [0164] The address generator 550 may receive address information from the command queue logic 210. The address generator 550 may generate the bank selection signal BS for selecting a memory bank where, for example, the memory bank 411 represents multiple memory banks. The address generator 550 may transmit the bank selection signal BS to the PIM device 400. In addition, the address generator 550 may generate the row address ADDR_R and the column address ADDR_C for accessing a region (e.g., memory cells) in the memory bank 411 and may transmit the row address ADDR_R and the column address ADDR_C to the PIM device 400. Please note that the PIM controller 500 issuing a memory command M_CMD and addresses ADDR_R and ADDR_C for a accessing a region in the memory bank 411 to a PIM device 400, where the memory command M_CMD may include a memory write command, corresponds to Applicant’s issuing instructions to store data in the memory address within the location in the memory to a PIM unit of the memory. This is because the PIM controller 500 issuing the M_CMD including a memory write command and ADDR_R/ADDR_C addresses of the memory bank 411 corresponds to the PIM circuitry issuing instructions to store data in the memory address within the location in the memory, and the PIM device 400 corresponds to the PIM unit of the memory.).
Song does not explicitly disclose the processor comprising: a plurality of processor cores;
in response to receiving an instruction from a processor core of the plurality of processor cores to store data at a location in the memory, determine a memory address within the location in the memory
However, Nagarajan discloses the processor comprising: a plurality of processor cores ([0043] a multi-core processing unit 104.);
in response to receiving an instruction from a processor core of the plurality of processor cores to store data at a location in the memory, determine a memory address within the location in the memory ([0009] each request of the multiple requests specifying an address for a memory location that stores the input; determining, based on the dispatch algorithm, an allocation of addresses corresponding to each of the multiple requests; and distributing the multiple requests to the multiple channel controllers based on the determined allocation of addresses. Please note that a request that specifies an address for a memory location storing the input corresponds to Applicant’s receiving an instruction to store data at a location in memory, as a request corresponds to a received instruction that causes action to be taken in response. Additionally, determining an allocation of addresses corresponding to the request corresponds to Applicant’s determining a memory address within the location in the memory in response. Furthermore, it is known in the art that a memory location that stores data requires a computer operation to have been conducted to store the data within that location. Therefore, it would have been obvious to a person of ordinary skill in the art prior to the filing date of the invention to have issued a request to store data in the specified address.),
Song and Nagarajan are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Song to incorporate the teachings of Nagarajan to modify the system with a PIM determining a memory address and issuing instructions to store data in the memory address to the PIM to do so in response to receiving instructions to store data at the location in memory and to use multiple processor cores, allowing for improved efficiency of operation of the system, as described in Nagarajan.
Regarding Claim 9, Song-Nagarajan as described in Claim 8, Song further discloses the PIM circuitry is configured to: ([0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500. Please note that the PIM controller 500 operating with memory locations and sending memory commands corresponds to Applicant’s PIM circuitry.)
Nagarajan further discloses generate a memory allocation request based on the location in the memory indicated by the instruction ([0035] Relatedly, each channel controller may be allocated a portion of resources, such as a buffer, from a shared scratchpad memory space to perform certain operations using the retrieved data. Because the number of addresses (or requests) processed by each channel controller is different, the number of scratchpad memory/buffer locations used by each channel controller will also be quite different. Please note that allocating resources such as a buffer from a shared scratchpad memory at different locations to perform certain operations corresponds to generating a memory allocation request based on the location in the memory indicated by the instruction, as it allocates memory from a specific shared scratchpad memory at a certain location of the buffer corresponding to the location in the memory indicated by the instruction, and doing so in order to process a request corresponds to generating a request.); and send the memory allocation request to an operating system associated with the processor ([0102] The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes […] an operating system. Please note that performing the allocation of resources such as a buffer (as mentioned in the previous citation) in a system containing code creating an execution environment for the computer program such as code that constitutes an operating system corresponds to sending the memory allocation request to an operating system, as it is known in the art that an operating system is the intermediary system which controls such operations as the fulfillment of allocation requests and the management of buffers required for computer programs to function.).
Regarding Claim 10, Song-Nagarajan as described in Claim 8, Song further discloses wherein the PIM circuitry is configured to ([0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500. Please note that the PIM controller 500 operating with memory locations and sending memory commands corresponds to Applicant’s PIM circuitry that is configured.)
Nagarajan further discloses determine the memory address within the location in the memory based on a memory mapping associated with the memory ([0033] each channel controller was mapped to a specific bank or channel in the large system memory, such that each channel controller could process only those addresses for memory locations to which the channel controller was mapped. Please note that each channel controller being mapped to a specific channel in the large system memory such that each channel controller can only process the addresses for memory locations to which it is mapped corresponds to Applicant’s being configured to determine the memory address within the location in the memory based on a memory mapping associated with the memory, as the specific mapping of the channel controller to a specific channel in the large system memory corresponds to a memory mapping associated with the memory, and only processing the addresses for memory locations to which it is mapped corresponds to determining the memory address within the location in the memory, as it uses the mapping to determine which addresses are available for the channel controller to process as part of its function.).
Regarding Claim 12, Song-Nagarajan as described in Claim 8, Nagarajan further discloses wherein the location in the memory indicates a channel of the memory ([0010] Each channel of the multiple channels in the memory can include a set of memory locations. Please note that each channel of the multiple channels in the memory including a set of memory locations corresponds to Applicant’s location in the memory indication a channel of the memory, as it would be obvious to utilize this mapping to determine a memory channel indicated by a particular memory location.).
Regarding Claim 15, Song discloses A processor and processing in memory (PIM) circuitry configured ([0160] The external device to the PIM device 400 may correspond to the PIM controller 500 of the PIM system 1-2.; [0161] The PIM controller 500 may control operations of the PIM device 400. Please note that the PIM controller 500 that is an external device to the PIM device 400 corresponds to Applicant’s processor comprising a configured PIM circuitry, as it contains circuitry to control the operations of the PIM device 400.) ;
external to the processor ([0155] the PIM system 1-2 may be configured to include a PIM device 400 and a PIM controller 500. The PIM device 400 may be configured to include a memory bank (BANK) 411 corresponding to a storage region; [0160] The external device to the PIM device 400 may correspond to the PIM controller 500 of the PIM system 1-2. Please note that the PIM controller 500 being external to the PIM device 400 corresponds to the location in a memory being external to the processor, as the PIM controller 500 is external to the PIM device 400 which includes the memory bank 411.);
to:
determine a memory address within the location in the memory ( [0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500.; [0162] The PIM controller 500 may be configured to include the command queue logic 210, the scheduler 220, the memory command generator 230, a MAC command generator 540, and an address generator 550. […] The memory command generator 230 may receive the command queue related to the memory mode of the PIM device 400 from the command queue logic 210 to generate and output the memory command M_CMD.; [0164] The address generator 550 may receive address information from the command queue logic 210. The address generator 550 may generate the bank selection signal BS for selecting a memory bank where, for example, the memory bank 411 represents multiple memory banks. The address generator 550 may transmit the bank selection signal BS to the PIM device 400. In addition, the address generator 550 may generate the row address ADDR_R and the column address ADDR_C for accessing a region (e.g., memory cells) in the memory bank 411 and may transmit the row address ADDR_R and the column address ADDR_C to the PIM device 400. Please note that the PIM controller 500 with the address generator 550 generating the bank selection signal BS for selecting a memory bank that may generate the row address ADDR_R and the column address ADDR_C for accessing a region (e.g., memory cells) in the memory bank 411 to be transmitted to the PIM device 400 corresponds to Applicant’s determining a memory address within the location in the memory, i.e., ADDR_R/ADDR_C in the memory bank 411, via the PIM circuitry of a processor external to the memory, i.e., via the PIM controller 500. Furthermore, it performs this sequence in response to receiving the memory command M_CMD.);
and issue instructions to store data in the memory address within the location in the memory to a PIM unit of the memory ([0103] the memory command M_CMD may include a memory read command and a memory write command.; [0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500.; [0162] The PIM controller 500 may be configured to include the command queue logic 210, the scheduler 220, the memory command generator 230, a MAC command generator 540, and an address generator 550. […] The memory command generator 230 may receive the command queue related to the memory mode of the PIM device 400 from the command queue logic 210 to generate and output the memory command M_CMD.; [0164] The address generator 550 may receive address information from the command queue logic 210. The address generator 550 may generate the bank selection signal BS for selecting a memory bank where, for example, the memory bank 411 represents multiple memory banks. The address generator 550 may transmit the bank selection signal BS to the PIM device 400. In addition, the address generator 550 may generate the row address ADDR_R and the column address ADDR_C for accessing a region (e.g., memory cells) in the memory bank 411 and may transmit the row address ADDR_R and the column address ADDR_C to the PIM device 400. Please note that the PIM controller 500 issuing a memory command M_CMD and addresses ADDR_R and ADDR_C for a accessing a region in the memory bank 411 to a PIM device 400, where the memory command M_CMD may include a memory write command, corresponds to Applicant’s issuing instructions to store data in the memory address within the location in the memory to a PIM unit of the memory. This is because the PIM controller 500 issuing the M_CMD including a memory write command and ADDR_R/ADDR_C addresses of the memory bank 411 corresponds to the PIM circuitry issuing instructions to store data in the memory address within the location in the memory, and the PIM device 400 corresponds to the PIM unit of the memory.).
Song does not explicitly disclose comprising: a plurality of processor cores;
in response to receiving an instruction from a processor core of the plurality of processor cores to store data at a location in a memory, determine a memory address within the location in the memory
However, Nagarajan discloses comprising: a plurality of processor cores ([0043] a multi-core processing unit 104.);
in response to receiving an instruction from a processor core of the plurality of processor cores to store data at a location in the memory, determine a memory address within the location in the memory ([0009] each request of the multiple requests specifying an address for a memory location that stores the input; determining, based on the dispatch algorithm, an allocation of addresses corresponding to each of the multiple requests; and distributing the multiple requests to the multiple channel controllers based on the determined allocation of addresses. Please note that a request that specifies an address for a memory location storing the input corresponds to Applicant’s receiving an instruction to store data at a location in memory, as a request corresponds to a received instruction that causes action to be taken in response. Additionally, determining an allocation of addresses corresponding to the request corresponds to Applicant’s determining a memory address within the location in the memory in response. Furthermore, it is known in the art that a memory location that stores data requires a computer operation to have been conducted to store the data within that location. Therefore, it would have been obvious to a person of ordinary skill in the art prior to the filing date of the invention to have issued a request to store data in the specified address.),
Song and Nagarajan are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Song to incorporate the teachings of Nagarajan to modify the system with a PIM determining a memory address and issuing instructions to store data in the memory address to the PIM to do so in response to receiving instructions to store data at the location in memory and to use multiple processor cores, allowing for improved efficiency of operation of the system, as described in Nagarajan.
Regarding Claim 16, Song-Nagarajan as described in Claim 15, Song further discloses the PIM circuitry is configured to: ([0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500. Please note that the PIM controller 500 operating with memory locations and sending memory commands corresponds to Applicant’s PIM circuitry.)
Nagarajan further discloses generate a memory allocation request based on the location in the memory indicated by the instruction ([0035] Relatedly, each channel controller may be allocated a portion of resources, such as a buffer, from a shared scratchpad memory space to perform certain operations using the retrieved data. Because the number of addresses (or requests) processed by each channel controller is different, the number of scratchpad memory/buffer locations used by each channel controller will also be quite different. Please note that allocating resources such as a buffer from a shared scratchpad memory at different locations to perform certain operations corresponds to generating a memory allocation request based on the location in the memory indicated by the instruction, as it allocates memory from a specific shared scratchpad memory at a certain location of the buffer corresponding to the location in the memory indicated by the instruction, and doing so in order to process a request corresponds to generating a request.); and send the memory allocation request to an operating system associated with the processor ([0102] The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes […] an operating system. Please note that performing the allocation of resources such as a buffer (as mentioned in the previous citation) in a system containing code creating an execution environment for the computer program such as code that constitutes an operating system corresponds to sending the memory allocation request to an operating system, as it is known in the art that an operating system is the intermediary system which controls such operations as the fulfillment of allocation requests and the management of buffers required for computer programs to function.).
Regarding Claim 17, Song-Nagarajan as described in Claim 15, Song further discloses wherein the PIM circuitry is configured to ([0160] The interface 431 of the PIM device 400 may receive the memory command M_CMD, the MAC commands MAC_CMDs, the bank selection signal BS, and the row/column addresses ADDR_R/ADDR_C from the PIM controller 500. Please note that the PIM controller 500 operating with memory locations and sending memory commands corresponds to Applicant’s PIM circuitry that is configured.)
Nagarajan further discloses determine the memory address within the location in the memory based on a memory mapping associated with the memory ([0033] each channel controller was mapped to a specific bank or channel in the large system memory, such that each channel controller could process only those addresses for memory locations to which the channel controller was mapped. Please note that each channel controller being mapped to a specific channel in the large system memory such that each channel controller can only process the addresses for memory locations to which it is mapped corresponds to Applicant’s being configured to determine the memory address within the location in the memory based on a memory mapping associated with the memory, as the specific mapping of the channel controller to a specific channel in the large system memory corresponds to a memory mapping associated with the memory, and only processing the addresses for memory locations to which it is mapped corresponds to determining the memory address within the location in the memory, as it uses the mapping to determine which addresses are available for the channel controller to process as part of its function.).
Regarding Claim 19, Song-Nagarajan as described in Claim 15, Nagarajan further discloses wherein the location in the memory indicates a channel of the memory ([0010] Each channel of the multiple channels in the memory can include a set of memory locations. Please note that each channel of the multiple channels in the memory including a set of memory locations corresponds to Applicant’s location in the memory indication a channel of the memory, as it would be obvious to utilize this mapping to determine a memory channel indicated by a particular memory location.).
Claims 4, 7, 11, 14, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Song (US 20230033179 A1) in view of Nagarajan et al. (US 20210303978 A1) and further in view of Prodromou et al. (US 20180107598 A1), hereinafter referred to as Song, Nagarajan, and Prodromou, respectively.
Regarding Claim 4, Song-Nagarajan as described in Claim 3 does not explicitly disclose wherein the PIM circuitry is configured to hash the memory address based on the memory mapping associated with the memory.
However, Prodromou discloses wherein the PIM circuitry is configured to hash the memory address based on the memory mapping associated with the memory ([0044] Generally, the access record and the remapping record are data structures (lists, tables, hashes, etc.) that include information about page accesses and page locations, respectively. Please note that hashes of the remapping record including information about page locations corresponds to Applicant’s hashing memory address based on the memory mapping associated with the memory, as it uses the remapping record corresponding to the memory mapping associated with the memory to corroborate to a hash containing information about its location, i.e., its address. It is known in the art that a page is a block of memory; therefore, this citation pertains to memory. Furthermore, to have a hash data structure paired to information about page locations indicates that hashing was performed via computer circuitry.).
Song-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Song-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to hash the memory address based on the associate memory mapping of the memory, allowing for improved performance of the system, as described in Prodromou.
Regarding Claim 7, Song-Nagarajan as described in Claim 1 does not explicitly disclose wherein the memory comprises a stacked memory.
However, Prodromou discloses wherein the memory comprises a stacked memory ([0038] Channels 116-122 are each coupled between processor 102 and a corresponding stacked DRAM module. Please note that the memory being a stacked DRAM module corresponds to Applicant’s memory comprising a stacked memory.).
Song-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Song-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to have the memory comprise a stacked memory, allowing for improved performance of the system, as described in Prodromou.
Regarding Claim 11, Song-Nagarajan as described in Claim 10 does not explicitly disclose hash the memory address based on the memory mapping associated with the memory.
However, Prodromou discloses hash the memory address based on the memory mapping associated with the memory ([0044] Generally, the access record and the remapping record are data structures (lists, tables, hashes, etc.) that include information about page accesses and page locations, respectively. Please note that hashes of the remapping record including information about page locations corresponds to Applicant’s hashing memory address based on the memory mapping associated with the memory, as it uses the remapping record corresponding to the memory mapping associated with the memory to corroborate to a hash containing information about its location, i.e., its address. It is known in the art that a page is a block of memory; therefore, this citation pertains to memory. Furthermore, to have a hash data structure paired to information about page locations indicates that hashing was performed via computer circuitry.).
Song-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Song-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to hash the memory address based on the associate memory mapping of the memory, allowing for improved performance of the system, as described in Prodromou.
Regarding Claim 14, Song-Nagarajan as described in Claim 8 does not explicitly disclose wherein the memory comprises a stacked memory.
However, Prodromou discloses wherein the memory comprises a stacked memory ([0038] Channels 116-122 are each coupled between processor 102 and a corresponding stacked DRAM module. Please note that the memory being a stacked DRAM module corresponds to Applicant’s memory comprising a stacked memory.).
Song-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Song-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to have the memory comprise a stacked memory, allowing for improved performance of the system, as described in Prodromou.
Regarding Claim 18, Song-Nagarajan as described in Claim 17 does not explicitly disclose hash the memory address based on the memory mapping associated with the memory.
However, Prodromou discloses hash the memory address based on the memory mapping associated with the memory ([0044] Generally, the access record and the remapping record are data structures (lists, tables, hashes, etc.) that include information about page accesses and page locations, respectively. Please note that hashes of the remapping record including information about page locations corresponds to Applicant’s hashing memory address based on the memory mapping associated with the memory, as it uses the remapping record corresponding to the memory mapping associated with the memory to corroborate to a hash containing information about its location, i.e., its address. It is known in the art that a page is a block of memory; therefore, this citation pertains to memory. Furthermore, to have a hash data structure paired to information about page locations indicates that hashing was performed via computer circuitry.).
Song-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Song-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to hash the memory address based on the associate memory mapping of the memory, allowing for improved performance of the system, as described in Prodromou.
Regarding Claim 20, Song-Nagarajan as described in Claim 15 does not explicitly disclose wherein the memory comprises a stacked memory.
However, Prodromou discloses wherein the memory comprises a stacked memory ([0038] Channels 116-122 are each coupled between processor 102 and a corresponding stacked DRAM module. Please note that the memory being a stacked DRAM module corresponds to Applicant’s memory comprising a stacked memory.).
Song-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Song-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to have the memory comprise a stacked memory, allowing for improved performance of the system, as described in Prodromou.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Song (US 20230033179 A1) in view of Nagarajan et al. (US 20210303978 A1) and further in view of Baxter et al. (US 8479124 B1), hereinafter referred to as Song, Nagarajan, and Baxter, respectively.
Regarding Claim 6, Song-Nagarajan as described in Claim 1 does not explicitly disclose wherein the PIM circuitry is included in a direct memory access (DMA) circuitry of the processor.
However, Baxter discloses wherein the PIM circuitry is included in a direct memory access (DMA) circuitry of the processor (Col. 15, Lines 55-58- a Communication Direct Memory Access Controller (CDMAC) PIM that contains an embedded intelligent Direct Memory Access (DMA) engine optimized for communication style data access to memory. While most often DMA engines are controlled by processors […]. Please note that a CDMAC PIM containing an embedded DMA engine controlled by processors corresponds to Applicant’s PIM circuitry included in a DMA circuitry of the processor, as the PIM is included in circuitry performing DMA operations and is controlled by processors.).
Song-Nagarajan and Baxter are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Song-Nagarajan to incorporate the teachings of Baxter to modify the system of Claim 1 to include the PIM circuitry in a DMA circuitry of the processor, allowing for improved performance of the system via optimized data access to the memory, as described in Baxter.
Regarding Claim 13, Song-Nagarajan as described in Claim 8 does not explicitly disclose wherein the processor further includes a direct memory access (DMA) circuitry and wherein the PIM circuitry is included in the DMA circuitry.
However, Baxter discloses wherein the processor further includes a direct memory access (DMA) circuitry and wherein the PIM circuitry is included in the DMA circuitry (Col. 15, Lines 55-58- a Communication Direct Memory Access Controller (CDMAC) PIM that contains an embedded intelligent Direct Memory Access (DMA) engine optimized for communication style data access to memory. While most often DMA engines are controlled by processors […]. Please note that a CDMAC PIM containing an embedded DMA engine controlled by processors corresponds to Applicant’s processor including DMA circuitry and PIM circuitry included in a DMA circuitry of the processor, as the PIM is included in circuitry performing DMA operations and is controlled by processors.).
Song-Nagarajan and Baxter are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Song-Nagarajan to incorporate the teachings of Baxter to modify the system of Claim 1 to include the PIM circuitry in a DMA circuitry of the processor, allowing for improved performance of the system via optimized data access to the memory, as described in Baxter.
Response to Arguments
Applicant's arguments filed 03/31/2026 have been fully considered but they are not persuasive.
Applicant’s arguments are summarized as follows:
Neither Yoon nor Nagarajan, alone or in combination, teach the limitations of Claim 8 that PIM circuitry of a processor external to a memory determines a memory address within a location of a memory and then issuing instructions to a PIM unit of the memory to store data at that memory address. This is because:
Yoon discloses a processor internal to a processing-in-memory system including a memory and not a PIM circuitry of a processor external to a memory. Yoon makes clear that the internal processor of a PIM circuitry including a memory is distinct from “an external processor 320,” which does not perform determining addresses within locations of a memory or issuing instructions to the processing-in-memory system to store data at that memory address. Yoon’s internal processor 120 cannot simultaneously disclose both the processor issuing instructions and the processor receiving those instructions
Nagarajan additionally does not remedy the deficiencies of Yoon, since it is silent to PIM circuitry of a processor external to a memory determining a memory address within a location of a memory and then issuing instructions to a PIM unit of the memory to store data at that memory address.
Therefore, neither of the references, alone or in combination, teach the claim limitations, and it overcomes the rejections under 35 U.S.C. 103.
Since Claims 1 and 15 contain similar limitations to Claim 8, which overcomes the rejections under 35 U.S.C. 103, they overcome the rejections under 35 U.S.C. 103 as well.
Since Claims 2, 3, 5, 9, 10, 12, 16, 17, and 19 depend from respective claims 1, 8, and 15, which overcome the rejections under 35 U.S.C. 103, they overcome the rejections under 35 U.S.C. 103 as well.
Regarding Claims 2, 9, and 16, Claim 2 recites “generating, at the PIM circuitry, a memory allocation request based on the location in the memory indicated by the instruction; and sending the memory allocation request to an operating system,” with Claims 9 and 16 reciting similar features. Examiner cites Nagarajan to teach these features, but this is unsupported, as Nagarajan discloses that channel controls are allocated buffers from a scratchpad memory distinct from memory 105, but is silent as to PIM circuitry making the allocations or that the allocations are based on a location indicated by an instruction received by the PIM circuitry. Nagarajan discloses channel controllers performing neural network computations based on the current allocation of shared resources to determine how to allocate the shared resources. Additionally, the Examiner does not provide a motivation for modifying Yon to incorporate the teachings of Nagarajan to arrive at the claimed features. Therefore, the rejections under 35 U.S.C. 103 for Claims 2, 9, and 16 should be withdrawn, as Yoon-Nagarajan does not teach the limitations.
Since Claims 4, 7, 11, 14, 18, and 20 depend from respective claims 1, 8, and 15, which overcome the rejections under 35 U.S.C. 103, and the combination with Prodromou does not remedy their deficiencies, they overcome the rejections under 35 U.S.C. 103 as well.
Since Claims 6 and 13 depend from respective claims 1, 8, and 15, which overcome the rejections under 35 U.S.C. 103, and the combination with Baxter does not remedy their deficiencies, they overcome the rejections under 35 U.S.C. 103 as well.
Regarding A, the examiner respectfully disagrees. the examiner respectfully disagrees. The Applicant’s arguments are moot, as the rejections of the Claim now relies on a new grounds of rejection, Song-Nagarajan, which discloses the limitations stated by the Applicant via the combination of references, as stated above.
Therefore, the recited features can be found in the cited combination of references, and independent Claim 1 remains rejected under 35 U.S.C. 103 for the reasons stated above, and the combinations cited would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the application. The rejections under 35 U.S.C. 103 are maintained.
Regarding B, the examiner respectfully disagrees. The Independent Claims 1 and 15 contain similar limitations to rejected Independent Claim 8 and do not add limitations that overcome the rejection; therefore, they likewise remain rejected, and the application is not in condition for allowance. The rejections under 35 U.S.C. 103 are maintained.
Regarding C, the examiner respectfully disagrees. The dependent claims 2, 3, 5, 9, 10, 12, 16, 17, and 19 depend on unpatentable claims and do not add limitations that overcome the rejection; therefore, they likewise remain rejected, and the application is not in condition for allowance. The rejections under 35 U.S.C. 103 are maintained.
Regarding D, the examiner respectfully disagrees. the examiner respectfully disagrees. The Applicant’s arguments are moot, as the rejections of the Claim now relies on a new grounds of rejection, Song-Nagarajan, which discloses the limitations stated by the Applicant via the combination of references, as stated above.
Therefore, the recited features can be found in the cited combination of references, and Claims 2, 9, and 16 remain rejected under 35 U.S.C. 103 for the reasons stated above, and the combinations cited would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the application. The rejections under 35 U.S.C. 103 are maintained.
Regarding E, the examiner respectfully disagrees. The dependent claims 4, 7, 11, 14, 18, and 20 depend on unpatentable claims and do not add limitations that overcome the rejection; therefore, they likewise remain rejected, and the application is not in condition for allowance. The rejections under 35 U.S.C. 103 are maintained.
Regarding F, the examiner respectfully disagrees. The dependent claims 6 and 13 depend on unpatentable claims and do not add limitations that overcome the rejection; therefore, they likewise remain rejected, and the application is not in condition for allowance. The rejections under 35 U.S.C. 103 are maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Song (US 20220197596 A1) discloses a PIM device and an external PIM controller that controls its operations, including data write operations for its memory banks with specified addresses (see [0076-0081]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARAZ T AKBARI whose telephone number is (571)272-4166. The examiner can normally be reached Monday-Thursday 9:30am-7:30pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FARAZ T AKBARI/Examiner, Art Unit 2196
/HIREN P PATEL/Primary Examiner, Art Unit 2196
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