Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to Applicant’s Amendment filed 12/15/2025. Claims 1-20 are pending. Claims 1,8, and 15 have been amended. Any examiner’s note, objection, or rejection not repeated is withdrawn due to Applicant’s amendment.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 8-10, 12, 15-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20220075713 A1) in view of Nagarajan et al. (US 20210303978 A1), hereinafter referred to as Yoon and Nagarajan, respectively.
Regarding Claim 1, Yoon discloses A method ([0015] a memory access method of a processing-in-memory) comprising: determining, at processor in memory (PIM) circuitry of a processor external to the memory, a memory address within the location in the memory ([0044] The processing-in-memory 100 may calculate the target physical address of the memory 110 to be accessed, through the internal processor 120 of the processing-in-memory 100. Please note that the processing-in-memory 100 calculating the target physical address of the memory 110 to be access through the internal processor 120 corresponds to Applicant’s determining at a PIM circuitry at a processor a memory address within the location in memory, as the processing-in-memory 100 corresponds to the PIM, the internal processor 120 corresponds to the processor, and the target physical address of the memory 110 corresponds to the memory address within the location in the memory. Additionally, since the internal processor 120 is distinct from the memory 110, this corresponds to the processor being external to the memory.);
and issuing instructions to store data in the memory address within the location in the memory to a PIM unit of the memory ([0043] The processing-in-memory 100 may generate a read or write instruction of the memory 110 for the PIM operation.; [0049] Thereafter, the internal processor 120 may perform (or execute) the instruction by accessing the target physical address. The processing-in-memory 100 may perform the read or write instruction by accessing the memory 110 at the target physical address. Please note that the PIM 100 generating a write instruction and performing the write instruction by accessing the memory 110 at the target physical address corresponds to Applicant’s issuing instructions to store data in the memory address within the location in the memory to a PIM unit of the memory, as the PIM 100 issues instructions to write to the target physical address, i.e., to store data in the memory address within the location in the memory.).
Yoon does not explicitly disclose in response to receiving an instruction to store data at a location in a memory,
However, Nagarajan discloses in response to receiving an instruction to store data at a location in a memory ([0009] each request of the multiple requests specifying an address for a memory location that stores the input. Please note that a request that specifies an address for a memory location storing the input corresponds to Applicant’s receiving an instruction to store data at a location in memory, as a request corresponds to a received instruction that causes action to be taken in response. Furthermore, it is known in the art that a memory location that stores data requires a computer operation to have been conducted to store the data within that location. Therefore, it would have been obvious to a person of ordinary skill in the art prior to the filing date of the invention to have issued a request to store data in the specified address.),
Yoon and Nagarajan are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Yoon to incorporate the teachings of Nagarajan to modify the system with a PIM determining a memory address and issuing instructions to store data in the memory address to the PIM to do so in response to receiving instructions to store data at the location in memory, allowing for improved efficiency of operation of the system, as described in Nagarajan.
Regarding Claim 2, Yoon-Nagarajan as described in Claim 1, Nagarajan further discloses generating, at the PIM circuitry, a memory allocation request based on the location in the memory indicated by the instruction ([0035] Relatedly, each channel controller may be allocated a portion of resources, such as a buffer, from a shared scratchpad memory space to perform certain operations using the retrieved data. Because the number of addresses (or requests) processed by each channel controller is different, the number of scratchpad memory/buffer locations used by each channel controller will also be quite different. Please note that allocating resources such as a buffer from a shared scratchpad memory at different locations to perform certain operations corresponds to generating a memory allocation request based on the location in the memory indicated by the instruction, as it allocates memory from a specific shared scratchpad memory at a certain location of the buffer corresponding to the location in the memory indicated by the instruction, and doing so in order to process a request corresponds to generating a request.); and sending the memory allocation request to an operating system ([0102] The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes […] an operating system. Please note that performing the allocation of resources such as a buffer (as mentioned in the previous citation) in a system containing code creating an execution environment for the computer program such as code that constitutes an operating system corresponds to sending the memory allocation request to an operating system, as it is known in the art that an operating system is the intermediary system which controls such operations as the fulfillment of allocation requests and the management of buffers required for computer programs to function.).
Regarding Claim 3, Yoon-Nagarajan as described in Claim 1, Nagarajan further discloses wherein the PIM circuitry is configured to determine the memory address within the location in the memory based on a memory mapping associated with the memory ([0033] each channel controller was mapped to a specific bank or channel in the large system memory, such that each channel controller could process only those addresses for memory locations to which the channel controller was mapped. Please note that each channel controller being mapped to a specific channel in the large system memory such that each channel controller can only process the addresses for memory locations to which it is mapped corresponds to Applicant’s being configured to determine the memory address within the location in the memory based on a memory mapping associated with the memory, as the specific mapping of the channel controller to a specific channel in the large system memory corresponds to a memory mapping associated with the memory, and only processing the addresses for memory locations to which it is mapped corresponds to determining the memory address within the location in the memory, as it uses the mapping to determine which addresses are available for the channel controller to process as part of its function.).
Regarding Claim 5, Yoon-Nagarajan as described in Claim 1, Nagarajan further discloses wherein the location in the memory indicates a channel of the memory ([0010] Each channel of the multiple channels in the memory can include a set of memory locations. Please note that each channel of the multiple channels in the memory including a set of memory locations corresponds to Applicant’s location in the memory indication a channel of the memory, as it would be obvious to utilize this mapping to determine a memory channel indicated by a particular memory location.).
Regarding Claim 8, Yoon discloses A processing system ([0028] systems described herein), comprising: a memory including a processing in memory (PIM) unit; and a processor coupled to the memory, ([0042] the processing-in-memory 100 of one or more embodiments may calculate the physical address (e.g., a target physical address) of the memory 110 through the internal processor 120. Please note that the memory 110 corresponds to Applicant’s memory including a 100 PIM unit, and the internal processor 120 corresponds to Applicant’s processor coupled to the memory.);
external to the memory ([0042] the processing-in-memory 100 of one or more embodiments may calculate the physical address (e.g., a target physical address) of the memory 110 through the internal processor 120. Please note that since the internal processor 120 is distinct from the memory 110, this corresponds to the processor being external to the memory.);
and PIM circuitry configured ([0009] the internal processor may be configured to perform a processing-in-memory (PIM) operation. Please note that the internal processor being configured to perform a PIM operation corresponds to Applicant’s processor including a configured PIM circuitry) to:
determine a memory address within the location in the memory ([0044] The processing-in-memory 100 may calculate the target physical address of the memory 110 to be accessed, through the internal processor 120 of the processing-in-memory 100. Please note that the processing-in-memory 100 calculating the target physical address of the memory 110 to be access through the internal processor 120 corresponds to Applicant’s determining at a PIM circuitry at a processor a memory address within the location in memory, as the processing-in-memory 100 corresponds to the PIM, the internal processor 120 corresponds to the processor, and the target physical address of the memory 110 corresponds to the memory address within the location in the memory.);
and issue instructions to store data in the memory address within the location in the memory to the PIM unit of the memory ([0043] The processing-in-memory 100 may generate a read or write instruction of the memory 110 for the PIM operation.; [0049] Thereafter, the internal processor 120 may perform (or execute) the instruction by accessing the target physical address. The processing-in-memory 100 may perform the read or write instruction by accessing the memory 110 at the target physical address. Please note that the PIM 100 generating a write instruction and performing the write instruction by accessing the memory 110 at the target physical address corresponds to Applicant’s issuing instructions to store data in the memory address within the location in the memory to a PIM unit of the memory, as the PIM 100 issues instructions to write to the target physical address, i.e., to store data in the memory address within the location in the memory.).
Yoon does not explicitly disclose the processor comprising: a plurality of processor cores;
in response to receiving an instruction from a processor core of the plurality of processor cores to store data at a location in the memory,
However, Nagarajan discloses the processor comprising: a plurality of processor cores ([0043] a multi-core processing unit 104.);
in response to receiving an instruction from a processor core of the plurality of processor cores to store data at a location in the memory ([0009] each request of the multiple requests specifying an address for a memory location that stores the input.; [0016] any address location of a memory cell in any channel of a high-bandwidth memory system that communicates with a processor core; [0043] the host 102 can be a processing unit, such as a processor, multiple processors, or multiple processor cores. Please note that a request that specifies an address for a memory location storing the input corresponds to Applicant’s receiving an instruction from a processor core of the plurality of processor cores to store data at a location in memory, as a request corresponds to a received instruction that causes action to be taken in response. Furthermore, it is known in the art that a memory location that stores data requires a computer operation to have been conducted to store the data within that location. Therefore, it would have been obvious to a person of ordinary skill in the art prior to the filing date of the invention to have issued a request to store data in the specified address. Additionally, the host 102 of the computing system consisting of multiple cores, where each address location of a memory cell in any channel of the memory system that communicates with a processor core corresponds to Applicant’s receiving an instruction from a processor core of the plurality of processor cores, as the system would receive communications, i.e., instructions, from a processor core.),
Yoon and Nagarajan are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Yoon to incorporate the teachings of Nagarajan to modify the system with a PIM determining a memory address and issuing instructions to store data in the memory address to the PIM to do so in response to receiving instructions to store data at the location in memory and to use multiple processor cores, allowing for improved efficiency of operation of the system, as described in Nagarajan.
Regarding Claim 9, Yoon-Nagarajan as described in Claim 8, Nagarajan further discloses generate a memory allocation request based on the location in the memory indicated by the instruction ([0035] Relatedly, each channel controller may be allocated a portion of resources, such as a buffer, from a shared scratchpad memory space to perform certain operations using the retrieved data. Because the number of addresses (or requests) processed by each channel controller is different, the number of scratchpad memory/buffer locations used by each channel controller will also be quite different. Please note that allocating resources such as a buffer from a shared scratchpad memory at different locations to perform certain operations corresponds to generating a memory allocation request based on the location in the memory indicated by the instruction, as it allocates memory from a specific shared scratchpad memory at a certain location of the buffer corresponding to the location in the memory indicated by the instruction, and doing so in order to process a request corresponds to generating a request.); and send the memory allocation request to an operating system associated with the processor ([0102] The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes […] an operating system. Please note that performing the allocation of resources such as a buffer (as mentioned in the previous citation) in a system containing code creating an execution environment for the computer program such as code that constitutes an operating system corresponds to sending the memory allocation request to an operating system, as it is known in the art that an operating system is the intermediary system which controls such operations as the fulfillment of allocation requests and the management of buffers required for computer programs to function.).
Regarding Claim 10, Yoon-Nagarajan as described in Claim 8, Nagarajan further discloses determine the memory address within the location in the memory based on a memory mapping associated with the memory ([0033] each channel controller was mapped to a specific bank or channel in the large system memory, such that each channel controller could process only those addresses for memory locations to which the channel controller was mapped. Please note that each channel controller being mapped to a specific channel in the large system memory such that each channel controller can only process the addresses for memory locations to which it is mapped corresponds to Applicant’s being configured to determine the memory address within the location in the memory based on a memory mapping associated with the memory, as the specific mapping of the channel controller to a specific channel in the large system memory corresponds to a memory mapping associated with the memory, and only processing the addresses for memory locations to which it is mapped corresponds to determining the memory address within the location in the memory, as it uses the mapping to determine which addresses are available for the channel controller to process as part of its function.).
Regarding Claim 12, Yoon-Nagarajan as described in Claim 8, Nagarajan further discloses wherein the location in the memory indicates a channel of the memory ([0010] Each channel of the multiple channels in the memory can include a set of memory locations. Please note that each channel of the multiple channels in the memory including a set of memory locations corresponds to Applicant’s location in the memory indication a channel of the memory, as it would be obvious to utilize this mapping to determine a memory channel indicated by a particular memory location.).
Regarding Claim 15, Yoon discloses A processor and processing in memory (PIM) circuitry configured ([0009] the internal processor may be configured to perform a processing-in-memory (PIM) operation. Please note that the internal processor being configured to perform a PIM operation corresponds to Applicant’s processor comprising a configured PIM circuitry) ;
external to the processor ([0042] the processing-in-memory 100 of one or more embodiments may calculate the physical address (e.g., a target physical address) of the memory 110 through the internal processor 120. Please note that since the internal processor 120 is distinct from the memory 110, this corresponds to the memory being external to the processor.);
to:
determine a memory address within the location in the memory ([0044] The processing-in-memory 100 may calculate the target physical address of the memory 110 to be accessed, through the internal processor 120 of the processing-in-memory 100. Please note that the processing-in-memory 100 calculating the target physical address of the memory 110 to be access through the internal processor 120 corresponds to Applicant’s determining at a PIM circuitry at a processor a memory address within the location in memory, as the processing-in-memory 100 corresponds to the PIM, the internal processor 120 corresponds to the processor, and the target physical address of the memory 110 corresponds to the memory address within the location in the memory.);
and issue instructions to store data in the memory address within the location in the memory to a PIM unit of the memory ([0043] The processing-in-memory 100 may generate a read or write instruction of the memory 110 for the PIM operation.; [0049] Thereafter, the internal processor 120 may perform (or execute) the instruction by accessing the target physical address. The processing-in-memory 100 may perform the read or write instruction by accessing the memory 110 at the target physical address. Please note that the PIM 100 generating a write instruction and performing the write instruction by accessing the memory 110 at the target physical address corresponds to Applicant’s issuing instructions to store data in the memory address within the location in the memory to a PIM unit of the memory, as the PIM 100 issues instructions to write to the target physical address, i.e., to store data in the memory address within the location in the memory.).
Yoon does not explicitly disclose comprising: a plurality of processor cores;
in response to receiving an instruction from a processor core of the plurality of processor cores to store data at a location in a memory
However, Nagarajan discloses comprising: a plurality of processor cores ([0043] a multi-core processing unit 104.);
in response to receiving an instruction from a processor core of the plurality of processor cores to store data at a location in a memory ([0009] each request of the multiple requests specifying an address for a memory location that stores the input.; [0016] any address location of a memory cell in any channel of a high-bandwidth memory system that communicates with a processor core; [0043] the host 102 can be a processing unit, such as a processor, multiple processors, or multiple processor cores. Please note that a request that specifies an address for a memory location storing the input corresponds to Applicant’s receiving an instruction from a processor core of the plurality of processor cores to store data at a location in memory, as a request corresponds to a received instruction that causes action to be taken in response. Furthermore, it is known in the art that a memory location that stores data requires a computer operation to have been conducted to store the data within that location. Therefore, it would have been obvious to a person of ordinary skill in the art prior to the filing date of the invention to have issued a request to store data in the specified address. Additionally, the host 102 of the computing system consisting of multiple cores, where each address location of a memory cell in any channel of the memory system that communicates with a processor core corresponds to Applicant’s receiving an instruction from a processor core of the plurality of processor cores, as the system would receive communications, i.e., instructions, from a processor core.),
Yoon and Nagarajan are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Yoon to incorporate the teachings of Nagarajan to modify the system with a PIM determining a memory address and issuing instructions to store data in the memory address to the PIM to do so in response to receiving instructions to store data at the location in memory and to use multiple processor cores, allowing for improved efficiency of operation of the system, as described in Nagarajan.
Regarding Claim 16, Yoon-Nagarajan as described in Claim 15, Nagarajan further discloses generate a memory allocation request based on the location in the memory indicated by the instruction ([0035] Relatedly, each channel controller may be allocated a portion of resources, such as a buffer, from a shared scratchpad memory space to perform certain operations using the retrieved data. Because the number of addresses (or requests) processed by each channel controller is different, the number of scratchpad memory/buffer locations used by each channel controller will also be quite different. Please note that allocating resources such as a buffer from a shared scratchpad memory at different locations to perform certain operations corresponds to generating a memory allocation request based on the location in the memory indicated by the instruction, as it allocates memory from a specific shared scratchpad memory at a certain location of the buffer corresponding to the location in the memory indicated by the instruction, and doing so in order to process a request corresponds to generating a request.); and send the memory allocation request to an operating system associated with the processor ([0102] The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes […] an operating system. Please note that performing the allocation of resources such as a buffer (as mentioned in the previous citation) in a system containing code creating an execution environment for the computer program such as code that constitutes an operating system corresponds to sending the memory allocation request to an operating system, as it is known in the art that an operating system is the intermediary system which controls such operations as the fulfillment of allocation requests and the management of buffers required for computer programs to function.).
Regarding Claim 17, Yoon-Nagarajan as described in Claim 15, Nagarajan further discloses determine the memory address within the location in the memory based on a memory mapping associated with the memory ([0033] each channel controller was mapped to a specific bank or channel in the large system memory, such that each channel controller could process only those addresses for memory locations to which the channel controller was mapped. Please note that each channel controller being mapped to a specific channel in the large system memory such that each channel controller can only process the addresses for memory locations to which it is mapped corresponds to Applicant’s being configured to determine the memory address within the location in the memory based on a memory mapping associated with the memory, as the specific mapping of the channel controller to a specific channel in the large system memory corresponds to a memory mapping associated with the memory, and only processing the addresses for memory locations to which it is mapped corresponds to determining the memory address within the location in the memory, as it uses the mapping to determine which addresses are available for the channel controller to process as part of its function.).
Regarding Claim 19, Yoon-Nagarajan as described in Claim 15, Nagarajan further discloses wherein the location in the memory indicates a channel of the memory ([0010] Each channel of the multiple channels in the memory can include a set of memory locations. Please note that each channel of the multiple channels in the memory including a set of memory locations corresponds to Applicant’s location in the memory indication a channel of the memory, as it would be obvious to utilize this mapping to determine a memory channel indicated by a particular memory location.).
Claims 4, 7, 11, 14, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20220075713 A1) in view of Nagarajan et al. (US 20210303978 A1) and further in view of Prodromou et al. (US 20180107598 A1), hereinafter referred to as Yoon, Nagarajan, and Prodromou, respectively.
Regarding Claim 4, Yoon-Nagarajan as described in Claim 3 does not explicitly disclose wherein the PIM circuitry is configured to hash the memory address based on the memory mapping associated with the memory.
However, Prodromou discloses wherein the PIM circuitry is configured to hash the memory address based on the memory mapping associated with the memory ([0044] Generally, the access record and the remapping record are data structures (lists, tables, hashes, etc.) that include information about page accesses and page locations, respectively. Please note that hashes of the remapping record including information about page locations corresponds to Applicant’s hashing memory address based on the memory mapping associated with the memory, as it uses the remapping record corresponding to the memory mapping associated with the memory to corroborate to a hash containing information about its location, i.e., its address. It is known in the art that a page is a block of memory; therefore, this citation pertains to memory. Furthermore, to have a hash data structure paired to information about page locations indicates that hashing was performed via computer circuitry.).
Yoon-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Yoon-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to hash the memory address based on the associate memory mapping of the memory, allowing for improved performance of the system, as described in Prodromou.
Regarding Claim 7, Yoon-Nagarajan as described in Claim 1 does not explicitly disclose wherein the memory comprises a stacked memory.
However, Prodromou discloses wherein the memory comprises a stacked memory ([0038] Channels 116-122 are each coupled between processor 102 and a corresponding stacked DRAM module. Please note that the memory being a stacked DRAM module corresponds to Applicant’s memory comprising a stacked memory.).
Yoon-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Yoon-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to have the memory comprise a stacked memory, allowing for improved performance of the system, as described in Prodromou.
Regarding Claim 11, Yoon-Nagarajan as described in Claim 10 does not explicitly disclose hash the memory address based on the memory mapping associated with the memory.
However, Prodromou discloses hash the memory address based on the memory mapping associated with the memory ([0044] Generally, the access record and the remapping record are data structures (lists, tables, hashes, etc.) that include information about page accesses and page locations, respectively. Please note that hashes of the remapping record including information about page locations corresponds to Applicant’s hashing memory address based on the memory mapping associated with the memory, as it uses the remapping record corresponding to the memory mapping associated with the memory to corroborate to a hash containing information about its location, i.e., its address. It is known in the art that a page is a block of memory; therefore, this citation pertains to memory. Furthermore, to have a hash data structure paired to information about page locations indicates that hashing was performed via computer circuitry.).
Yoon-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Yoon-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to hash the memory address based on the associate memory mapping of the memory, allowing for improved performance of the system, as described in Prodromou.
Regarding Claim 14, Yoon-Nagarajan as described in Claim 8 does not explicitly disclose wherein the memory comprises a stacked memory.
However, Prodromou discloses wherein the memory comprises a stacked memory ([0038] Channels 116-122 are each coupled between processor 102 and a corresponding stacked DRAM module. Please note that the memory being a stacked DRAM module corresponds to Applicant’s memory comprising a stacked memory.).
Yoon-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Yoon-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to have the memory comprise a stacked memory, allowing for improved performance of the system, as described in Prodromou.
Regarding Claim 18, Yoon-Nagarajan as described in Claim 17 does not explicitly disclose hash the memory address based on the memory mapping associated with the memory.
However, Prodromou discloses hash the memory address based on the memory mapping associated with the memory ([0044] Generally, the access record and the remapping record are data structures (lists, tables, hashes, etc.) that include information about page accesses and page locations, respectively. Please note that hashes of the remapping record including information about page locations corresponds to Applicant’s hashing memory address based on the memory mapping associated with the memory, as it uses the remapping record corresponding to the memory mapping associated with the memory to corroborate to a hash containing information about its location, i.e., its address. It is known in the art that a page is a block of memory; therefore, this citation pertains to memory. Furthermore, to have a hash data structure paired to information about page locations indicates that hashing was performed via computer circuitry.).
Yoon-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Yoon-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to hash the memory address based on the associate memory mapping of the memory, allowing for improved performance of the system, as described in Prodromou.
Regarding Claim 20, Yoon-Nagarajan as described in Claim 15 does not explicitly disclose wherein the memory comprises a stacked memory.
However, Prodromou discloses wherein the memory comprises a stacked memory ([0038] Channels 116-122 are each coupled between processor 102 and a corresponding stacked DRAM module. Please note that the memory being a stacked DRAM module corresponds to Applicant’s memory comprising a stacked memory.).
Yoon-Nagarajan and Prodromou are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Yoon-Nagarajan to incorporate the teachings of Prodromou to modify the system of Claim 1 to have the memory comprise a stacked memory, allowing for improved performance of the system, as described in Prodromou.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20220075713 A1) in view of Nagarajan et al. (US 20210303978 A1) and further in view of Baxter et al. (US 8479124 B1), hereinafter referred to as Yoon, Nagarajan, and Baxter, respectively.
Regarding Claim 6, Yoon-Nagarajan as described in Claim 1 does not explicitly disclose wherein the PIM circuitry is included in a direct memory access (DMA) circuitry of the processor.
However, Baxter discloses wherein the PIM circuitry is included in a direct memory access (DMA) circuitry of the processor (Col. 15, Lines 55-58- a Communication Direct Memory Access Controller (CDMAC) PIM that contains an embedded intelligent Direct Memory Access (DMA) engine optimized for communication style data access to memory. While most often DMA engines are controlled by processors […]. Please note that a CDMAC PIM containing an embedded DMA engine controlled by processors corresponds to Applicant’s PIM circuitry included in a DMA circuitry of the processor, as the PIM is included in circuitry performing DMA operations and is controlled by processors.).
Yoon-Nagarajan and Baxter are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Yoon-Nagarajan to incorporate the teachings of Baxter to modify the system of Claim 1 to include the PIM circuitry in a DMA circuitry of the processor, allowing for improved performance of the system via optimized data access to the memory, as described in Baxter.
Regarding Claim 13, Yoon-Nagarajan as described in Claim 8 does not explicitly disclose wherein the processor further includes a direct memory access (DMA) circuitry and wherein the PIM circuitry is included in the DMA circuitry.
However, Baxter discloses wherein the processor further includes a direct memory access (DMA) circuitry and wherein the PIM circuitry is included in the DMA circuitry (Col. 15, Lines 55-58- a Communication Direct Memory Access Controller (CDMAC) PIM that contains an embedded intelligent Direct Memory Access (DMA) engine optimized for communication style data access to memory. While most often DMA engines are controlled by processors […]. Please note that a CDMAC PIM containing an embedded DMA engine controlled by processors corresponds to Applicant’s processor including DMA circuitry and PIM circuitry included in a DMA circuitry of the processor, as the PIM is included in circuitry performing DMA operations and is controlled by processors.).
Yoon-Nagarajan and Baxter are both considered to be analogous to the claimed invention because they are in the same field of performing data operations within computer memory. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Yoon-Nagarajan to incorporate the teachings of Baxter to modify the system of Claim 1 to include the PIM circuitry in a DMA circuitry of the processor, allowing for improved performance of the system via optimized data access to the memory, as described in Baxter.
Response to Arguments
Applicant's arguments filed 12/15/2025 have been fully considered but they are not persuasive.
Applicant’s arguments are summarized as follows:
Neither Yoon nor Nagarajan, alone or in combination, teach the amended limitation of Claim 1 that PIM circuitry of a processor external to a memory determines a memory address within a location of a memory and then issuing instructions to a PIM unit of the memory to store data at that memory address. This is because:
Yoon discloses a processor internal to a processing-in-memory system including a memory and not a PIM circuitry of a processor external to a memory. Yoon makes clear that the internal processor of a PIM circuitry including a memory is distinct from “an external processor 320,” which does not perform determining addresses within locations of a memory or issuing instructions to the processing-in-memory system to store data at that memory address.
Nagarajan additionally does not remedy the deficiencies of Yoon, since it is silent to PIM circuitry of a processor external to a memory determining a memory address within a location of a memory and then issuing instructions to a PIM unit of the memory to store data at that memory address.
Therefore, neither of the references, alone or in combination, teach the claim limitations, and it overcomes the rejections under 35 U.S.C. 103.
Since Claims 8 and 15 have been similarly amended and contain similar limitations to Claim 1, which overcomes the rejections under 35 U.S.C. 103, they overcome the rejections under 35 U.S.C. 103 as well.
Since Claims 2, 3, 5, 9, 10, 12, 16, 17, and 19 depend from respective claims 1, 8, and 15, which overcome the rejections under 35 U.S.C. 103, they overcome the rejections under 35 U.S.C. 103 as well.
Since Claims 4, 7, 11, 14, 18, and 20 depend from respective claims 1, 8, and 15, which overcome the rejections under 35 U.S.C. 103, and the combination with Prodromou does not remedy their deficiencies, they overcome the rejections under 35 U.S.C. 103 as well.
Since Claims 6 and 13 depend from respective claims 1, 8, and 15, which overcome the rejections under 35 U.S.C. 103, and the combination with Baxter does not remedy their deficiencies, they overcome the rejections under 35 U.S.C. 103 as well.
Regarding A, the examiner respectfully disagrees.
Regarding i, as stated above, Yoon states that [0044] The processing-in-memory 100 may calculate the target physical address of the memory 110 to be accessed, through the internal processor 120 of the processing-in-memory 100. Since the internal processor 120 is distinct from the memory 110, this corresponds to the PIM circuitry of a processor external to the memory. The external processor 320 mentioned by Applicant was not cited as corresponding to this limitation. The claim states “a PIM circuitry of a processor external to the memory,” and the internal processor 120 of the PIM 100 fits this description based on the broadest reasonable interpretation of the claim language; the same cited section also recites calculating the target physical memory of the memory 110 to be accessed, i.e., determining addresses within locations of a memory. Furthermore, as described above, Yoon states [0049] Thereafter, the internal processor 120 may perform (or execute) the instruction by accessing the target physical address. The processing-in-memory 100 may perform the read or write instruction by accessing the memory 110 at the target physical address, corresponding to issuing instructions to the PIM system to store data at the memory address, as the PIM 100 issues instructions to write to the target physical address, i.e., to store data in the memory address within the location in the memory.
Regarding ii, as Yoon cites the aforementioned limitations, and Nagarajan is not cited as disclosing those limitations, Applicant’s argument is not persuasive.
Therefore, the recited features can be found in the cited combination of references, and independent Claim 1 remains rejected under 35 U.S.C. 103 for the reasons stated above, and the combinations cited would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the application. The rejections under 35 U.S.C. 103 are maintained.
Regarding B, the examiner respectfully disagrees. The Independent Claims 8 and 15 contain similar limitations to rejected Independent Claim 1 and do not add limitations that overcome the rejection; therefore, they likewise remain rejected, and the application is not in condition for allowance. The rejections under 35 U.S.C. 103 are maintained.
Regarding C, the examiner respectfully disagrees. The dependent claims 2, 3, 5, 9, 10, 12, 16, 17, and 19 depend on unpatentable claims and do not add limitations that overcome the rejection; therefore, they likewise remain rejected, and the application is not in condition for allowance. The rejections under 35 U.S.C. 103 are maintained.
Regarding D, the examiner respectfully disagrees. The dependent claims 4, 7, 11, 14, 18, and 20 depend on unpatentable claims and do not add limitations that overcome the rejection; therefore, they likewise remain rejected, and the application is not in condition for allowance. The rejections under 35 U.S.C. 103 are maintained.
Regarding E, the examiner respectfully disagrees. The dependent claims 6 and 13 depend on unpatentable claims and do not add limitations that overcome the rejection; therefore, they likewise remain rejected, and the application is not in condition for allowance. The rejections under 35 U.S.C. 103 are maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Luo (US 20200349217 A1) discloses a PIM architecture with a processor connected to a memory, with a PIM coupled to the memory array, an external processor performing look-up table and logic functionality separate from the internal PIM, DMA, and memory interfacing (see [0033, 0074, 110, 118, 145]).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARAZ T AKBARI whose telephone number is (571)272-4166. The examiner can normally be reached Monday-Thursday 9:30am-7:30pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FARAZ T AKBARI/Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
Prosecution Insights