Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/23/2026 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-6, 8, 12-13, 15 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Conrad et al. (US 2014/0189285).
Regarding claim 1, Conrad discloses a processor, comprising:
a plurality of cores; a first core of the plurality of cores comprising: a first translation lookaside buffer (TLB) to store address translations associated with page table walk operations [see paragraph 2; plurality of processors, each comprising a TLB for storing address translations], and
power management logic to cause the first core to enter into a first low power state in which the address translations in the first TLB are no longer valid [see paragraphs 5-6 & 19; processor is put into a low power state and TLB entries are flushed/invalidated], wherein prior to entering into the first low power state, the first core is to write an indication in a memory location that the first TLB no longer contains valid address translations [see paragraph 23; processor sets information in a storage circuit indicating that its associated TLB has been flushed/invalidated]; and
a second core of the plurality of cores to perform an operation requiring invalidation of one or more address translations previously stored in the first TLB [see paragraphs 19 & 25-26; second processor needs to invalidate regions of first processor TLB], the second core to determine whether to transmit a request to the first core to invalidate the one or more address translations based on the indication [see paragraphs 25-26; special storage circuitry is checked to see if invalidation requests should be sent to first processor TLB], wherein
the indication indicates the request not to be transmitted to the first core while the first core remains in the first low power state [see paragraphs 20-27; “A more efficient approach would have been for the OS 102 to recognize that the first processor had already flushed its associated TLB information and, in response, prevent issuance of the TLB_Shootdown interrupt to the first processor. This essentially lets the first processor "sleep longer" thereby making the overall system more power efficient.”, and “a thread executing on a processor requests that the processor enter a sleep state that requires the processor to flush its TLB information. In response, the processor flushes its TLB information 201 and sets information in a storage circuit (e.g., register or system memory) signifying that its associated TLB information has been flushed.”, and “By so-doing, those processors that should have their TLB information invalidated but have already flushed their TLB information can remain in a sleep state”. The information set in the storage circuitry signifies that the processor core has entered a low-power state and that the TLB information has been flushed. The storage system then identifies, based on this set information, which processors should be sent a TLB_Shootdown. The processor that entered the low power state would not be sent a shootdown request as the set information would indicating that the processor is in a flushed stated due to entering a low power state. The intention of setting this information is to have the processor remain in a low power sleep state].
Regarding claim 5, Conrad discloses the processor of claim 1 wherein the operation requiring invalidation of the one or more address translations previously stored in the first TLB comprises updates to one or more corresponding page table entries [see paragraph 19; wherein the operation requiring invalidation requires updates to the TLB translations (page table entries)].
Regarding claim 6, Conrad discloses the processor of claim 5 wherein the second core comprises a second TLB, the second core to flush one or more corresponding address translations stored in the second TLB [see paragraphs 20 & 25; second processor includes TLB translations that need to be invalidated and TLB shootdowns are issued].
Claims 8, 12-13, 15 and 19-20 recite similar claim limitations to those of claims 1 and 5-6 and are rejected using the same citations and interpretations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 7, 9-10, 14, 16 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Conrad in view of Wei et al. (US 2022/0083476).
Regarding claim 2, Conrad discloses the processor of claim 1, wherein the request comprises a first request, the second core to transmit a second request to a third core of the plurality of cores if a second TLB of the third core includes the one or more address translations [see paragraph 20; TLB shootdown sent to any additional processor in need of invalidation].
Conrad does not expressly disclose the second core is to wait for a completion acknowledgement from the third core before performing additional operations.
Wei discloses a computer system for issuing TLB shootdown requests. A shootdown completion acknowledgement is waited for before issuing additional requests [see paragraphs 28-29]
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilizing the waiting teachings of Wei in the system of Conrad.
The motivation for doing so would have been to reduce CAPU cache contention generated by TLB shootdowns [see Wei, paragraph 25].
Therefore, it would have been obvious to combine Wei with Conrad for the benefits listed above, to obtain the invention as specified in claims 2, 7, 9-10, 14, 16 and 21.
Regarding claim 7, the combination discloses the processor of claim 1 wherein the first request comprises a first inter-processor interrupt (IPI) and wherein the second request comprises a second IPI [see Wei, paragraphs 21-24; inter-processor interrupts (IPIs) used to request TLB shootdowns].
Claims 9, 14, 16 and 21 recite similar claim limitations to those of claims 2 and 7 and are rejected using the same citations and interpretations.
Regarding claim 10, the combination discloses the method of claim 9 [see rejection of claim 9 above], wherein if the first core writes the indication after the second core has transmitted the first request, then the second core is to determine not to wait for the first core to exit from the first low power state based on the indication [see Claim Interpretation section above; if the first core does not write the indication after the second core has transmitted the first request, the determination step of the second core is not performed, and nothing else happens].
Claims 4, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Conrad in view of Wang et al. (US 2015/0067259).
Regarding claim 4, Conrad discloses the processor of claim 1 as discussed above, including operating in low power states defined by the ACPI standard [see paragraph 5].
Conrad does not expressly disclose the first TLB is to be power-gated when the first core is in the first low power state.
Wang discloses a computer system in which a processor core may be operated in a low power C6 state in which high speed memories may be power-gated [see paragraph 33].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the power gating of Wang in the system of Conrad.
The motivation for doing so would have been to save even more power [see Wang, paragraph 33].
Therefore, it would have been obvious to combine Wang with Conrad for the benefits listed above, to obtain the invention as specified in claims 4, 11 and 18.
Claims 11 and 18 recite similar claim limitations to those of claim 4 and are rejected using the same citations and interpretations.
Allowable Subject Matter
Claims 3 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and all 101 rejections are properly overcome. The prior art of record fails to teach or render obvious the claim limitations regarding determining by the second core not to wait for the first core to exit from the first low power state based on the indication if the writing of the indication occurs after the second core has transmitted the first request.
Response to Arguments
Applicant’s arguments, filed 7/23/2026, with respect to 101 rejections have been fully considered and are persuasive. The rejection of claims 15-20 has been withdrawn.
Applicant's arguments filed 7/23/2026, regarding the new claim amendments, have been fully considered but they are not persuasive.
Applicant argues the prior art fails to teach the amendment of claim 1 of “wherein
the indication indicates the request not to be transmitted to the first core while the first core remains in the first low power state”. Conrad teaches a storage system in which information is set for a processor that has entered a low power state, and its TLB contents have been flushed. This information is then used for subsequent TLB_Shootdown requests in order to determine which processor should receive a shootdown request. The processor in the low state would not be sent the shootdown based on the set information. The intention of setting this information is to have the processor remain in a low power sleep state. See the rejection of claim 1 above for additional citations. Therefore, it is believed that Conrad discloses the new limitation of “wherein the indication indicates the request not to be transmitted to the first core while the first core remains in the first low power state”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT.
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/RYAN BERTRAM/Primary Examiner, Art Unit 2137
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