CTNF 18/122,612 CTNF 99193 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement Acknowledgment is made of the information disclosure statements filed on 16 March 2023, U.S. patents and Foreign Patents have been considered. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 9, 10, 13, 14, and 15 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Borer et al. (United States Patent Application Publication US7464362B1), hereinafter referenced as Borer . In regards to claim 9 (Borer) shows a computer system comprising a computer aided design tool, wherein the computer aided design tool is configured to: receive a portion of code for a circuit design for an integrated circuit selected by a user of the computer aided design tool; and Borer [Column 4 Lines 55-65] discloses: “The incremental compilation procedure may be performed after the set-up compilation described with reference to FIG. 1. At 401, one or more selected partitions may be selected to be synthesized. According to an embodiment of the present invention, the results from a set-up compilation may be evaluated to identify whether any of the partitions of the system satisfy system requirements such as timing or power requirements for example. The partitions that do not satisfy system requirements may be selected for synthesis in the incremental compilation (re-synthesis). Partitions with results from the set-up compilation that meet system requirements may be preserved or “locked down”.” synthesize the portion of the code selected by the user to logic resources of the integrated circuit to generate a synthesis output. Borer [Column 6 Line 50 through Column 7 Line 5] discloses: “The system designer 700 includes a synthesis unit 730. The synthesis unit 730 generates a logic design of a system to be implemented by a target device. The synthesis unit 730 takes a conceptual Hardware Description Language (HDL) design definition and generates an optimized logical representation of the system. The optimized logical representation of the system generated by the synthesis unit 730 may include a representation that has a minimized number of functional blocks and registers, such as logic gates and logic elements, required for the system. The synthesis unit 730 also determines how to implement the functional blocks and registers in the optimized logic representation utilizing specific resources on a target device, thus creating an optimized post-synthesis netlist for each of the partitions in the system. The post-synthesis netlists indicate how the resources on the target device can be utilized to implement the system. The post-synthesis netlists may, for example, include components such as LEs on the target device.” Borer [Column 4 Lines 5-10] discloses: “According to an embodiment of the present invention, a post-synthesis netlist is generated for each of the partitions in the system from mapping. This post-synthesis netlists may be an optimized technology-mapped netlist generated from the HDL.” In regards to claim 10 (Borer) shows the computer system of claim 9: provide the user with an option to select a processing type comprising at least one of: a library for the synthesis output, a gate for the synthesis output, a configurable circuit level for the synthesis output, or a logic circuit level for the synthesis output; Borer [Column 4 Lines 55-65] discloses: “The incremental compilation procedure may be performed after the set-up compilation described with reference to FIG. 1. At 401, one or more selected partitions may be selected to be synthesized. According to an embodiment of the present invention, the results from a set-up compilation may be evaluated to identify whether any of the partitions of the system satisfy system requirements such as timing or power requirements for example. The partitions that do not satisfy system requirements may be selected for synthesis in the incremental compilation (re-synthesis). Partitions with results from the set-up compilation that meet system requirements may be preserved or “locked down”.” In regards to claim 13 (Borer) shows the computer system of claim 9: provide the user with an interface allowing selection of a synthesis option comprising at least one of: adding pipelining to the circuit design, locking the synthesis output to selected logic blocks, or spreading the portion of the code across multiple groups of logic circuits in the integrated circuit; Borer [Column 6 Line 50 through Column 7 Line 5] discloses: “The system designer 700 includes a synthesis unit 730. The synthesis unit 730 generates a logic design of a system to be implemented by a target device. The synthesis unit 730 takes a conceptual Hardware Description Language (HDL) design definition and generates an optimized logical representation of the system. The optimized logical representation of the system generated by the synthesis unit 730 may include a representation that has a minimized number of functional blocks and registers, such as logic gates and logic elements, required for the system. The synthesis unit 730 also determines how to implement the functional blocks and registers in the optimized logic representation utilizing specific resources on a target device, thus creating an optimized post-synthesis netlist for each of the partitions in the system. The post-synthesis netlists indicate how the resources on the target device can be utilized to implement the system. The post-synthesis netlists may, for example, include components such as LEs on the target device.” In regards to claim 14 (Borer) shows the computer system of claim 9: generate an interface displaying a summary of the synthesis output comprising at least one of: a number of gates, a number of configurable circuits, a number of wires, or a list of routes; Borer [Column 4 Lines 5-10] discloses: “According to an embodiment of the present invention, a post-synthesis netlist is generated for each of the partitions in the system from mapping. This post-synthesis netlists may be an optimized technology-mapped netlist generated from the HDL.” In regards to claim 15 (Borer) shows the computer system of claim 9: receive a selection from the user for a synthesis option comprising at least one of: a type of logic circuitry, groupings of logic circuits, pipelining, locking the synthesis output, or a layout area in the integrated circuit; and synthesize the portion of the code based on the selection from the user; Borer [Column 4 Lines 55-65] discloses: “The incremental compilation procedure may be performed after the set-up compilation described with reference to FIG. 1. At 401, one or more selected partitions may be selected to be synthesized. According to an embodiment of the present invention, the results from a set-up compilation may be evaluated to identify whether any of the partitions of the system satisfy system requirements such as timing or power requirements for example. The partitions that do not satisfy system requirements may be selected for synthesis in the incremental compilation (re-synthesis). Partitions with results from the set-up compilation that meet system requirements may be preserved or “locked down”.” Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1 – 7, 12, 16, 18 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over US7464362B1 (Borer) in view of US6836877B1 (Dupenloup) . In regards to claim 1 (Borer) shows a method for processing code for a circuit design for an integrated circuit using a computer system, the method comprising: receiving at least a portion of the code for the circuit design for the integrated circuit, wherein the portion of the code comprises an error; Borer [Column 5 Lines 20-30] discloses: “According to an embodiment of the present invention, when partitioning a system, a partition with no logic may be specified. In this embodiment, the empty netlist would include an interface that defines its connectivity. The interface may include virtual pins.” Borer differs from the claimed invention in that it does not explicitly disclose making an assumption about the error using a computer aided design tool in the computer system; generating a revised circuit design for the integrated circuit with the error corrected based on the assumption and based on the code. Dupenloup teaches making an assumption about the error using a computer aided design tool in the computer system; and Dupenloup [Column 26 Lines 20-35] discloses: “Both Verilog-HDL and VHDL do not require that input pins of instantiated modules are connected to any net. As a result, some module input pins can be left unconnected when modules get instantiated. FIG. 35A shows an example of module 320 with unconnected input pins 321. Module “M1” 320 instantiated in module “TOP” 322 has its input pin “A” 321 left unconnected in the context of module “TOP” 322. Module M2 323 does not have any unconnected pins. Synopsys Design Compiler ties unconnected module input pins to logic zero (FIG. 35B). During synthesis, the logic is simplified based on this assumption.” Dupenloup teaches generating a revised circuit design for the integrated circuit with the error corrected based on the assumption and based on the code. Dupenloup [Column 26 Lines 35-36] discloses: “Referring to FIG. 35B, the unconnected pin 321 is now connected to ground, a logic zero, in this example.” The motivation to combine Borer and Dupenloup at the effective filing date of the invention is to improve EDA synthesis robustness by incorporating Dupenloup's assumption-based error handling into Borer's incremental FPGA compilation system, with a reasonable expectation of success as both references address synthesizing HDL code for digital circuit designs. In regards to claim 2 (Borer) does not show: the error comprises an error of omission in the code for the circuit design; Dupenloup teaches the error comprises an error of omission in the code for the circuit design; Dupenloup [Column 26 Lines 20-35] discloses: “Both Verilog-HDL and VHDL do not require that input pins of instantiated modules are connected to any net. As a result, some module input pins can be left unconnected when modules get instantiated. FIG. 35A shows an example of module 320 with unconnected input pins 321. Module “M1” 320 instantiated in module “TOP” 322 has its input pin “A” 321 left unconnected in the context of module “TOP” 322. Module M2 323 does not have any unconnected pins. Synopsys Design Compiler ties unconnected module input pins to logic zero (FIG. 35B). During synthesis, the logic is simplified based on this assumption.” The motivation to combine Borer and Dupenloup at the effective filing date of the invention is to improve EDA synthesis robustness by incorporating Dupenloup's assumption-based error handling into Borer's incremental FPGA compilation system, with a reasonable expectation of success as both references address synthesizing HDL code for digital circuit designs. In regards to claim 3 (Borer) shows the method of claim 1: the error comprises an error of commission in the code for the circuit design; Borer [Column 5 Lines 20-30] discloses: “According to an embodiment of the present invention, when partitioning a system, a partition with no logic may be specified. In this embodiment, the empty netlist would include an interface that defines its connectivity. The interface may include virtual pins.” In regards to claim 4 (Borer) shows the method of claim 1: receiving at least the portion of the code further comprises receiving only the portion selected by a user that comprises the error in a graphical user interface generated by the computer aided design tool; Borer [Column 4 Lines 55-65] discloses: “The incremental compilation procedure may be performed after the set-up compilation described with reference to FIG. 1. At 401, one or more selected partitions may be selected to be synthesized. According to an embodiment of the present invention, the results from a set-up compilation may be evaluated to identify whether any of the partitions of the system satisfy system requirements such as timing or power requirements for example. The partitions that do not satisfy system requirements may be selected for synthesis in the incremental compilation (re-synthesis). Partitions with results from the set-up compilation that meet system requirements may be preserved or “locked down”.” In regards to claim 5 (Borer) shows the method of claim 1: making the assumption further comprises making the assumption with regard to at least one of a timing constraint, a voltage constraint, a power constraint, a routing constraint, a wiring constraint, or a floorplan constraint for the integrated circuit; Borer [Column 5 Lines 20-30] discloses: “These virtual pins may be given a specific location on the target device and can accept timing constraints just as physical input output pins. By creating an empty partition, an incomplete design may be compiled and have its timing analyzed as if the design was fully specified.” In regards to claim 6 (Borer) does not show: generating the revised circuit design further comprises generating using first expressions in a first hardware description language and second expressions in a second hardware description language, and compiling the revised circuit design with the first and the second expressions; Dupenloup teaches generating the revised circuit design further comprises generating using first expressions in a first hardware description language and second expressions in a second hardware description language, and compiling the revised circuit design with the first and the second expressions; Dupenloup [Column 26 Lines 20-35] discloses: "Both Verilog-HDL and VHDL do not require that input pins of instantiated modules are connected to any net." The motivation to combine Borer and Dupenloup at the effective filing date of the invention is to improve EDA synthesis robustness by incorporating Dupenloup's assumption-based error handling into Borer's incremental FPGA compilation system, with a reasonable expectation of success as both references address synthesizing HDL code for digital circuit designs. In regards to claim 7 (Borer) shows the method of claim 1: generating a user interface that displays an output of revised code with the error corrected and constraints for the circuit design; Borer [Column 4 Lines 5-10] discloses: “According to an embodiment of the present invention, a post-synthesis netlist is generated for each of the partitions in the system from mapping. This post-synthesis netlists may be an optimized technology-mapped netlist generated from the HDL.” In regards to claim 12 (Borer) does not show: provide a suggestion to the user for a change to the code to correct an error in the code; Dupenloup teaches provide a suggestion to the user for a change to the code to correct an error in the code; Dupenloup [Column 26 Lines 33-35] discloses: “Only a warning is issued to tell users that unconnected input pins have been tied to zero.” The motivation to combine Borer and Dupenloup at the effective filing date of the invention is to improve EDA synthesis robustness by incorporating Dupenloup's assumption-based error handling into Borer's incremental FPGA compilation system, with a reasonable expectation of success as both references address synthesizing HDL code for digital circuit designs. In regards to claim 16 (Borer) shows a computer system comprising a computer aided design tool, wherein the computer aided design tool is configured to: receive at least a portion of code for a circuit design for an integrated circuit, wherein the portion of the code comprises a violation of a rule; Borer [Column 5 Lines 20-30] discloses: “According to an embodiment of the present invention, when partitioning a system, a partition with no logic may be specified. In this embodiment, the empty netlist would include an interface that defines its connectivity. The interface may include virtual pins.” Borer differs from the claimed invention in that it does not explicitly disclose making an assumption that eliminates the violation of the rule from the code; generating a revised circuit design for the integrated circuit based on the code with the violation of the rule eliminated using the assumption. Dupenloup teaches making an assumption that eliminates the violation of the rule from the code; and Dupenloup [Column 26 Lines 20-35] discloses: “Both Verilog-HDL and VHDL do not require that input pins of instantiated modules are connected to any net. As a result, some module input pins can be left unconnected when modules get instantiated. FIG. 35A shows an example of module 320 with unconnected input pins 321. Module “M1” 320 instantiated in module “TOP” 322 has its input pin “A” 321 left unconnected in the context of module “TOP” 322. Module M2 323 does not have any unconnected pins. Synopsys Design Compiler ties unconnected module input pins to logic zero (FIG. 35B). During synthesis, the logic is simplified based on this assumption.” Dupenloup teaches generate a revised circuit design for the integrated circuit based on the code with the violation of the rule eliminated using the assumption. Dupenloup [Column 26 Lines 35-36] discloses: “Referring to FIG. 35B, the unconnected pin 321 is now connected to ground, a logic zero, in this example.” The motivation to combine Borer and Dupenloup at the effective filing date of the invention is to improve EDA synthesis robustness by incorporating Dupenloup's assumption-based error handling into Borer's incremental FPGA compilation system, with a reasonable expectation of success as both references address synthesizing HDL code for digital circuit designs. In regards to claim 18 (Borer) shows the computer system of claim 16: access additional code from a library of components for circuit designs based on an expression in the code for the circuit design; and generate the revised circuit design with the additional code from the library; Borer [Column 6 Line 50 through Column 7 Line 5] discloses: “The system designer 700 includes a synthesis unit 730. The synthesis unit 730 generates a logic design of a system to be implemented by a target device. The synthesis unit 730 takes a conceptual Hardware Description Language (HDL) design definition and generates an optimized logical representation of the system. The optimized logical representation of the system generated by the synthesis unit 730 may include a representation that has a minimized number of functional blocks and registers, such as logic gates and logic elements, required for the system. The synthesis unit 730 also determines how to implement the functional blocks and registers in the optimized logic representation utilizing specific resources on a target device, thus creating an optimized post-synthesis netlist for each of the partitions in the system. The post-synthesis netlists indicate how the resources on the target device can be utilized to implement the system. The post-synthesis netlists may, for example, include components such as LEs on the target device.” In regards to claim 19 (Borer) shows the computer system of claim 16: eliminate the violation by adding at least one of: a voltage constraint, a timing constraint, a power constraint, a floorplan constraint, a routing constraint, a wiring constraint, an input port, an output port, a variable declaration, a signal width, a register, or an instantiation of a component to the revised circuit design; Borer [Column 5 Lines 20-30] discloses: “These virtual pins may be given a specific location on the target device and can accept timing constraints just as physical input output pins. By creating an empty partition, an incomplete design may be compiled and have its timing analyzed as if the design was fully specified.” Borer differs from the claimed invention in that it does not explicitly disclose identifying the violation of the rule as an error of omission. Dupenloup teaches identify the violation of the rule as an error of omission; and Dupenloup [Column 26 Lines 20-35] discloses: “Both Verilog-HDL and VHDL do not require that input pins of instantiated modules are connected to any net. As a result, some module input pins can be left unconnected when modules get instantiated. FIG. 35A shows an example of module 320 with unconnected input pins 321. Module “M1” 320 instantiated in module “TOP” 322 has its input pin “A” 321 left unconnected in the context of module “TOP” 322. Module M2 323 does not have any unconnected pins. Synopsys Design Compiler ties unconnected module input pins to logic zero (FIG. 35B). During synthesis, the logic is simplified based on this assumption.” The motivation to combine Borer and Dupenloup at the effective filing date of the invention is to improve EDA synthesis robustness by incorporating Dupenloup's assumption-based error handling into Borer's incremental FPGA compilation system, with a reasonable expectation of success as both references address synthesizing HDL code for digital circuit designs. In regards to claim 20 (Borer) does not show: generate the revised circuit design using a first subset of the code written in a first hardware description language and a second subset of the code written in a second hardware description language; and synthesize the revised circuit design with the first and the second subsets of the code; Dupenloup teaches generate the revised circuit design using a first subset of the code written in a first hardware description language and a second subset of the code written in a second hardware description language; and synthesize the revised circuit design with the first and the second subsets of the code; Dupenloup [Column 26 Lines 20-35] discloses: "Both Verilog-HDL and VHDL do not require that input pins of instantiated modules are connected to any net." The motivation to combine Borer and Dupenloup at the effective filing date of the invention is to improve EDA synthesis robustness by incorporating Dupenloup's assumption-based error handling into Borer's incremental FPGA compilation system, with a reasonable expectation of success as both references address synthesizing HDL code for digital circuit designs . 07-21-aia AIA Claim s 8, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US7464362B1 (Borer) in view of US6836877B1 (Dupenloup) as applied to claims 1, 9, and 16 above, respectively, and further in view of US8166436B1 (Baeckler) . In regards to claim 8 (Borer modified by Dupenloup) does not show: performing a limited synthesis of the revised circuit design in an early design exploration mode that skips a subset of operations performed during a full synthesis to generate a netlist comprising logic circuits for the revised circuit design; Baeckler teaches performing a limited synthesis of the revised circuit design in an early design exploration mode that skips a subset of operations performed during a full synthesis to generate a netlist comprising logic circuits for the revised circuit design; Baeckler [Column 3 Lines 20-35] discloses: “The present invention is related to a logic synthesis algorithm that improves the power, area and frequency predictability of a logic design early on during the High Level Synthesis, prior to Technology Mapping, without degrading the power, speed (Fmax) or area of the final design implementation. The tradeoff of the algorithm, however, is that the mapped logic cannot be subject to any further logic minimization steps. The High Level Synthesis algorithm involves a set of rules that identify situations where logic can be converted or mapped directly to technology or logic cells without the loss of power, speed (Fmax) or area of the final design implementation. The conversion makes the power, speed or area properties of the final implementation easier to accurately estimate. Accordingly, the set of rules specifies logic that is not likely to benefit from further minimization to improve predictability without a loss of quality.” The motivation to combine Borer and Dupenloup at the effective filing date of the invention is to improve EDA synthesis robustness by incorporating Dupenloup's assumption-based error handling into Borer's incremental FPGA compilation system, with a reasonable expectation of success as both references address synthesizing HDL code for digital circuit designs. The motivation to combine Borer, Dupenloup, and Baeckler at the effective filing date of the invention is to add early design exploration capability to the combined system, with a reasonable expectation of success as Borer and Baeckler are both Altera Corporation references directed to improvements of the same Quartus CAD tool platform for FPGA synthesis. In regards to claim 11 (Borer modified by Dupenloup) does not show: synthesize the portion of the code in an early design exploration mode that allows a violation of at least one synthesis rule; Baeckler teaches synthesize the portion of the code in an early design exploration mode that allows a violation of at least one synthesis rule; Baeckler [Column 3 Lines 20-35] discloses: “The present invention is related to a logic synthesis algorithm that improves the power, area and frequency predictability of a logic design early on during the High Level Synthesis, prior to Technology Mapping, without degrading the power, speed (Fmax) or area of the final design implementation. The tradeoff of the algorithm, however, is that the mapped logic cannot be subject to any further logic minimization steps. The High Level Synthesis algorithm involves a set of rules that identify situations where logic can be converted or mapped directly to technology or logic cells without the loss of power, speed (Fmax) or area of the final design implementation. The conversion makes the power, speed or area properties of the final implementation easier to accurately estimate. Accordingly, the set of rules specifies logic that is not likely to benefit from further minimization to improve predictability without a loss of quality.” The motivation to combine Borer and Dupenloup at the effective filing date of the invention is to improve EDA synthesis robustness by incorporating Dupenloup's assumption-based error handling into Borer's incremental FPGA compilation system, with a reasonable expectation of success as both references address synthesizing HDL code for digital circuit designs. The motivation to combine Borer, Dupenloup, and Baeckler at the effective filing date of the invention is to add early design exploration capability to the combined system, with a reasonable expectation of success as Borer and Baeckler are both Altera Corporation references directed to improvements of the same Quartus CAD tool platform for FPGA synthesis. In regards to claim 17 (Borer modified by Dupenloup) does not show: the rule is a synthesis rule, and the computer aided design tool is further configured to synthesize the revised circuit design with the violation of the synthesis rule eliminated during an early design exploration mode; Baeckler teaches the rule is a synthesis rule, and the computer aided design tool is further configured to synthesize the revised circuit design with the violation of the synthesis rule eliminated during an early design exploration mode; Baeckler [Column 3 Lines 20-35] discloses: “The present invention is related to a logic synthesis algorithm that improves the power, area and frequency predictability of a logic design early on during the High Level Synthesis, prior to Technology Mapping, without degrading the power, speed (Fmax) or area of the final design implementation. The tradeoff of the algorithm, however, is that the mapped logic cannot be subject to any further logic minimization steps. The High Level Synthesis algorithm involves a set of rules that identify situations where logic can be converted or mapped directly to technology or logic cells without the loss of power, speed (Fmax) or area of the final design implementation. The conversion makes the power, speed or area properties of the final implementation easier to accurately estimate. Accordingly, the set of rules specifies logic that is not likely to benefit from further minimization to improve predictability without a loss of quality.” The motivation to combine Borer and Dupenloup at the effective filing date of the invention is to improve EDA synthesis robustness by incorporating Dupenloup's assumption-based error handling into Borer's incremental FPGA compilation system, with a reasonable expectation of success as both references address synthesizing HDL code for digital circuit designs. The motivation to combine Borer, Dupenloup, and Baeckler at the effective filing date of the invention is to add early design exploration capability to the combined system, with a reasonable expectation of success as Borer and Baeckler are both Altera Corporation references directed to improvements of the same Quartus CAD tool platform for FPGA synthesis. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jack Chiang can be reached on (571)-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANWER AHMED ALAWDI/ Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851 Application/Control Number: 18/122,612 Page 2 Art Unit: 2851 Application/Control Number: 18/122,612 Page 3 Art Unit: 2851 Application/Control Number: 18/122,612 Page 4 Art Unit: 2851 Application/Control Number: 18/122,612 Page 5 Art Unit: 2851 Application/Control Number: 18/122,612 Page 6 Art Unit: 2851 Application/Control Number: 18/122,612 Page 7 Art Unit: 2851 Application/Control Number: 18/122,612 Page 8 Art Unit: 2851 Application/Control Number: 18/122,612 Page 9 Art Unit: 2851 Application/Control Number: 18/122,612 Page 10 Art Unit: 2851 Application/Control Number: 18/122,612 Page 11 Art Unit: 2851 Application/Control Number: 18/122,612 Page 12 Art Unit: 2851 Application/Control Number: 18/122,612 Page 13 Art Unit: 2851 Application/Control Number: 18/122,612 Page 14 Art Unit: 2851 Application/Control Number: 18/122,612 Page 15 Art Unit: 2851 Application/Control Number: 18/122,612 Page 16 Art Unit: 2851 Application/Control Number: 18/122,612 Page 17 Art Unit: 2851 Application/Control Number: 18/122,612 Page 18 Art Unit: 2851 Application/Control Number: 18/122,612 Page 19 Art Unit: 2851 Application/Control Number: 18/122,612 Page 20 Art Unit: 2851 Application/Control Number: 18/122,612 Page 21 Art Unit: 2851 Application/Control Number: 18/122,612 Page 22 Art Unit: 2851
Prosecution Insights