DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the [a first comparator circuit; a first offset voltage; a second comparator circuit; a second offset voltage; a second circuit; a third circuit; a third offset voltage] must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. As a consequence, the above deficiency is interpreted as follows for examination purposes: -
a first comparator circuit, is considered numeral 150 in fig. 1
a first offset voltage, is considered numeral 144 in fig. 1
a second comparator circuit, it is considered numeral 160 in fig. 1
a second offset voltage, is considered numeral 172 in fig. 1
a second circuit, is considered numeral 170 in fig. 2
a third circuit, is considered numeral 210 in fig. 2
a third offset voltage, is considered element PFM_EXT<9:0> in fig. 2
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In para [0023], line 4, the signal “PWMCOMP_OS” is not shown in any of the figures and therefore it is not clear how this signal is being applied.
In para [0025], line 2, the signal “PFMCOMP_OS” is not shown in any of the figures and therefore it is not clear how this signal is being applied.
Clarification and/or correction to the specification is required.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 1, line 2, recites “a first comparator having a first offset voltage” is not mentioned anywhere in the specification. It is not clear whether element 150 or element 160 in figure 1 is considered as the first comparator. Additionally, it is not clear whether element 144 or element Verr is the first offset voltage. The specification appears to be completely silent on this matter.
Claim 1, line 4, recites “a second comparator circuit having a second offset voltage” is not mentioned anywhere in the specification. It is not clear whether element 150 or element 160 in figure 1 is considered as the second comparator. Additionally, it is not clear whether element 172 or element Verr is the second offset voltage. The specification appears to be completely silent on this matter.
Claim 1, line 5, recites “a second circuit configured to generate a second code” is not mentioned anywhere in the specification. It is not clear whether element DAC 170 or element mux 220 or element 310 is considered as the second circuit. Additionally, the second code cannot be in element 310, because according to para. [0027], element 310 is the calculator circuit. The specification appears to be completely silent on this matter.
Claim 2, line 3, recites “the third circuit has a third offset voltage” is not to be found in the specification whatsoever.
The specification is objected for failing to provide adequate written description for the subject matter recited in claims 3-20. The Examiner has identified specific examples of unsupported limitations above; however, this list is not exhaustive. Applicant is directed to review all dependent claims (claims 2-20) to ensure each limitation is fully supported by the specification as originally filed. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-12, 14-18 and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Thomas et al (US Publication No. 20150137776).
Regarding claim 1, Thomas teaches an apparatus (i.e., apparatus 400; fig. 8)(Note: The entire action revolves around fig. 8, thus, the annotation "fig. 8" is infrequently mentioned for clarity purposes), comprising: a first comparator circuit (SKIP comparator 440) having a first offset voltage (Zerror); a first circuit (Sample and Hold Circuit 432) configured to generate a first code (SampleLX) based on the first offset voltage; a second comparator circuit (PWM comparator 414) having a second offset voltage (Vramp); and a second circuit (Error Estimation Circuit 438) configured to generate a second code (Verror_estimated) based on the second offset voltage and the first code (e.g., Duty=Vout/Vin=Verror/Vramp; para. [0047]), wherein the first offset voltage and the second offset voltage are partially (i.e., partially as only during one mode either PSK/DCM or FPWM/CCM) compensated (i.e., via compensation circuit 420) based on the second code (e.g., the logic block 442 also provides control signals to block integration of the Zerror signal and to reset the integrator 436, as well as controlling the dynamic response of the compensation circuit 420 during operation in PSK mode, as indicated in FIG. 8 by dashed lines; para. [0061]).
Regarding claim 2, Thomas teaches the apparatus of claim 1; further comprising a third circuit (Error Amplifier 418) coupled to the first comparator circuit, wherein: the third circuit has a third offset voltage (Vfb), and the first code is generated based on the third offset voltage (implicit, as seen in fig. 8).
Regarding claim 3, Thomas teaches the apparatus of claim 1; wherein the first circuit is configured to determine (i.e., may be determined analytically or empirically for any particular implementation; para. [0047]) the first offset voltage in response to the first comparator circuit switching a binary output (i.e., The resulting binary logical signal SCMP is output to the logic block 442 which makes the decision whether to initiate a pulse or to place the power stage 412 in a high impedance state; para. [0060]).
Regarding claim 5, Thomas teaches the apparatus of claim 1; further comprising: a calculator circuit (Zerror Integrator 434-Zerror Clamp 436) configured to: receive one or more sensed input and output voltages (i.e., Zerror Integrator 434 receives one respective input signal from block 442 and one respective output signal from block 432), and provide a third code (SampleLX_integrated) based on the sensed input and output voltages (e.g., The SampleLX voltage signal is integrated by the Zerror integrator 434. The integrated signal drifts down if the minimum of Il is positive, and drifts up if the minimum of Il is negative; para. [0052]).
Regarding claim 6, Thomas teaches the apparatus of claim 5; further comprising a fourth circuit (Summer 437) configured to generate a fifth code (Zerror) based on the second code and the third code (e.g., where k2 is the inverse of the gain of the feedback network 420, 422. Using these two properties, then, Verror=k1*k2*Vref. Or, setting k=k1*k2, Verror=k*Vref. Thus, setting Verror_estimated=k*Vref generates a voltage level which is an approximation to the Verror voltage; para. [0047]).
Regarding claim 7, Thomas teaches the apparatus of claim 6; wherein the fifth code is configured to further compensate (i.e., via compensation circuit 420) the first offset voltage and the second offset voltage (implicit, as seen in fig. 8).
Regarding claim 8, Thomas teaches the apparatus of claim 7; further comprising a plurality of components (i.e., plurality of components 422, 420), wherein: each of the plurality of components comprises respective offset voltages (i.e., respective offset voltages Vout, Vfb), and the fifth code is configured to further compensate (i.e., via compensation circuit 420) the respective offset voltages (implicit, as seen in fig. 8).
Regarding claim 9, Thomas teaches the apparatus (400); comprising: a first component (i.e., PSK 410) having a first offset voltage (Zerror); a first circuit (Sample and Hold Circuit 432) configured to: receive one or more sensed voltages (i.e., Zerror Integrator 434 receives one respective input signal from block 442 and one respective output signal from block 432), and provide a first code (SampleLX) based on the one or more sensed voltages; and a second circuit (Error Estimation Circuit 438) configured to: receive (i.e., receiving via Feedback circuit 422) the first code, receive a second code (Verror_estimated), wherein the second code is based on the first offset voltage (implicit, as seen in fig. 8), and generate a third code (SampleLX_integrated) configured to compensate (via compensation circuit 420) the first offset voltage (implicit, as seen in fig. 8).
Regarding claim 10, Thomas teaches the apparatus of claim 9; further comprising a comparator circuit (SKIP comparator 440), wherein the first offset voltage is associated with the comparator circuit (implicit, as seen in fig. 8).
Regarding claim 11, Thomas teaches the apparatus of claim 9; further comprising a component (i.e., PWM 408) comprising a second offset voltage (Vramp), wherein the third code is further configured to compensate (i.e., via compensation circuit 420) the second offset voltage (implicit, as seen in fig. 8).
Regarding claim 12, Thomas teaches the apparatus of claim 11; wherein the component comprises a ramp voltage generator circuit (i.e., Ramp Generator 416).
Regarding claim 14, Thomas teaches the apparatus of claim 9; further comprising a pulse width modulation (PWM) generator circuit (i.e., Logic 442) configured to operate based on a threshold current (i.e., the threshold current as the reversal/sampling-points of the current in the inductor L, Zerror increases if the minimum inductor current Il reverses, Zerror falls to Verror_estimated if the minimum inductor current Il is positive. This method is based on instantaneous measurement of the current in the inductor for determining the size of the pulse--an approach that will not scale up to high frequencies. This technique also compares the output voltage with different thresholds, which induces a larger output voltage ripple; para. [0042]), wherein the third code is configured to maintain an operating current (i.e., to sustain the operating current. The Zerror signal thus effectively detects reversal of the current in the inductor L, and a sustained negative current, without the need for high-speed circuits (e.g., using only a sample & hold 432 and an analog integrator 434); para. [0059]) for the PWM generator circuit above the threshold current (e.g., These characteristics are evident in the signal diagram of FIG. 9. The voltage LX is sampled at the minimum inductor current Il, which occurs as M1 switches off and M0 switches on (marked by vertical dashed lines on the Il plot); [0059]).
Regarding claim 15, Thomas teaches the apparatus of claim 9; wherein the one or more sensed voltages comprise an input voltage (Vin) from a power source (V).
Regarding claim 16, Thomas teaches the apparatus of claim 9; wherein the one or more sensed voltages comprise an output voltage (Vout) for a load (load/LC).
Regarding claim 17, Thomas teaches a circuit (400), comprising: a plurality of components (i.e., plurality of components 422, 420), wherein each of the plurality of components has a respective offset voltage (i.e., respective offset voltages Vout, Vfb); a first circuit (Sample and Hold Circuit 432) configured to generate a first code (SampleLX) corresponding to i) the respective offset voltage and ii) a first comparator offset voltage (SKIP comparator 440); a second circuit (Error Estimation Circuit 438) configured to generate a second code (Verror_estimated) based on the first code and a second comparator offset voltage (PWM comparator 414); a current offset calculator circuit (Zerror Integrator 434-Zerror Clamp 436) configured to: obtain an input voltage (Vin), provide a third code (SampleLX_integrated) based on the input voltage; and a third circuit (Error Amplifier 418) configured to generate a fourth code (SampleLX) based on the second code and the third code, wherein the fourth code is configured to compensate (i.e., via compensation circuit 420) the respective offset voltages, the first comparator offset voltage, and the second comparator offset voltage (implicit, as seen in fig. 8).
Regarding claim 18, Thomas teaches the circuit of claim 17; wherein the plurality of components comprises a ramp voltage generator circuit (Ramp Generator 416).
Regarding claim 20, Thomas teaches the circuit of claim 17; wherein the plurality of components comprises one or more comparator circuits (i.e., 440, 414).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al (US Publication No. 20150137776) in view of Kim et al (US Publication No. 20180191199).
Regarding claim 4, Thomas teaches the apparatus of claim 1.
Thomas does not teach further comprising a sensing resistor coupled to the first comparator circuit, wherein: the sensing resistor has a fourth offset voltage, and the first code is generated based on the fourth offset voltage.
Kim teaches in a similar field of endeavor in regulated power systems (i.e., apparatus 150; fig. 1E); wherein a sensing resistor (i.e., Rs/2, Rs/2, Rs) coupled to the first comparator circuit (i.e., AERR), wherein: the sensing resistor has a fourth offset voltage (i.e., VREF_DN), and the first code (i.e., Vcon) is generated based on the fourth offset voltage (implicit, as seen in fig. 1E).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the sensing resistor in Thomas, as taught by Kim, as it provides the advantage of optimizing the circuit design towards creating a predictable, tiny voltage drop that lets the system measure electrical current using Ohm’s law.
Regarding claim 13, is rejected for the same reasons that have already been stated/discussed above in rejected claim 4. {See rejection of claim 4}
Regarding claim 19, is rejected for the same reasons that have already been stated/discussed above in rejected claim 4. {See rejection of claim 4}
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270- 1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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