DETAILED ACTION
1. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-2 and 4-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suresh et al (hereafter Suresh)(US Pub. 20190205093).
5. As to claim 1, Suresh discloses circuitry (abstract) comprising:
polynomial multiplication circuitry to multiply a first input value to a second input value to compute a result (fig. 1 multiplier); and
modular reduction circuitry to perform modular reduction on multiplicative components of the result independently while other multiplicative expansion components of the result are still be calculated by the polynomial multiplication circuitry (fig. 1 reduction circuit 102).
6. As to claim 4, Suresh discloses wherein the circuitry is implemented in programmable logic and digital signal processing (DSP) blocks ([0020]) of a field programmable gate array (FPGA) ([0113]).
7. As to claim 5, Suresh discloses wherein the modular reduction circuitry performs modular reduction by multiplicative modular reduction to generate a modular reduction result that is a sum of multiple individual multiplicative reduction results ([0033]-[0034] summation).
8. As to claim 6 and 12, Suresh discloses wherein the modular reduction circuitry comprises a lookup table having entries that are used in the multiplicative modular reduction ([0066] lookup table).
9. As to claim 7, Suresh discloses a state register that stores an operation read address for the lookup table as an index in a current iteration ([0068] store address unit).
10. As to claim 8, Suresh discloses wherein the state register comprises an embedded memory of a digital signal processing (DSP) block of field programmable gate array (FPGA) circuitry.
11. As to claim 9, Suresh discloses clock circuitry to operate at an overclocked frequency ([0114]).
12. As to claims 10 and 13, Suresh discloses wherein the polynomial multiplication circuitry and the modular reduction circuitry are pipelined with multiple levels of pipelining using a plurality of intermediate registers, wherein different groups of the registers operate on different clocks ([0063]-[0064] and fig 10a-10b in order and execution pipeline).
13. As to claim 11, the claim is rejected for similar reasons as claim 1 above.
Claim Rejections - 35 USC § 103
14. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
15. Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suresh in view of Renes et al (hereafter Renes)(US Pub. 20210377026).
16. As to claim 2, Suresh does not disclose wherein the first input value and the second input value comprise a plurality of limbs, and wherein the polynomial multiplication circuitry multiplies the first input value to the second input value from a most significant limb to a least significant limb.
However, Renes discloses wherein the first input value and the second input value comprise a plurality of limbs, and wherein the polynomial multiplication circuitry multiplies the first input value to the second input value from a most significant limb to a least significant limb ([0008] limbs).
17. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Suresh by incorporating a plurality of limbs, and wherein the polynomial multiplication circuitry multiplies the first input value to the second input value from a most significant limb to a least significant limb, as in Renes, for the benefit of multiplying two polynomials for a cryptographic application efficiently using existing co-processors (Renes [0003]).
18. As to claim 3, the combination of Suresh and Renes discloses wherein the polynomial multiplication circuitry generates the first component of the product as a partial product corresponding to multiplying the most significant limb of the first input value to the most significant limb of the second input value (Renes [0007]-[0010]).
Allowable Subject Matter
19. Claims 14-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 14 recites at least performing error checking on the first output; determining that the first output is not erroneous; after a second of the plurality of iterations has completed, storing a second output of the second of the plurality of iterations; performing error checking on the second output; determining that the second output is erroneous; retrieving the first output; and ignoring operations performed between the first output and the second output and iteratively performing the multiplication and modular reduction operations at an iteration based on the first output.
The closest prior art of record US Pub. 20190205093 teaches iteratively performing multiplication and modular reduction operations using integrated circuitry. However, the prior art of record does not teach or suggest at least performing error checking on the first output; determining that the first output is not erroneous; after a second of the plurality of iterations has completed, storing a second output of the second of the plurality of iterations; performing error checking on the second output; determining that the second output is erroneous; retrieving the first output; and ignoring operations performed between the first output and the second output and iteratively performing the multiplication and modular reduction operations at an iteration based on the first output.
Conclusion
20. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. 20220188072 – related to data encryption, and more specifically to techniques for performing multiplication operations associated with homomorphic encryption.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151
