DETAILED ACTION
This action is in response to the amendments filed on 002/17/2026, in which claim 12 has been cancelled, claim 21 has been added, claims 1-11, 13-21 are presented for the examination.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/17/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21 discloses “the selector switch selects a given one of the plurality of BIOS chips and provides a bidirectional electrical path between the given BIOS chip and the one or more additional components”. Applicant has provided support as Fig. 3, 4 and page 10 and 11. None of the cited support by the applicant or the entire specification teaches bidirectional electrical path. For the examining purposes, examiner interprets as a path between given BIOS chip and one or more additional components.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-11, 13-21 have been considered but are not persuasive.
Huang does not suggest transmitting or receiving data on a path between the CPU 220, via the hardware control circuit 210 and the switch circuit 240, to the first/second BIOS programs 251/261.
Response:
Examiner respectfully disagrees. Specification of instant application on page 11, lines 20-29, teaches active and inactive paths. In the example, electrical path associated with metal bridge segment 420-4 may comprise transmit and power path (i e active path) whereas, receive path is not present or inactive. Therefore, it is clear that the there are multiple electrical paths associated with the metal bridge segments but only one path is active at any given time.
Furthermore, Claim 21 discloses “the selector switch selects a given one of the plurality of BIOS chips and provides a bidirectional electrical path between the given BIOS chip and the one or more additional components”. Applicant has provided support as Fig. 3, 4 and page 10 and 11. None of the cited support by the applicant or the entire specification teaches bidirectional electrical path.
Huang teaches (1) electrical path that goes from the CPU 220, via the hardware control circuit 210 and the switch circuit 240, to the first BIOS programs 251 and (2) electrical path that goes from the CPU 220, via the hardware control circuit 210 and the switch circuit 240, to the second BIOS programs 261. Both electrical paths are connected through the selector switch (i e switch circuit 240) as claimed. One of the path can be active and could be transmit path as claimed.
Therefore, examiner believes the combination of the cited prior-arts teaches each and every limitations of claims 1, 9, 15.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11, 13-21 are rejected under 35 U.S.C. 103 as being unpatentable over
Frank et al. (US 2007/0136570, referred herein after Frank) in view of Huang et al. (US 2009/0063834, referred herein after Huang).
As per claim 1, 9, 15, Frank discloses a method, comprising:
obtaining, by at least one processing device, in response to an application of power to the at least one processing device, one or more instructions provided by a selected basic input/output system (BIOS) chip of a plurality of BIOS chips of the at least one processing device ([0009], [0034], system power up, booting up normally),
executing, by the at least one processing device, at least one of the one or more instructions to initiate a boot process of the at least one processing device (Fig. 3, steps 312, 314, [0036]);
wherein the method is performed by the at least one processing device, wherein the at least one processing device comprises a processor coupled to a memory (Fig. 1, CPU and Flash memory, [0020]);
Frank does not specifically disclose the selected BIOS chip is selected using a selector switch that selectively provides at least one active electrical path between the selected BIOS chip and one or more additional components of the at least one processing device, wherein the at least one active electrical path through the selector switch comprises at least portions of one or more of a receive path for receiving data and a transmit path for transmitting data between the selected BIOS chip and the one or more additional components of at least one processing device; wherein the selector switch is controlled, at least in part responsive to user input, to select one of the plurality of BIOS chip;
wherein the selector switch is controlled, at least in part responsive to user input, to select one of the plurality of BIOS chip;
However, Huang discloses the selected BIOS chip is selected using a selector switch that selectively provides at least one active electrical path between the selected BIOS chip and one or more additional components of the at least one processing device, wherein the at least one active electrical path through the selector switch comprises at least portions of one or more of a receive path for receiving data and a transmit path for transmitting data between the selected BIOS chip and the one or more additional components of at least one processing device; wherein the selector switch is controlled, at least in part responsive to user input, to select one of the plurality of BIOS chip (Fig. 2, [0015], [0016], BIOS (e g either BIOS 250, 260) is selected using a selector switch 240, which also provides an electrical path between selected BIOS and at least one processing unit (CPU 220) via hardware control circuit. Electrical path that connects CPU to BIOS can transmits/receives the data, ”the hardware control circuit 210 sends out a switch signal to the switch circuit 240 to restart the system 200, wherein the BIOS_READY signal, which is initiated as disabled when the system starts up, can be any signals transmitted from one of the chips controlled by the central processing unit 220, via chip pins, i.e. the General Purpose I/O (GPIO) pins, to the hardware control circuit 210. The above-mentioned first BIOS program 251 and second BIOS program 261 are programs comprising a system initiation program, which can be the same program codes or include different program codes for different intentions such as mutual BIOS backups, mutual BIOS retrievals, and virus protections, etc.”, Specification page 11, lines 20-29 electrical paths receive or transmit, one of them is active at any given time)); wherein the selector switch is controlled, at least in part responsive to user input, to select one of the plurality of BIOS chip (instant application describes in [0025], “It is to be appreciated that the term “user” in this context and elsewhere herein is intended to be broadly construed so as to encompass, for example, human, hardware, software or firmware entities (including services), as well as various combinations of such entities.”. Huang teaches in [0015], [0016] CPU controls BIOS-READY signal via chip pins to select one of the plurality of BIOS chips, CPU is considered as hardware which selects one of BIOS chips);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Huang’s auto switching BIOS system with two or more BIOS into Frank’s computing device limiting mechanism because one of the ordinary skill in the art would have been motivated in decreasing the manufacturing cost and improving the efficiency of the system operation.
As per claim 2, 10, 16, Frank discloses the method of claim 1, wherein the selector switch selects only one of the plurality of BIOS chips at a given time (Fig. 2, BIOS A or BIOS B is selected as claimed).
As per claim 3, 11, 17, Frank discloses the method of claim 1, wherein the selector switch comprises at least portions of each of a plurality of electrical paths between the selected BIOS chip and the one or more additional components (Fig. 2, [0026], flash chip 244 with two distinct storage sections, with the code of a conventional BIOS flashed into one section and the HLM BIOS code flashed into the other. Note that the BIOS selector 142 (or embedded controller 140) may also access the flash 244 for storage, e.g., to maintain which boot path to execute following a power-down state).
As per claim 4, Huang discloses the method of claim 3, wherein the plurality of electrical paths comprises at least portions of a power path (Fig. 2, [0015]-[0018]).
As per claim 5, Frank discloses the method of claim 1, wherein the selector switch provides power to the selected BIOS chip (Fig. 2, [0023], [0026]-[0027], [0034]).
As per claim 6, 13, 18, Frank discloses the method of claim 1, wherein the selector switch is manually controlled by a user to select one of the plurality of BIOS chips ([0036]-[0038], “step 318 representing handling the problem detection otherwise, e.g., via a warning prompt by which the user may be able to switch the boot path data back to normal for the next boot.”).
As per claim 7, 14, 19, Frank discloses the method of claim 1, wherein the plurality of BIOS chips comprises at least a primary BIOS chip (Fig. 2, BIOS A) and at least one secondary BIOS chip (Fig. 2, BIOS B), and wherein, in response to one or more of a failure of the selected BIOS chip, a degradation of the selected BIOS chip and a detection of unauthorized software on the at least one processing device (Fig. 3, step 310, problem detected, [0035]-[0036]), the selector switch is controlled to select one of the at least one secondary BIOS chip (Fig. 3, step 312, [0036], If step 310 detects a problem, the metering mechanism 140 sets the boot path data at step 312 so that the device will boot from the HLM BIOS on the next boot).
As per claim 8, 20, Frank discloses the method of claim 7, wherein the selected at least one secondary BIOS chip loads an operating system associated with the at least one processing device following the one or more of the failure, the degradation and the detection of the unauthorized software (Fig. 3, step 312, [0036], If step 310 detects a problem, the metering mechanism 140 sets the boot path data at step 312 so that the device will boot from the HLM BIOS on the next boot).
As per claim 21, Huang discloses the method of claim 1, wherein, in a first configuration, the selector switch (Fig. 2, switch 240) selects a given one of the plurality of BIOS chips (Fig. 2, BIOS 251) and provides a bidirectional electrical path between the given BIOS chip and the one or more additional components (Fig. 2, CPU 220 is considered as one or more additional components) and wherein, in a different, second configuration, the selector switch (Fig. 2, switch 240) selects a different one of the plurality of BIOS chips (Fig. 2, BIOS 261) and provides a bidirectional electrical path between the different BIOS chip and the one or more additional components (Fig. 2, CPU 220 is considered as one or more additional components)
Conclusion
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/KAMINI B PATEL/Primary Examiner, Art Unit 2114