DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 have been presented and pending in the application. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 1; In line 5, it is unclear as to whether the “sideband bus control circuitry” functionally and/or structurally interconnected to perform any function in the context of the claimed invention (i.e., the sideband bus control circuitry is not utilized, nor provide any function in the claimed invention). In line 8, the phrase “reset components in the memory module” & “asserting of the reset signal” lack proper, clear & functional antecedent basis. In line 9, the phrase “reset signal” lacks proper and clear antecedent basis. In claims 12 & 17, the unclarities of the claim 1 are similarly applied , respectively . The examiner notes that the claimed “memory” appears to nominally recite an apparatus/method without utilizing, performing or providing any memory module/device functions/operations (i.e., no memory accessing operations performed by the claimed invention); the claimed invention appears to be directed to a system/method for providing “reset” operation . Therefore, when the examiner applies Broadest Reasonable Interpretation, the claimed invention is directed to resetting device/method with or without memory function , as claimed. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 12-13 & 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Bassman et al. (US 2020/0133355) . The examiner relies on the entire teachings of the Bassman reference for this rejection; the examiner kindly advises the applicant to carefully consider the entire teachings of the Bassman reference to better understand the examiner’s position & the interpretation applied to the claimed invention. The Bassman reference teaches, when the examiner applies Broadest Reasonable Interpretation to the claimed invention, functionally equivalent limitations of the claimed invention as follows: CLAIMS 1-2, 12-13 & 17-18 Bassman REF TEACHINGS 1.A memory module comprising: a plurality of memory devices ; and FIG 2 with accompanying description, a IHS (200) includes STORAGE CONTROLLER (230) with STORAGE DRIVES (240a..240n) , see also MEMORY MODULE (210) a memory module management controller coupled to the plurality of memory devices, the memory module management controller comprising a reset controller and sideband bus control circuitry, FIG 2 with accompanying description, STORAGE CONTROLLER (230) having sideband bus monitor 230a coupled to STORAGE DRIVES (240a..240n) ; the 203 & 230a teaches the memory module management controller comprised of reset controller and sideband bus the reset controller to monitor a reset signal received FIG 2 with accompanying description, par 57, “resetting the state of the I2C controller utilized by the managed device…signaling the resetting of the bus to the remote access controller”; par 62 , “ the sideband bus monitor will reset the sideband bus based on the sideband bus timer configured by the remote access controller ” ; see also par 48, “restarting the managed device in order to reinitialize the sideband bus is possible…” from a memory controller in a host system that is communicatively coupled to the memory module and FIG 2 with accompanying description, the REMOTE ACCESS CONTROLLER (255) communicatively coupled to the STORAGE CONTROLLER (230) to drive an output reset signal to reset components in the memory module in response to assertion of the reset signal. FIG 2 with accompanying description, par 57, “sideband bus monitor resets the sideband bus…without affecting the operations of the HIS…” 2. The memory module of Claim 1, wherein a memory module management controller to drive the output reset signal to a component for a duration of time for the component, the duration of time programmed in a control register in the memory module management controller. FIG 2 with accompanying description, par 57, “resetting the state of the I 2 C controller utilized by the managed device…signaling the resetting of the bus to the remote access controller”; par 62, “the sideband bus monitor will reset the sideband bus based on the sideband bus timer configured by the remote access controller”; see also par 48, “restarting the managed device in order to reinitialize the sideband bus is possible…” 12. A system comprising: a memory controller; and a memory module comprising: a plurality of memory devices; and a memory module management controller coupled to the plurality of memory devices, the memory module management controller comprising a reset controller and sideband bus control circuitry, the reset controller to monitor a reset signal received from the memory controller that is communicatively coupled to the memory module and to drive an output reset signal to reset components in the memory module in response to assertion of the reset signal. The teachings of the claim 1 are similarly applied The teachings of the claim 1 are similarly applied 13. The system of Claim 12, wherein a memory module management controller to drive the output reset signal to a component for a duration of time for the component, the duration of time programmed in a control register in the memory module management controller. The teachings of the claim 2 are similarly applied The teachings of the claim 2 are similarly applied 17. A method comprising: monitoring, by a reset controller in memory module management controller in a memory module, a reset signal received from a memory controller in a host system that is communicatively coupled to the memory module, the memory module management controller coupled to a plurality of memory devices, the memory module management controller comprising sideband bus control circuitry; and driving, by the reset controller, an output reset signal to reset components in the memory module in response to assertion of the reset signal. The teachings of the claim 1 are similarly applied The teachings of the claim 1 are similarly applied 18. The method of Claim 17, wherein the reset controller to drive the output reset signal to a component for a duration of time for the component, the duration of time programmed in a control register in the memory module management controller. The teachings of the claim 2 are similarly applied Examiner notes that the Bassman reference does not expressly or identically disclose or use the claimed “memory” (i.e., the Bassman reference teachings of figures 1-2 includes/discloses a similar memory or storage devices); however, such difference in usage of “memory” terminology is a nominal difference that are not expressly utilized in the claimed invention. In addition, the Basman reference teaches the functional equivalence teachings of the claimed invention (i.e., reset function/method/apparatus). Therefore, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to come up with the claimed invention from the functionally equivalent teachings of the Bassman reference for the detailed teachings and reasons discussed above. Claim s 1-20 a re rejected under 35 U.S.C. 103 as being unpatentable over Mishra et al. (US 2018/0173667 A1) in view of LE et al. (US 2020/0226045 A1) . The above discussed teachings of the Bassman reference provide well-known teachings in the art of resetting function/system; therefore, the examiner takes official notice that the claimed features/recitations are well-known in the art. The examiner relies on the entire teachings of the Mishra & LE reference s for this rejection; the examiner kindly advises the applicant to carefully consider the entire teachings of the Bassman reference to better understand the examiner’s position & the interpretation applied to the claimed invention. The Mishra & LE reference s teach, when the examiner applies Broadest Reasonable Interpretation to the claimed invention, functionally equivalent limitations of the claimed invention as follows: CLAIMS 1-20 Mishra REF. TEACHINGS LE REF. TEACH I N G S 1.A memory module comprising: a plurality of memory devices ; and FIG 2 with accompanying description, a device 202 includes storage 224 & controller logic 212; examiner any slave devices can be memory devices Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET a memory module management controller coupled to the plurality of memory devices, the memory module management controller comprising a reset controller and sideband bus control circuitry, FIG 2 & 16 with accompanying description, SoC Device 1600 having a reset controller 1604 performs the reset and sideband control circuitry function of the claimed invention Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET from a memory controller in a host system that is communicatively coupled to the memory module and FIG 2 , 15 & 16 with accompanying description, SoC Device 1600 having a reset controller 1604 performs the reset and sideband control circuitry function of the claimed invention ; the examiner notes that the Host Device 1500 teaches the host memory controller Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET to drive an output reset signal to reset components in the memory module in response to assertion of the reset signal. FIG 2 , 15 & 16 with accompanying description, par 144, “device 1600 may include a reset controller 1604 configured to decode signals transmitted on serial bus and to drive reset signals 1626, 1628, 1630 and 1632…” Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET 2. The memory module of Claim 1, wherein a memory module management controller to drive the output reset signal to a component for a duration of time for the component, the duration of time programmed in a control register in the memory module management controller. Obvious from the teachings of FIG 2, 15 & 16 with accompanying description, par 144, “device 1600 may include a reset controller 1604 configured to decode signals transmitted on serial bus and to drive reset signals 1626, 1628, 1630 and 1632…” & par 147, “Output gating logic 1612 may be provided to enable selective generation of the reset signals 1626, 1628, 1630 and 1632…can operate autonomously and can force hard other components 1602, 1606, 1608 within the Soc…outside the reset controller 1604 may respond to select signals, control signals, reset signals and/or multi-bit codes that can be used to generate specific combinations of reset signals” ; the examiner also notes that this is also well-known in the art Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET 3. The memory module of Claim 1, wherein a short pulse on the reset signal to indicate a request to reset the sideband bus control circuitry. Obvious from the teachings of FIG 16 -17 with accompanying description , par 155, “device reset pattern 1700 that may be used to target device or function 1602, 1606, 1608 and/or a group of devices or functions”; the examiner notes that reset pattern teaches the functionally equivalent limitation of the short/long pulse ; the examiner also notes that this is also well-known in the art Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET 4. The memory module of Claim 1, wherein a long pulse on the reset signal to indicate a request to reset components in the memory module management controller and other devices on the memory module. Obvious from the teachings of FIG 16-17 with accompanying description, par 155 “device reset pattern 1700 that may be used to target device or function 1602, 1606, 1608 and/or a group of devices or functions”; the examiner notes that reset pattern teaches the functionally equivalent limitation of the short/long pulse ; the examiner also notes that this is also well-known in the art Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET 5. The memory module of Claim 4, wherein the reset controller to assert a memory reset signal to reset one or more memory devices on the memory module. Obvious from the teachings of FIG 2, 1 5-17 with accompanying description, par 144, “device 1600 may include a reset controller 1604 configured to decode signals transmitted on serial bus and to drive reset signals 1626, 1628, 1630 and 1632…” & par 147, “Output gating logic 1612 may be provided to enable selective generation of the reset signals 1626, 1628, 1630 and 1632…can operate autonomously and can force hard other components 1602, 1606, 1608 within the Soc…outside the reset controller 1604 may respond to select signals, control signals, reset signals and/or multi-bit codes that can be used to generate specific combinations of reset signals” ; the examiner also notes that this is also well-known in the art Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET 6. The memory module of Claim 4, wherein the reset controller to assert a data buffer reset to reset one or more buffers on the memory module. Obvious from the teachings of FIG 2, 15-17 with accompanying description, par 144, “device 1600 may include a reset controller 1604 configured to decode signals transmitted on serial bus and to drive reset signals 1626, 1628, 1630 and 1632…” & par 147, “Output gating logic 1612 may be provided to enable selective generation of the reset signals 1626, 1628, 1630 and 1632…can operate autonomously and can force hard other components 1602, 1606, 1608 within the Soc…outside the reset controller 1604 may respond to select signals, control signals, reset signals and/or multi-bit codes that can be used to generate specific combinations of reset signals” ; the examiner also notes that this is also well-known in the art Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET 7. The memory module of Claim 1, wherein the reset controller to reset components in the memory module in response to a command received from the sideband bus control circuitry. Obvious from the teachings of FIG 16-17 with accompanying description, par 155, “device reset pattern 1700 that may be used to target device or function 1602, 1606, 1608 and/or a group of devices or functions”; the examiner notes that reset pattern teaches the functionally equivalent limitation of the short/long pulse ; the examiner also notes that this is also well-known in the art Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET 8. The memory module of Claim 1, wherein the reset controller to interrupt power for a duration of time to a component to reset the component in the memory module. Obvious from the teachings of FIG 16-17 with accompanying description, par 1 46 , “ reset controller 1604 to assert a reset signal 1632 directed to the power-on logic, which causes the power-on logic to drive a global reset signal 1624 that resets all device and functions ” ; the examiner notes that the reset the power-on logic teaches interrupt power for a duration of time ; the examiner also notes that this is also well-known in the art Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET 9. The memory module of Claim 8, wherein the duration of time is programmed in a control register. Obvious from the teachings of FIG 16-17 with accompanying description, par 1 50 , “ different values in RGR and RGR can ensure that one or more of the reset signals 1626, 1628, 1630 and 1632 are generated when a device reset pattern or other singling is detected on the serial bus…may be suppressed by writing the device address of the peripheral 1600” ; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time ; the examiner also notes that this is also well-known in the art Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET 10. The memory module of Claim 1, wherein the memory module is a Dual Inline Memory Module (DIMM). Figs 2-3 with accompanying description ; par 11, “DIMMs fails, it is often…electrically isolated” teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET , se also figure 5A-5C with accompanying description 11. The memory module of Claim 1, wherein the sideband bus control circuitry to control an I3C serial bus. Inherent features of I2C and I3C of figures 15-16 12. A system comprising: a memory controller; and a memory module comprising: a plurality of memory devices; and a memory module management controller coupled to the plurality of memory devices, the memory module management controller comprising a reset controller and sideband bus control circuitry, the reset controller to monitor a reset signal received from the memory controller that is communicatively coupled to the memory module and to drive an output reset signal to reset components in the memory module in response to assertion of the reset signal. The teachings of the claim 1 are similarly applied The teachings of the claim 1 are similarly applied 13. The system of Claim 12, wherein a memory module management controller to drive the output reset signal to a component for a duration of time for the component, the duration of time programmed in a control register in the memory module management controller. The teachings of the claim 2 are similarly applied The teachings of the claim 2 are similarly applied 14. The system of Claim 12, wherein a short duration pulse on the reset signal to indicate a request to reset the sideband bus control circuitry. The teachings of the claim 3 are similarly applied The teachings of the claim 3 are similarly applied 15. The system of Claim 12, wherein a long duration pulse on the reset signal to indicate a request to reset components in the memory module management controller and other devices on the memory module. The teachings of the claim 4 are similarly applied The teachings of the claim 4 are similarly applied 16. The system of claim 12, further comprising one or more of: at least one processor communicatively coupled to the memory controller; a display communicatively coupled to at least one processor; or a power supply to provide power to the system. Obvious features of figure 1 and/or well-known & commonly practiced features in the art Obvious features of figure 2 and/or well-known & commonly practiced features in the art 17. A method comprising: monitoring, by a reset controller in memory module management controller in a memory module, a reset signal received from a memory controller in a host system that is communicatively coupled to the memory module, the memory module management controller coupled to a plurality of memory devices, the memory module management controller comprising sideband bus control circuitry; and driving, by the reset controller, an output reset signal to reset components in the memory module in response to assertion of the reset signal. The teachings of the claim 1 are similarly applied The teachings of the claim 1 are similarly applied 18. The method of Claim 17, wherein the reset controller to drive the output reset signal to a component for a duration of time for the component, the duration of time programmed in a control register in the memory module management controller. The teachings of the claim 2 are similarly applied The teachings of the claim 2 are similarly applied 19. The method of Claim 17, wherein a short duration pulse on the reset signal to indicate a request to reset the sideband bus control circuitry. The teachings of the claim 3 are similarly applied The teachings of the claim 3 are similarly applied 20. The method of Claim 17, wherein a long duration pulse on the reset signal to indicate a request to reset components in the memory module management controller and other devices on the memory module. The teachings of the claim 4 are similarly applied The teachings of the claim 4 are similarly applied Examiner notes that the Mishra reference does not expressly or identically disclose or use the claimed “memory” (i.e., figures 1-2 of the Mishra reference teachings includes/discloses similar memory or storage devices); however, such difference in usage of the “memory” terminology is a nominal difference that are not expressly utilized in the claimed invention , and also the claimed memory terminology is well-known & commonly practiced in the art of memory system as evidenced by the LE reference teachings (I.e., the well-known system from the same applicant) . In addition, the LE reference further teaches the motivation of using SIDEBAND BUS (e.g., typically & commonly known in the art to use I2C/I3C protocol) & RESET signals ; moreover, the Mishra reference teaches the functional equivalence teachings of the claimed invention (i.e., reset function/method/apparatus). Therefore, since both of the teachings of the Mishra & LE references are directed to the same field of resetting functions/operations in a device or system with the memory , it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to add / combine the functionally equivalent rese t teachings of the Mishra reference to /with the memory device teachings with the reset motivation of the LE reference for establishing an efficient resetting function in a memory system (i.e., resetting function/operations are one of necessary operations for proper operations of memory systems) for the detailed teachings and reasons discussed above. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT CHRISTOPHER B SHIN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-4159 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 8:00-4:00 PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT IDRISS N ALROBAYE can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-270-1023 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER B SHIN/ Primary Examiner, Art Unit 2181