CTFR 18/123,218 CTFR 67688 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. The Amendment received April 27, 2026 has been entered and carefully considered. Claims 1-3, 5, 10-11 & 21-32 have been presented and pending in the application. Official Notice Teachings The examiner finds the claimed resetting function/operations in memory/storage devices were well-known and commonly practiced in the art. Following prior art of record: Seo et al. (US 2021/0334225 A1); Keshava et al. (US 2016/0358669 A1) & KESHAVA (US 2017/0038974 A1) teach well-known and commonly practiced functions/operations of the claimed resetting functions/operations, including the features of dependent claims, being part of well-known memory system operations. The examiner advises the applicant to carefully consider the entire teachings of the above discussed Seo, Keshava & KESHAVA references that are directed to the same field of endeavor and the same applicant which inherently teaches motivations to combine or add the well-known respective teachings. In addition, the above teachings of the prior art of record supports the following examiner’s statement/reasons of well-known teachings discussed in the following art rejections. Response to Arguments 07-37 AIA Applicant's arguments filed 4/27/2026 have been fully considered but they are not persuasive. Importantly, the applicant is COMPLETELY SILENT (i.e., no arguments have been presented) with respect to the art rejection or in response to the last office action/rejection of the claims 1-20 over the Mishra et al. (US 2018/0173667 A1) in view of LE et al. (US 2020/0226045 A1). Therefore, the examiner believes that the prior art rejection was and is proper & the prior 103 art rejection was agreed by the applicant (i.e., no disagreements/arguments have been issued/provided by the applicant). For the above reasons, the examiner firmly believes that, if the applicant inadvertently failed to disagree with the art rejection, the applicant’s response is incomplete; therefore, the examiner maintains substantially the same art rejections of the last office action of the claims 1-20 that are now claimed as claims 1-3, 5, 10-11, 21-32 (i.e., the present claims 1-21-27, 2-22-28, 3-23-27, 5-24-30, 10-25-31 & 11-26-32 are substantially/functionally identical to each other (i.e., the dash lined claims); furthermore, the present claim 1 is substantially identical to the previous claim 1; the present claim 2 is substantially identical to the previous claim 2; the present claim 3 is substantially identical to the previous claims 3 & 4; the present claim 5 is substantially identical to the previous claims 5 & 6; the present claim 10 is substantially identical to the previous claims 10 & 11; and the present claim 11 is not functionally utilized by the present claim 1, other than being present). With respect to the arguments of the last art rejection of the claims 1-2, 21-22 & 27-28 over the Bassman reference. The examiner disagrees with the applicant’s argument presented on page 8 of the amendment. More specifically, the examiner disagrees with the applicant’s interpretation of the claimed invention and the interpretation of the art rejection applied in the last office action; the applicant’s arguments are not commensurate with the claimed invention and the thrust/content of the art rejection; therefore, the applicant’s argument is not supported by the recited/claimed invention (i.e., the applicant’s contention is based on “separate component from the managed devices it monitors…operate from a different power plane…”). As can be seen from the 103-art rejection, the rejection is based on the functionally equivalent teachings of the claimed invention; furthermore, the claimed invention does not support applicant’s argument. Therefore, the examiner maintains the art rejection as follows . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-2, 21-22 & 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Bassman et al. (US 2020/0133355) . The examiner relies on the entire teachings of the Bassman reference fand the official notice teachings for this rejection; the examiner kindly advises the applicant to carefully consider the entire teachings of the Bassman, Seo, Keshava & KESHAVA references to better understand the examiner’s position & the interpretation applied to the claimed invention. The Bassman reference teaches, when the examiner applies Broadest Reasonable Interpretation to the claimed invention, functionally equivalent limitations of the claimed invention as follows: CLAIMS 1-2, 21-22 & 27-28 Bassman REF TEACHINGS 1.An apparatus comprising: processing circuitry coupled to memory devices; and FIG 2 with accompanying description, a IHS (200) includes STORAGE CONTROLLER (230) and/or REMOTE ACCESS CONTROLLER (255) with STORAGE DRIVES (240a..240n), see also MEMORY MODULE (210) a memory controller coupled to the memory devices, the memory controller comprising a reset controller and sideband circuitry, FIG 2 with accompanying description, a IHS (200) includes STORAGE CONTROLLER (230) and/or REMOTE ACCESS CONTROLLER (255) with STORAGE DRIVES (240a..240n), the 255 and/or 230 & 230a teach the memory controller comprised of reset controller and sideband circuitry wherein, via the reset controller, the memory controller to monitor a reset signal and FIG 2 with accompanying description, par 57, “resetting the state of the I2C controller utilized by the managed device…signaling the resetting of the bus to the remote access controller”(the examiner notes that the 255 monitors the reset signal from 230a); par 62, “the sideband bus monitor will reset the sideband bus based on the sideband bus timer configured by the remote access controller”; see also par 48, “restarting the managed device in order to reinitialize the sideband bus is possible…” drive an output reset signal to reset components in response to assertion of the reset signal FIG 2 with accompanying description, par 57, “resetting the state of the I2C controller utilized by the managed device…signaling the resetting of the bus to the remote access controller” (the examiner notes that the 255c/255n monitors the reset signal from 230a 2. The apparatus claim 1, wherein the memory controller to drive the output reset signal for a duration of time, wherein the duration of time is programmed in a control register associated with the memory controller. FIG 2 with accompanying description, par 57, “resetting the state of the I2C controller utilized by the managed device…signaling the resetting of the bus to the remote access controller”; par 62, “the sideband bus monitor will reset the sideband bus based on the sideband bus timer configured by the remote access controller”; see also par 48, “restarting the managed device in order to reinitialize the sideband bus is possible…” The examiner notes that this is also well-known in the art (See, Seo et al figure 4 with accompanying description) 21. (New) A memory system comprising: memory devices coupled to processing circuitry; and a memory controller coupled to the memory devices, the memory controller comprising a reset controller and sideband circuitry, wherein, via the reset controller, the memory controller to monitor a reset signal and drive an output reset signal to reset components in response to assertion of the reset signal. The teachings of the claim 1 are similarly applied 22. (New) The memory system of claim 21, wherein the memory controller to drive the output reset signal for a duration of time, wherein the duration of time is programmed in a control register associated with the memory controller. The teachings of the claim 2 are similarly applied 27. (New) A method comprising: monitoring, by memory controller coupled to the memory devices further coupled to processing circuitry of a computing device, a reset signal and drive an output reset signal to reset components in response to assertion of the reset signal, the memory controller comprising a reset controller and sideband circuitry; and driving an output reset signal to reset components in response to assertion of the reset signal. The teachings of the claim 1 are similarly applied 28. (New) The method of claim 27, further comprising driving, by the memory controller, an output reset signal for a duration of time, wherein the duration of time is programmed in a control register associated with the memory controller. The teachings of the claim 1 are similarly applied Examiner notes that the Bassman reference does not expressly or identically disclose or use the claimed “memory” (i.e., the Bassman reference teachings of figures 1-2 includes/discloses a similar memory or storage devices); however, such difference in usage of “memory” terminology is a nominal difference that are not expressly utilized in the claimed invention. In addition, the Basman reference teaches the functional equivalence teachings of the claimed invention (i.e., reset function/method/apparatus), and, as also demonstrated by the supportive teachings of the Official Notice, the resetting parts of an apparatus is well-known and commonly practiced in the art of the claimed invention. Therefore, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to come up with the claimed invention from the functionally equivalent teachings of the Bassman reference for the detailed teachings and reasons, including the well-known teachings, discussed above . 07-21-aia AIA Claim s 1-3, 5, 10-11 & 21-32 (similar to the previous claims 1-20) are rejected under 35 U.S.C. 103 as being unpatentable over Mishra et al. (US 2018/0173667 A1) in view of LE et al. (US 2020/0226045 A1) . The examiner maintains substantially the same art rejections of the last office action of the claims 1-3, 5, 10-11, 21-32 (i.e., the present claims 1-21-27, 2-22-28, 3-23-27, 5-24-30, 10-25-31 & 11-26-32 are substantially/functionally identical (i.e., the dash lined claims); furthermore, the present claim 1 is substantially identical to the previous claim 1; the present claim 2 is substantially identical to the previous claim 2; the present claim 3 is substantially identical to the previous claims 3 & 4; the present claim 5 is substantially identical to the previous claims 5 & 6; the present claim 10 is substantially identical to the previous claims 10 & 11; and the present claim 11 is not functionally utilized by the present claim 1, other than being present). Consequently, the previous teachings of the substantially identical claims of the present claims are similarly applied, and the identical claims of the present claims 11, 16 & 32 are substantially obviously/identically taught (i.e., claimed functionally equivalent) by the “processing circuitry” teachings of the claim 1, 21 & 27. The above discussed teachings of the Bassman reference & the official notice teachings provide well-known teachings in the art of resetting function/system; therefore, the examiner takes official notice that the claimed features/recitations are well-known in the art. The examiner relies on the entire teachings of the Mishra & LE references for this rejection; the examiner kindly advises the applicant to carefully consider the entire teachings of the Bassman reference & above discussed official notice teachings to better understand the examiner’s position & the interpretation applied to the claimed invention. The Mishra & LE references teach, when the examiner applies Broadest Reasonable Interpretation to the claimed invention, functionally equivalent limitations of the claimed invention as follows: CLAIMS 1-20 (1-3, 5, 10-11, & 21-32) Mishra REF. TEACHINGS LE REF. TEACHINGS 1.A memory module comprising: a plurality of memory devices ; and FIG 2 with accompanying description, a device 202 includes storage 224 & controller logic 212; examiner any slave devices can be memory devices Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings a memory module management controller coupled to the plurality of memory devices, the memory module management controller comprising a reset controller and sideband bus control circuitry, FIG 2 & 16 with accompanying description, SoC Device 1600 having a reset controller 1604 performs the reset and sideband control circuitry function of the claimed invention Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings from a memory controller in a host system that is communicatively coupled to the memory module and FIG 2, 15 & 16 with accompanying description, SoC Device 1600 having a reset controller 1604 performs the reset and sideband control circuitry function of the claimed invention ; the examiner notes that the Host Device 1500 teaches the host memory controller Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings to drive an output reset signal to reset components in the memory module in response to assertion of the reset signal. FIG 2, 15 & 16 with accompanying description, par 144, “device 1600 may include a reset controller 1604 configured to decode signals transmitted on serial bus and to drive reset signals 1626, 1628, 1630 and 1632…” Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings 2. The memory module of Claim 1, wherein a memory module management controller to drive the output reset signal to a component for a duration of time for the component, the duration of time programmed in a control register in the memory module management controller. Obvious from the teachings of FIG 2, 15 & 16 with accompanying description, par 144, “device 1600 may include a reset controller 1604 configured to decode signals transmitted on serial bus and to drive reset signals 1626, 1628, 1630 and 1632…” & par 147, “Output gating logic 1612 may be provided to enable selective generation of the reset signals 1626, 1628, 1630 and 1632…can operate autonomously and can force hard other components 1602, 1606, 1608 within the Soc…outside the reset controller 1604 may respond to select signals, control signals, reset signals and/or multi-bit codes that can be used to generate specific combinations of reset signals”; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings 3. The memory module of Claim 1, wherein a short pulse on the reset signal to indicate a request to reset the sideband bus control circuitry. Obvious from the teachings of FIG 16-17 with accompanying description, par 155, “device reset pattern 1700 that may be used to target device or function 1602, 1606, 1608 and/or a group of devices or functions”; the examiner notes that reset pattern teaches the functionally equivalent limitation of the short/long pulse; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings 4. The memory module of Claim 1, wherein a long pulse on the reset signal to indicate a request to reset components in the memory module management controller and other devices on the memory module. Obvious from the teachings of FIG 16-17 with accompanying description, par 155 “device reset pattern 1700 that may be used to target device or function 1602, 1606, 1608 and/or a group of devices or functions”; the examiner notes that reset pattern teaches the functionally equivalent limitation of the short/long pulse; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings 5. The memory module of Claim 4, wherein the reset controller to assert a memory reset signal to reset one or more memory devices on the memory module. Obvious from the teachings of FIG 2, 15-17 with accompanying description, par 144, “device 1600 may include a reset controller 1604 configured to decode signals transmitted on serial bus and to drive reset signals 1626, 1628, 1630 and 1632…” & par 147, “Output gating logic 1612 may be provided to enable selective generation of the reset signals 1626, 1628, 1630 and 1632…can operate autonomously and can force hard other components 1602, 1606, 1608 within the Soc…outside the reset controller 1604 may respond to select signals, control signals, reset signals and/or multi-bit codes that can be used to generate specific combinations of reset signals”; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings 6. The memory module of Claim 4, wherein the reset controller to assert a data buffer reset to reset one or more buffers on the memory module. Obvious from the teachings of FIG 2, 15-17 with accompanying description, par 144, “device 1600 may include a reset controller 1604 configured to decode signals transmitted on serial bus and to drive reset signals 1626, 1628, 1630 and 1632…” & par 147, “Output gating logic 1612 may be provided to enable selective generation of the reset signals 1626, 1628, 1630 and 1632…can operate autonomously and can force hard other components 1602, 1606, 1608 within the Soc…outside the reset controller 1604 may respond to select signals, control signals, reset signals and/or multi-bit codes that can be used to generate specific combinations of reset signals”; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings 7. The memory module of Claim 1, wherein the reset controller to reset components in the memory module in response to a command received from the sideband bus control circuitry. Obvious from the teachings of FIG 16-17 with accompanying description, par 155, “device reset pattern 1700 that may be used to target device or function 1602, 1606, 1608 and/or a group of devices or functions”; the examiner notes that reset pattern teaches the functionally equivalent limitation of the short/long pulse; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings 8. The memory module of Claim 1, wherein the reset controller to interrupt power for a duration of time to a component to reset the component in the memory module. Obvious from the teachings of FIG 16-17 with accompanying description, par 146, “reset controller 1604 to assert a reset signal 1632 directed to the power-on logic, which causes the power-on logic to drive a global reset signal 1624 that resets all device and functions”; the examiner notes that the reset the power-on logic teaches interrupt power for a duration of time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings 9. The memory module of Claim 8, wherein the duration of time is programmed in a control register. Obvious from the teachings of FIG 16-17 with accompanying description, par 150, “different values in RGR and RGR can ensure that one or more of the reset signals 1626, 1628, 1630 and 1632 are generated when a device reset pattern or other singling is detected on the serial bus…may be suppressed by writing the device address of the peripheral 1600”; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings Figs 2-3 with accompanying description teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings 10. The memory module of Claim 1, wherein the memory module is a Dual Inline Memory Module (DIMM). Figs 2-3 with accompanying description; par 11, “DIMMs fails, it is often…electrically isolated” teaches well-known memory module/device configuration in the art that uses SIDEBAND BUS & RESET, se also figure 5A-5C with accompanying description; the examiner notes that reset pattern teaches the functionally equivalent limitation of the duration time; the examiner also notes that this is also well-known in the art, as disused in the official notice teachings 11. The memory module of Claim 1, wherein the sideband bus control circuitry to control an I3C serial bus. Inherent/obvoius features of I2C and I3C of figures 15-16 12. A system comprising: a memory controller; and a memory module comprising: a plurality of memory devices; and a memory module management controller coupled to the plurality of memory devices, the memory module management controller comprising a reset controller and sideband bus control circuitry, the reset controller to monitor a reset signal received from the memory controller that is communicatively coupled to the memory module and to drive an output reset signal to reset components in the memory module in response to assertion of the reset signal. The teachings of the claim 1 are similarly applied The teachings of the claim 1 are similarly applied 13. The system of Claim 12, wherein a memory module management controller to drive the output reset signal to a component for a duration of time for the component, the duration of time programmed in a control register in the memory module management controller. The teachings of the claim 2 are similarly applied The teachings of the claim 2 are similarly applied 14. The system of Claim 12, wherein a short duration pulse on the reset signal to indicate a request to reset the sideband bus control circuitry. The teachings of the claim 3 are similarly applied The teachings of the claim 3 are similarly applied 15. The system of Claim 12, wherein a long duration pulse on the reset signal to indicate a request to reset components in the memory module management controller and other devices on the memory module. The teachings of the claim 4 are similarly applied The teachings of the claim 4 are similarly applied 16. The system of claim 12, further comprising one or more of: at least one processor communicatively coupled to the memory controller; a display communicatively coupled to at least one processor; or a power supply to provide power to the system. Obvious features of figure 1 and/or well-known & commonly practiced features in the art Obvious features of figure 2 and/or well-known & commonly practiced features in the art 17. A method comprising: monitoring, by a reset controller in memory module management controller in a memory module, a reset signal received from a memory controller in a host system that is communicatively coupled to the memory module, the memory module management controller coupled to a plurality of memory devices, the memory module management controller comprising sideband bus control circuitry; and driving, by the reset controller, an output reset signal to reset components in the memory module in response to assertion of the reset signal. The teachings of the claim 1 are similarly applied The teachings of the claim 1 are similarly applied 18. The method of Claim 17, wherein the reset controller to drive the output reset signal to a component for a duration of time for the component, the duration of time programmed in a control register in the memory module management controller. The teachings of the claim 2 are similarly applied The teachings of the claim 2 are similarly applied 19. The method of Claim 17, wherein a short duration pulse on the reset signal to indicate a request to reset the sideband bus control circuitry. The teachings of the claim 3 are similarly applied The teachings of the claim 3 are similarly applied 20. The method of Claim 17, wherein a long duration pulse on the reset signal to indicate a request to reset components in the memory module management controller and other devices on the memory module. The teachings of the claim 4 are similarly applied The teachings of the claim 4 are similarly applied Examiner notes that the Mishra reference does not expressly or identically disclose or use the claimed “memory” (i.e., figures 1-2 of the Mishra reference teachings includes/discloses similar memory or storage devices); however, such difference in usage of the “memory” terminology is a nominal difference that are not expressly utilized in the claimed invention, and also the claimed memory terminology is well-known & commonly practiced in the art of memory system as evidenced by the LE reference teachings (I.e., the well-known system from the same applicant). In addition, the LE reference further teaches the motivation of using SIDEBAND BUS (e.g., typically & commonly known in the art to use I2C/I3C protocol) & RESET signals; moreover, the Mishra reference teaches the functional equivalence teachings of the claimed invention (i.e., reset function/method/apparatus). In addition, the examiner also demonstrated by the supportive teachings of the Official Notice, the resetting parts of an apparatus is well-known and commonly practiced in the art of the claimed invention. Therefore, since both of the teachings of the Mishra & LE references are directed to the same field of resetting functions/operations in a device or system with the memory, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to add/combine the functionally equivalent reset teachings of the Mishra reference to/with the memory device teachings with the reset motivation of the LE reference for establishing an efficient resetting function in a memory system (i.e., resetting function/operations are one of necessary operations for proper operations of memory systems) for the detailed teachings and reasons discussed above. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER B SHIN whose telephone number is (571)272-4159. The examiner can normally be reached 8:00-4:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached at 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER B SHIN/Primary Examiner, Art Unit 2181 Application/Control Number: 18/123,218 Page 2 Art Unit: 2181 Application/Control Number: 18/123,218 Page 3 Art Unit: 2181 Application/Control Number: 18/123,218 Page 4 Art Unit: 2181 Application/Control Number: 18/123,218 Page 5 Art Unit: 2181 Application/Control Number: 18/123,218 Page 6 Art Unit: 2181 Application/Control Number: 18/123,218 Page 7 Art Unit: 2181 Application/Control Number: 18/123,218 Page 8 Art Unit: 2181 Application/Control Number: 18/123,218 Page 9 Art Unit: 2181 Application/Control Number: 18/123,218 Page 10 Art Unit: 2181 Application/Control Number: 18/123,218 Page 11 Art Unit: 2181 Application/Control Number: 18/123,218 Page 12 Art Unit: 2181 Application/Control Number: 18/123,218 Page 13 Art Unit: 2181 Application/Control Number: 18/123,218 Page 14 Art Unit: 2181 Application/Control Number: 18/123,218 Page 15 Art Unit: 2181 Application/Control Number: 18/123,218 Page 16 Art Unit: 2181 Application/Control Number: 18/123,218 Page 17 Art Unit: 2181 Application/Control Number: 18/123,218 Page 18 Art Unit: 2181 Application/Control Number: 18/123,218 Page 19 Art Unit: 2181 Application/Control Number: 18/123,218 Page 20 Art Unit: 2181
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