DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed on 12/18/2025.
Claims 1-17 are pending.
Claim Objections
Claims 2 and 6 are objected to because they fail to comply with 37 CFR 1.121(c). 37 CFR 1.121(c)(2) requires that “All claims being currently amended in an amendment paper shall be presented in the claim listing, indicate a status of "currently amended," and be submitted with markings to indicate the changes that have been made relative to the immediate prior version of the claims. The text of any added subject matter must be shown by underlining the added text. The text of any deleted matter must be shown by strike-through except that double brackets placed before and after the deleted characters may be used to show deletion of five or fewer consecutive characters”.
Claim 2 previously included the limitation “is configured to: exclude””; however, this is shown in the claim with an underline denoting added text. Further, the word “switches” is present in the current claim with a strikethrough, but the previous claim 2 stated “switch”.
Claim 6 previously included the limitation “is configured to identify”; however, this has not been shown in the claim as removed text. Further, the word “identifies” is present in the current claim with a strikethrough, but was not present in the previous claim 6.
Examiner suggests canceling affected claims and adding new claims to replace them in order to provide clarity and update the claims in compliance with 37 CFR 1.121(c). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2-8 recite the limitation “individually and/or collectively”. It is unclear whether this is meant to mean “individually and collectively” or “individually or collectively”. Examiner will interpret this to mean “individually or collectively”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-17 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1: Claims 1-8 and 16 are directed to an electronic apparatus and fall within the statutory category of machine. Claims 9-15 and 17 are directed to a method and fall within the statutory category of process. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 1 and 9: The limitations of “identify(ing) whether processes among the plurality of processes loaded into the first memory are in an inactivated state,”, “identify(ing) a process switched to an inactivated state among the plurality of processes loaded into the first memory”, and “identify a second process among the plurality of processes not in the inactivated state”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe processes among a plurality of processes and, based on these observations, can mentally identify whether the processes are in inactivated state or not.
Therefore, Yes, claims 1 and 9 recite a judicial exception.
Step 2A Prong 2:
Claims 1 and 9: The judicial exception is not integrated into a practical application. In particular, the claims recite additional element recitations of “a first memory;” and “a second memory, wherein the second memory comprises a first area configured to store and retrieve data using sequential access method and a second area configured to store and retrieve data using random access method;”, which are merely recitations of technological environment/field of use (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, the claims recite additional element recitations of “and at least one processor comprising processing circuitry, the at least one processor, individually and/or collectively, configured to:”, which are merely recitations of generic computing components (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, the claims recite additional element recitations of “load(ing) a plurality of processes of an application into the first memory,”, “and store(ing) data of the first process in the first area of the second memory by the sequential access method,”, “and store(ing) data of the second process in the second area of the second memory by the random access method,”, and “and based on an event that the first process stored in the first area of the second memory is restored from the inactivated state to an activated state, load(ing) the data of the first process stored in the first area into the first memory”, which are merely recitations of data storage, which is insignificant extra solution activity (see MPEP §2106.05(g)) which does not integrate a judicial exception into practical application.
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea.
After having evaluated the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 1 and 9 not only recite a judicial exception but that the claims are directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claims 1 and 9: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components, field of use/technological environment, and insignificant extra solution activity which do not amount to significantly more than the abstract idea. Further, the insignificant extra solution activity is well-understood, routine, and conventional in the art. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network…iv. Storing and retrieving information in memory” [MPEP§ 2106.05(d)(II)].
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, Claims 1 and 9 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 2 and 10, the claims recite additional abstract idea recitations of “exclude at least one process to be switched to the inactivated state among the plurality of processes of the application loaded into the first memory from a scheduling target;” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe a process to be switched to an inactivated state, and based on this observation, can mentally exclude the process from a scheduling target. This can be done by generating a mental schedule without the process included. This may also be done with pencil and paper. Further, the claims recite additional element recitations of “and switch the excluded at least one process to the inactivated state” which is merely a recitation of using a computer as a tool, through a generic computing function, to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claims 2 and 10 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 2 and 10 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 2 and 10 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 3 and 11, the claims recite additional element recitations of “load the plurality of processes of the application into the first memory based on spare capacity of the first memory and average usage of the at least one processor”, which are merely recitations of data storage, which is insignificant extra solution activity (see MPEP §2106.05(g)) which does not integrate a judicial exception into practical application. Further, the insignificant extra solution activity is well-understood, routine, and conventional in the art. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network…iv. Storing and retrieving information in memory” [MPEP§ 2106.05(d)(II)]. Further, claims 3 and 11 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 3 and 11 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 3 and 11 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 4 and 12, the claims recite additional element recitations of “load(ing) the plurality of processes of the application into the first memory based on preparation for executing the application”, which are merely recitations of data storage, which is insignificant extra solution activity (see MPEP §2106.05(g)) which does not integrate a judicial exception into practical application. Further, the insignificant extra solution activity is well-understood, routine, and conventional in the art. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network…iv. Storing and retrieving information in memory” [MPEP§ 2106.05(d)(II)]. Further, claims 4 and 12 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 4 and 12 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 4 and 12 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 5 and 13, the claims recite additional abstract idea recitations of “identify(ing) that the preparation for executing the application has occurred based on at least one of spare capacity of the first memory, speed of the processor, or average usage of the processor” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe a spare capacity of a first memory, speed of a processor, or average usage of a processor, and based on this observation can identify, through mental evaluation, that the preparation for executing an application has occurred. Further, claims 5 and 13 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 5 and 13 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 5 and 13 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 6 and 14, the claims recite additional abstract idea recitations of “identify(ing) that an event has occurred based on an input received through the interface to execute the application” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe an input received through an interface to execute an application, and based on this observation can identify, through mental evaluation, that an event has occurred. Further, the claims recite additional element recitations of “further comprising an interface,”, which is merely a recitation of technological environment/field of use (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, claims 6 and 14 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 6 and 14 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 6 and 14 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 7 and 15, the claims recite additional abstract idea recitations of “add(ing) the first process, the data of which is stored in the first area of the second memory, to a scheduling target based on an event”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe an event and, based on these observations, can mentally add a process to a mental scheduling target. This may also be done with pencil and paper. Further, the claims recite additional abstract idea recitations of “and restoring the firstprocess to the activated state”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally assign an activated state to a process. This may also be done with pencil and paper. Further, the claims recite additional element recitations of “an event, to restore the process to the activated state”, which is merely a recitation of using a computer as a tool, through a generic computing function, to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claims 7 and 15 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 7 and 15 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 7 and 15 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 8, the claim recites additional abstract idea recitations of “identify one or more processes of the application that are absent in the first memory based on an event,”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe an event and, based on these observations, can mentally identify whether a plurality of processes of an application are absent from a first memory. Further, the claims recite additional abstract idea recitations of “identify an area of the second memory, in which the data of the identified one or more processes is stored”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe a process and, based on these observations, can mentally identify the area of a second memory, in which the data of the process is stored. Further, the claim recites additional element recitations of “load the data of the identified one or more processes from the identified area of the second memory to the first memory”, which are merely recitations of data storage, which is insignificant extra solution activity (see MPEP §2106.05(g)) which does not integrate a judicial exception into practical application. Further, the insignificant extra solution activity is well-understood, routine, and conventional in the art. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network…iv. Storing and retrieving information in memory” [MPEP§ 2106.05(d)(II)]. Further, claim 8 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 8 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 8 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 16 and 17, the claims recite additional element recitations of “wherein the first memory comprises a volatile memory, and wherein the second memory comprises a nonvolatile memory”, which are merely recitations of technological environment/field of use (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, claims 16 and 17 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 16 and 17 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 16 and 17 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Therefore, Claims 1-17 do not recite patent eligible subject matter under U.S.C. §101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6-9, 12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Bavishi (US 2020/0278797 A1) in view of Iwabuchi (US 2017 /0153842 A1) in view of Dastidar (US 10,922,226 B1) in view of Noro (US 2017/0262390 A1).
With regard to claim 1, Bavishi teaches:
An electronic apparatus comprising: a first memory; “In some embodiments, the read-only cache and/or the write-read cache (first memory) can be preloaded with data prior to receiving memory access requests from the host system. For example, the read-only cache and/or the write-read cache can be preloaded during initialization of an application executing on the host system” [Bavishi ¶ 27 Examiner notes the read-only cache 200 and the write-read cache 202 are considered the first memory].
a second memory, “The memory sub-system 110 can include media, such as memory components 112A to 112N. The memory components 112A to 112N can be volatile memory components, non-volatile memory components, or a combination of such. In some embodiments, the memory sub-system is a storage system” [Bavishi ¶ 34]. “The separate read-only and write-read caches can be located between the host system and the media components, also referred to as a "backing store," (second memory) of the memory sub-system” [Bavishi ¶ 22 Examiner notes the backing store is considered the second memory].
wherein the second memory comprises a first area configured to store and retrieve data using sequential access method and a second area configured to store and retrieve data using random access method; “The different types of memory access workloads can be sequential (in-order) and random (out-of-order) accesses. For example, an application can request to read original data from an address, write different data to the address, and read the different data from the address” [Bavishi ¶ 20].
and at least one processor comprising processing circuitry, the at least one processor, individually and/or collectively, configured to: “The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119” [Bavishi ¶ 37].
load a plurality of processes of an application into the first memory, “In some embodiments, the read-only cache and/or the write-read cache can be preloaded with data prior to receiving memory access requests from the host system. For example, the read-only cache and/or the write-read cache can be preloaded during initialization of an application executing on the host system” [Bavishi ¶ 27].
identify a first process among the plurality of processes that is in the inactivated state “The evict queue 218 can be used to evict data from the read-only cache 200 and/or the write-read cache 202 as desired. For example, when the read-only cache 200 and/or the write-read cache 202 are full (every cache line includes at least some valid data in one or more sectors), an eviction policy such as least recently used can be used to select the cache line with data that is least recently used to evict. The data of the selected cache line can be read out of the read-only cache 200 and/or write-read cache 202 and stored in the evict queue 218” [Bavishi ¶ 46].
and store data of the first process in the first area of the second memory “During operation, when is the memory sub-system determines to flush either of the caches 200 or 202, the dirty cache lines can be identified and queued to the evict queue 218 to be sent to the backing store” [Bavishi ¶ 51].
Bavishi fails to teach wherein the second memory comprises a first area configured to store and retrieve data using sequential access method and a second area configured to store and retrieve data using random access method; and store data of the first process in the first area of the second memory by the sequential access method, identify a second process among the plurality of processes not in the inactivated state and store data of the second process in the second area of the second memory by the random access method.
However, Iwabuchi teaches:
wherein the second memory comprises a first area configured to store and retrieve data using sequential access method and a second area configured to store and retrieve data using random access method; “As such, an SMR HDD may be configured to allocate data based on how frequently the data is modified or how often the data is predicted to be modified. The predictability arises from dividing the SMR HDD into random access zones and sequential access zones and allocating the data into one of the two types of zones” [Iwabuchi ¶ 13].
and store data of the first process in the first area of the second memory by the sequential access method, “If the file is not accessed for a predetermined period of time and controller 8 updated the hinting bits to be equal to 11, controller 8 may classify the data block as a cold data block. Cold data blocks may be most efficiently stored in the sequential access zone, as access to the cold data blocks is limited” [Iwabuchi ¶ 74].
identify a second process among the plurality of processes not in the inactivated state and store data of the second process in the second area of the second memory by the random access method, “In other instances, such as when controller 8 updates the hinting bits to be equal to 10 based on the increments performed on the set of counter bits, controller 8 may determine that the unknown media file is accessed frequently enough that it is more efficient to store the data block in a random access zone. As such, responsive to controller 8 updating the hinting bits, controller 8 may move the data block from the sequential access zone to the random access zone” [Iwabuchi ¶ 74].
Iwabuchi is considered to be analogous to the claimed invention because it is in the same field of improving the reliability of storage systems. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi to incorporate the teachings of Iwabuchi and include wherein the second memory comprises a first area configured to store and retrieve data using sequential access method and a second area configured to store and retrieve data using random access method; and store data of the first process in the first area of the second memory by the sequential access method, identify a second process among the plurality of processes not in the inactivated state and store data of the second process in the second area of the second memory by the random access method. Doing so would allow for further efficiency in the storage of data. “Cold data blocks may be most efficiently stored in the sequential access zone, as access to the cold data blocks is limited” [Iwabuchi ¶ 74].
Bavishi in view of Iwabuchi fails to explicitly teach identify whether processes among the plurality of processes loaded into the first memory are in an inactivated state.
However, Dastidar teaches identify whether processes among the plurality of processes loaded into the first memory are in an inactivated state, “At step 504, the kernel 228 determines that an address space for an inactive process executing on a peripheral needs to be swapped out to storage” [Dastidar Col. 6-7 Lines 65-67, 1]. “In the example of FIG. 2, the kernel 228 can determine that app-A is inactive. In such case, the kernel 228 swaps out app-A regular memory 214 to storage, since the app-A regular pages 220 are marked as regular memory” [Dastidar Col. 7 Lines 10-13].
Dastidar is considered to be analogous to the claimed invention because it is in the same field of improving the reliability of storage systems. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi in view of Iwabuchi to incorporate the teachings of Dastidar and include identify whether processes among the plurality of processes loaded into the first memory are in an inactivated state. Doing so would allow for the system to identify entire applications and corresponding processes which are inactive for memory swapping. “At step 510, the kernel 228 swaps dirty pages in regular memory to storage. At step 512, the kernel 228 completes the swap operation” [Dastidar Col. 7 Lines 6-8].
Bavishi in view of Iwabuchi in view of Dastidar fails to explicitly teach and based on an event that the first process stored in the first area of the second memory is restored from the inactivated state to an activated state, load the data of the first process stored in the first area into the first memory.
However, Noro teaches:
and based on an event that the first process stored in the first area of the second memory is restored from the inactivated state to an activated state, “When shortage of the memory 11 occurs, the memory manager 10 transmits a memory saving instruction to the swap manager 8b and, when data that is not in the memory 11 is needed (restored to an activated state), transmits a memory restoration instruction to the swap manager 8b” [Noro ¶ 70].
load the data of the first process stored in the first area into the first memory. “As described above, the smart device 1a saves the data unneeded when the user processing is restarted in the swap area and thus is able to save and restore data by using the swap function” [Noro ¶ 64].
Noro is considered to be analogous to the claimed invention because it is in the same field of program loading. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi in view of Iwabuchi in view of Dastidar to incorporate the teachings of Noro and include based on an event that the first process stored in the first area of the second memory is restored from the inactivated state to an activated state, load the data of the first process stored in the first area into the first memory. Doing so would allow for the system to restore data at the time when it is needed for application operation. “As described above, the smart device 1a saves the data unneeded when the user processing is restarted in the swap area and thus is able to save and restore data by using the swap function” [Noro ¶ 64].
With regard to claim 4, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the electronic apparatus of claim 1, as referenced above. Bavishi further teaches wherein the at least one processor, individually and/or collectively, is configured to load the plurality of processes of the application into the first memory based on preparation for executing the application. “In some embodiments, the processing device can receive a command or instruction from an application to preload the read-only cache or the write-read cache with the data associated with the application. Such data can be data that is to be used by or operated on by the application” [Bavishi ¶ 58]. “In some embodiments, the read-only cache and/or the write-read cache can be preloaded with data prior to receiving memory access requests from the host system. For example, the read-only cache and/or the write-read cache can be preloaded during initialization of an application executing on the host system” [Bavishi ¶ 27].
With regard to claim 6, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the electronic apparatus of claim 1, as referenced above. Bavishi further teaches further comprising an interface, wherein the at least one processor, individually and/or collectively, is configured to: identify that the event has occurred based on an input received through the interface to execute the application. “The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands (input) received from the host system into command instructions to access the memory components 112A to 112N as well as convert responses associated with the memory components 112A to 112N into information for the host system 120” [Bavishi ¶ 38].
With regard to claim 7, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the electronic apparatus of claim 1, as referenced above. Bavishi further teaches:
wherein the at least one processor, individually and/or collectively, is configured to: add the first process, the data of which is stored in the first area of the second memory, “Fill operations can be generated to store the data obtained from the backing store in one or more sectors of a cache line in the read-only cache and/or the write-read cache” [Bavishi ¶ 27].
to a scheduling target based on an event, to restore the first process to the activated state. “The fill operations can be generated when a read request is received and the requested data is not found (cache miss) (event) in either read-only cache 200 or write-read cache 202” [Bavishi ¶ 45]. “In some embodiments, to further improve performance and quality of service of the memory sub-system, a priority scheduler can be used with a priority queue to determine a schedule (scheduling target) of when to execute requests and fill operations. As described above, the outstanding command queues can queue misses for read requests for data and misses for write requests for data in the caches. A priority scheduler can determine a schedule of when to execute the requests based on when the requests are received” [Bavishi ¶ 30 Examiner notes including a process in an execution schedule is considered restoring it to an activated state].
With regard to claim 8, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the electronic apparatus of claim 1, as referenced above. Bavishi further teaches:
wherein the at least one processor, individually and/or collectively, is configured to: identify one or more processes of the application that are absent in the first memory based on an event, “When data requested (event) to be read is already present in either of the read-only cache or the write-read cache, the read request can be performed to read the data from the appropriate cache line storing the requested data. When there is a cache miss and neither the read-only cache nor the write-read cache stores the requested data, the read requests can be processed using the outstanding command queues” [Bavishi ¶ 57].
identify an area of the second memory, in which the data of the identified one or more processes is stored, and load the data of the identified one or more processes from the identified area of the second memory to the first memory. “At operation 710, the processing device determines that data requested by a set of read operations has been retrieved from a memory component of a memory subsystem … At block 720, the processing device executes the one or more fill operations to store the data at a cache line of a cache of the memory sub-system. A fill operation can be generated when the data is retrieved from the backing store” [Bavishi ¶ 55].
With regard to claim 9, Bavishi teaches:
A method of controlling an electronic apparatus comprising a first memory “In some embodiments, the read-only cache and/or the write-read cache (first memory) can be preloaded with data prior to receiving memory access requests from the host system. For example, the read-only cache and/or the write-read cache can be preloaded during initialization of an application executing on the host system” [Bavishi ¶ 27 Examiner notes the read-only cache 200 and the write-read cache 202 are considered the first memory].
and a second memory, “The memory sub-system 110 can include media, such as memory components 112A to 112N. The memory components 112A to 112N can be volatile memory components, non-volatile memory components, or a combination of such. In some embodiments, the memory sub-system is a storage system” [Bavishi ¶ 34]. “The separate read-only and write-read caches can be located between the host system and the media components, also referred to as a "backing store," (second memory) of the memory sub-system” [Bavishi ¶ 22 Examiner notes the backing store is considered the second memory].
wherein the second memory comprises a first area configured to store and retrieve data using sequential access method and a second area configured to store and retrieve data using random access method, “The different types of memory access workloads can be sequential (in-order) and random (out-of-order) accesses. For example, an application can request to read original data from an address, write different data to the address, and read the different data from the address” [Bavishi ¶ 20].
the method comprising: loading a plurality of processes of an application into the first memory, “In some embodiments, the read-only cache and/or the write-read cache can be preloaded with data prior to receiving memory access requests from the host system. For example, the read-only cache and/or the write-read cache can be preloaded during initialization of an application executing on the host system” [Bavishi ¶ 27].
identifying a first process among the plurality of processes that is in the inactivated state “The evict queue 218 can be used to evict data from the read-only cache 200 and/or the write-read cache 202 as desired. For example, when the read-only cache 200 and/or the write-read cache 202 are full (every cache line includes at least some valid data in one or more sectors), an eviction policy such as least recently used can be used to select the cache line with data that is least recently used to evict. The data of the selected cache line can be read out of the read-only cache 200 and/or write-read cache 202 and stored in the evict queue 218” [Bavishi ¶ 46].
and storing data of the first process in the first area of the second memory “During operation, when is the memory sub-system determines to flush either of the caches 200 or 202, the dirty cache lines can be identified and queued to the evict queue 218 to be sent to the backing store” [Bavishi ¶ 51].
Bavishi fails to teach wherein the second memory comprises a first area configured to store and retrieve data using sequential access method and a second area configured to store and retrieve data using random access method; and storing data of the first process in the first area of the second memory by the sequential access method, identifying a second process among the plurality of processes not in the inactivated state and storing data of the second process in the second area of the second memory by the random access method.
However, Iwabuchi teaches:
wherein the second memory comprises a first area configured to store and retrieve data using sequential access method and a second area configured to store and retrieve data using random access method; “As such, an SMR HDD may be configured to allocate data based on how frequently the data is modified or how often the data is predicted to be modified. The predictability arises from dividing the SMR HDD into random access zones and sequential access zones and allocating the data into one of the two types of zones” [Iwabuchi ¶ 13].
and storing data of the first process in the first area of the second memory by the sequential access method, “If the file is not accessed for a predetermined period of time and controller 8 updated the hinting bits to be equal to 11, controller 8 may classify the data block as a cold data block. Cold data blocks may be most efficiently stored in the sequential access zone, as access to the cold data blocks is limited” [Iwabuchi ¶ 74].
identifying a second process among the plurality of processes not in the inactivated state and storing data of the second process in the second area of the second memory by the random access method, “In other instances, such as when controller 8 updates the hinting bits to be equal to 10 based on the increments performed on the set of counter bits, controller 8 may determine that the unknown media file is accessed frequently enough that it is more efficient to store the data block in a random access zone. As such, responsive to controller 8 updating the hinting bits, controller 8 may move the data block from the sequential access zone to the random access zone” [Iwabuchi ¶ 74].
Iwabuchi is considered to be analogous to the claimed invention because it is in the same field of improving the reliability of storage systems. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi to incorporate the teachings of Iwabuchi and include wherein the second memory comprises a first area configured to store and retrieve data using sequential access method and a second area configured to store and retrieve data using random access method; and storing data of the first process in the first area of the second memory by the sequential access method, identifying a second process among the plurality of processes not in the inactivated state and storing data of the second process in the second area of the second memory by the random access method. Doing so would allow for further efficiency in the storage of data. “Cold data blocks may be most efficiently stored in the sequential access zone, as access to the cold data blocks is limited” [Iwabuchi ¶ 74].
Bavishi in view of Iwabuchi fails to explicitly teach identifying whether processes among the plurality of processes loaded into the first memory are in an inactivated state.
However, Dastidar teaches identifying whether processes among the plurality of processes loaded into the first memory are in an inactivated state; “At step 504, the kernel 228 determines that an address space for an inactive process executing on a peripheral needs to be swapped out to storage” [Dastidar Col. 6-7 Lines 65-67, 1]. “In the example of FIG. 2, the kernel 228 can determine that app-A is inactive. In such case, the kernel 228 swaps out app-A regular memory 214 to storage, since the app-A regular pages 220 are marked as regular memory” [Dastidar Col. 7 Lines 10-13].
Dastidar is considered to be analogous to the claimed invention because it is in the same field of improving the reliability of storage systems. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi in view of Iwabuchi to incorporate the teachings of Dastidar and include identifying whether processes among the plurality of processes loaded into the first memory are in an inactivated state. Doing so would allow for the system to identify entire applications and corresponding processes which are inactive for memory swapping. “At step 510, the kernel 228 swaps dirty pages in regular memory to storage. At step 512, the kernel 228 completes the swap operation” [Dastidar Col. 7 Lines 6-8].
Bavishi in view of Iwabuchi in view of Dastidar fails to explicitly teach and based on an event that the first process stored in the first area of the second memory is restored from the inactivated state to an activated state, loading the data of the first process stored in the first area into the first memory.
However, Noro teaches:
and based on an event that the first process stored in the first area of the second memory is restored from the inactivated state to an activated state, “When shortage of the memory 11 occurs, the memory manager 10 transmits a memory saving instruction to the swap manager 8b and, when data that is not in the memory 11 is needed (restored to an activated state), transmits a memory restoration instruction to the swap manager 8b” [Noro ¶ 70].
loading the data of the first process stored in the first area into the first memory. “As described above, the smart device 1a saves the data unneeded when the user processing is restarted in the swap area and thus is able to save and restore data by using the swap function” [Noro ¶ 64].
Noro is considered to be analogous to the claimed invention because it is in the same field of program loading. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi in view of Iwabuchi in view of Dastidar to incorporate the teachings of Noro and include based on an event that the first process stored in the first area of the second memory is restored from the inactivated state to an activated state, loading the data of the first process stored in the first area into the first memory. Doing so would allow for the system to restore data at the time when it is needed for application operation. “As described above, the smart device 1a saves the data unneeded when the user processing is restarted in the swap area and thus is able to save and restore data by using the swap function” [Noro ¶ 64].
With regard to claim 12, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the method of claim 9, as referenced above. Bavishi further teaches wherein the loading the plurality of processes of the application into the first memory comprises loading the plurality of processes of the application into the first memory based on preparation for executing the application. “In some embodiments, the processing device can receive a command or instruction from an application to preload the read-only cache or the write-read cache with the data associated with the application. Such data can be data that is to be used by or operated on by the application” [Bavishi ¶ 58]. “In some embodiments, the read-only cache and/or the write-read cache can be preloaded with data prior to receiving memory access requests from the host system. For example, the read-only cache and/or the write-read cache can be preloaded during initialization of an application executing on the host system” [Bavishi ¶ 27].
With regard to claim 14, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the method of claim 9, as referenced above. Bavishi further teaches further comprising identifying that an event has occurred based on an input received through an interface to execute the application. “The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands (input) received from the host system into command instructions to access the memory components 112A to 112N as well as convert responses associated with the memory components 112A to 112N into information for the host system 120” [Bavishi ¶ 38].
With regard to claim 15, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the method of claim 9, as referenced above. Bavishi further teaches:
further comprising: adding the first process, the data of which is stored in the first area of the second memory, “Fill operations can be generated to store the data obtained from the backing store in one or more sectors of a cache line in the read-only cache and/or the write-read cache” [Bavishi ¶ 27].
to a scheduling target based on an event, and restoring the first process to the activated state. “The fill operations can be generated when a read request is received and the requested data is not found (cache miss) (event) in either read-only cache 200 or write-read cache 202” [Bavishi ¶ 45]. “In some embodiments, to further improve performance and quality of service of the memory sub-system, a priority scheduler can be used with a priority queue to determine a schedule (scheduling target) of when to execute requests and fill operations. As described above, the outstanding command queues can queue misses for read requests for data and misses for write requests for data in the caches. A priority scheduler can determine a schedule of when to execute the requests based on when the requests are received” [Bavishi ¶ 30 Examiner notes including a process in an execution schedule is considered restoring it to an activated state].
With regard to claim 16, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the electronic apparatus of claim 1, as referenced above. Bavishi further teaches:
wherein the first memory comprises a volatile memory, “In some embodiments, the read-only cache and/or the write-read cache can be preloaded with data prior to receiving memory access requests from the host system” [Bavishi ¶ 27].
and wherein the second memory comprises a nonvolatile memory. “A memory sub-system can be a storage system, such as a solid-state drive (SSD), or a hard disk drive (HDD). A memory sub-system can be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). A memory sub-system can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components” [Bavishi ¶ 2].
With regard to claim 17, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the method of claim 9, as referenced above. Bavishi further teaches:
wherein the first memory comprises a volatile memory, “In some embodiments, the read-only cache and/or the write-read cache can be preloaded with data prior to receiving memory access requests from the host system” [Bavishi ¶ 27].
and wherein the second memory comprises a nonvolatile memory. “A memory sub-system can be a storage system, such as a solid-state drive (SSD), or a hard disk drive (HDD). A memory sub-system can be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). A memory sub-system can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components” [Bavishi ¶ 2].
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Bavishi (US 2020/0278797 A1) in view of Iwabuchi (US 2017 /0153842 A1) in view of Dastidar (US 10,922,226 B1) in view of Noro (US 2017/0262390 A1) in view of Dobrev (US 2018/0165122 A1).
With regard to claim 2, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the electronic apparatus of claim 1, as referenced above. Bavishi in view of Iwabuchi in view of Dastidar in view of Noro fails to explicitly teach wherein the at least one processor, individually and/or collectively, is configured to: exclude at least one process to be switched to the inactivated state among the plurality of processes of the application loaded into the first memory from a scheduling target; and switch the excluded at least one process to the inactivated state.
However, Dobrev teaches:
wherein the at least one processor, individually and/or collectively, is configured to: exclude a process to be switched to the inactivated state among the plurality of processes of the application loaded into the first memory from a scheduling target; “In some examples, the schedule generator 242 generates the task execution schedule 238 as a version of the task list 240 in a finalized form ready for execution after determining all dependencies and after removing tasks deemed unnecessary” [Dobrev ¶ 97]. “Using automation plans as disclosed herein significantly reduces or eliminates inefficiencies of prior deployment techniques by providing more-efficient task execution schedules for deployments that are generated to exclude unnecessary tasks for target deployments, generated to execute tasks in parallel when such opportunities exist, and generated to be consistent with inter-task dependencies so that dependency errors are decreased or eliminated during deployment processes” [Dobrev ¶ 119].
and switch the excluded at least one process to the inactivated state. “The task list 240 of the illustrated example is an execution graph or timeline that lays out dependencies between tasks… The example schedule generator 242 uses the user-provided parameter values received via the user interface 142 in combination with tasks from the task list 240 to generate an example task execution schedule 238 of tasks needed to deploy the SDDC 202 and/or the virtual appliance(s) 224a-c” [Dobrev ¶ 67 Examiner notes, not including a process in the execution schedule is considered switching it to an inactivated state].
Dobrev is considered to be analogous to the claimed invention because it is in the same field of program loading. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi in view of Iwabuchi in view of Dastidar in view of Noro to incorporate the teachings of Dobrev and include that the at least one processor, individually and/or collectively, is configured to: exclude a process to be switched to the inactivated state among the plurality of processes of the application loaded into the first memory from a scheduling target; and switch the excluded at least one process to the inactivated state. Doing so would allow for a more efficient deployment technique. “Using automation plans as disclosed herein significantly reduces or eliminates inefficiencies of prior deployment techniques by providing more-efficient task execution schedules for deployments that are generated to exclude unnecessary tasks for target deployments…” [Dobrev ¶ 119].
With regard to claim 10, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the method of claim 9, as referenced above. Bavishi in view of Iwabuchi in view of Dastidar in view of Noro fails to explicitly teach further comprising excluding at least one process to be switched to the inactivated state among the plurality of processes of the application loaded into the first memory from a scheduling target, and switching the excluded process to the inactivated state.
However, Dobrev teaches:
further comprising excluding at least one process to be switched to the inactivated state among the plurality of processes of the application loaded into the first memory from a scheduling target, “In some examples, the schedule generator 242 generates the task execution schedule 238 as a version of the task list 240 in a finalized form ready for execution after determining all dependencies and after removing tasks deemed unnecessary” [Dobrev ¶ 97]. “Using automation plans as disclosed herein significantly reduces or eliminates inefficiencies of prior deployment techniques by providing more-efficient task execution schedules for deployments that are generated to exclude unnecessary tasks for target deployments, generated to execute tasks in parallel when such opportunities exist, and generated to be consistent with inter-task dependencies so that dependency errors are decreased or eliminated during deployment processes” [Dobrev ¶ 119].
and switching the excluded process to the inactivated state. “The task list 240 of the illustrated example is an execution graph or timeline that lays out dependencies between tasks… The example schedule generator 242 uses the user-provided parameter values received via the user interface 142 in combination with tasks from the task list 240 to generate an example task execution schedule 238 of tasks needed to deploy the SDDC 202 and/or the virtual appliance(s) 224a-c” [Dobrev ¶ 67 Examiner notes, not including a process in the execution schedule is considered switching it to an inactivated state].
It would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi in view of Iwabuchi in view of Dastidar in view of Noro to incorporate the teachings of Dobrev and include excluding at least one process to be switched to the inactivated state among the plurality of processes of the application loaded into the first memory from a scheduling target, and switching the excluded process to the inactivated state. Doing so would allow for a more efficient deployment technique. “Using automation plans as disclosed herein significantly reduces or eliminates inefficiencies of prior deployment techniques by providing more-efficient task execution schedules for deployments that are generated to exclude unnecessary tasks for target deployments…” [Dobrev ¶ 119].
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Bavishi (US 2020/0278797 A1) in view of Iwabuchi (US 2017/0153842 A1) in view of Dastidar (US 10,922,226 B1) in view of Noro (US 2017/0262390 A1) in view of Oishi (US 2016/0357623 A1).
With regard to claim 3, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the electronic apparatus of claim 1, as referenced above. Bavishi further teaches wherein the at least one processor, individually and/or collectively, is configured to: load the plurality of processes of the application into the first memory based on spare capacity of the first memory “These memory sub-systems can use higher performance and lower capacity media, referred to as caches, to store data that is accessed frequently (temporal locality) or data located in a memory region that has recently been accessed (spatial locality)” [Bavishi ¶ 17]. “For example, when the read-only cache 200 and/or the write-read cache 202 are full (every cache line includes at least some valid data in one or more sectors), an eviction policy such as least recently used can be used to select the cache line with data that is least recently used to evict” [Bavishi ¶ 47].
Bavishi in view of Iwabuchi in view of Dastidar in view of Noro fails to explicitly teach and average usage of the at least one processor.
However, Oishi teaches and average usage of the at least one processor. “(S27) The highest priority monitoring process 122 compares the latest CPU utilization with the maximum value registered in the CPU utilization table 114, for each process. The highest priority monitoring process 122 determines whether there is any process whose latest CPU utilization exceeds the past maximum value among the processes being executed by the CPU 101” [Oishi ¶ 104].
Oishi is considered to be analogous to the claimed invention because it is in the same field of considering the execution order of a plurality of tasks. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi in view of Iwabuchi in view of Dastidar in view of Noro to incorporate the teachings of Oishi and include average usage of the at least one processor. Doing so would allow for the system to track and mitigate processor usage which is too high. “In the case where it is presumed that the CPU 101 is in the abnormal operating state, on the other hand, the watchdog timer 102 is not initialized, but the CPU 101 is reset promptly. As a result, it is possible to appropriately adjust the time at which the watchdog timer 102 sends a reset signal” [Oishi ¶ 110].
With regard to claim 11, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the method of claim 9, as referenced above. Bavishi further teaches comprising loading the plurality of processes of the application into the first memory based on spare capacity of the first memory “These memory sub-systems can use higher performance and lower capacity media, referred to as caches, to store data that is accessed frequently (temporal locality) or data located in a memory region that has recently been accessed (spatial locality)” [Bavishi ¶ 17]. “For example, when the read-only cache 200 and/or the write-read cache 202 are full (every cache line includes at least some valid data in one or more sectors), an eviction policy such as least recently used can be used to select the cache line with data that is least recently used to evict” [Bavishi ¶ 47].
Bavishi in view of Iwabuchi in view of Dastidar in view of Noro fails to explicitly teach and average usage of the at least one processor of the electronic apparatus.
However, Oishi teaches and average usage of the at least one processor of the electronic apparatus. “(S27) The highest priority monitoring process 122 compares the latest CPU utilization with the maximum value registered in the CPU utilization table 114, for each process. The highest priority monitoring process 122 determines whether there is any process whose latest CPU utilization exceeds the past maximum value among the processes being executed by the CPU 101” [Oishi ¶ 104].
Oishi is considered to be analogous to the claimed invention because it is in the same field of considering the execution order of a plurality of tasks. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi in view of Iwabuchi in view of Dastidar in view of Noro to incorporate the teachings of Oishi and include average usage of the at least one processor of the electronic apparatus. Doing so would allow for the system to track and mitigate processor usage which is too high. “In the case where it is presumed that the CPU 101 is in the abnormal operating state, on the other hand, the watchdog timer 102 is not initialized, but the CPU 101 is reset promptly. As a result, it is possible to appropriately adjust the time at which the watchdog timer 102 sends a reset signal” [Oishi ¶ 110].
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Bavishi (US 2020/0278797 A1) in view of Iwabuchi (US 2017/0153842 A1) in view of Dastidar (US 10,922,226 B1) in view of Noro (US 2017/0262390 A1) in view of Potonniee (US 2004/0178261 A1).
With regard to claim 5, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the electronic apparatus of claim 4, as referenced above. Bavishi in view of Iwabuchi in view of Dastidar in view of Noro fails to explicitly teach wherein the at least one processor, individually and/or collectively, is configured to: identify that the preparation for executing the application has occurred based on at least one of spare capacity of the first memory, speed of the processor, or average usage of the processor.
However, Potonniee teaches wherein the at least one processor, individually and/or collectively, is configured to: identify that the preparation for executing the application has occurred based on at least one of spare capacity of the first memory, speed of the processor, or average usage of the processor. “Provision can be made that this deployment of medium priority elements is carried out only if the performance or capacities of the terminal are sufficient (step 8), or that these elements are deployed in order of priority until the available resources (for example in terms of memory capacity) of the terminal reach a predefined minimum threshold, or else, in the case of an asynchronous deployment, the number of deployments initiated in parallel is limited according to the available resources of the terminal, so as not to slow down, in a way appreciable to the user, the execution of the application in progress” [Potonniee ¶ 64].
Potonniee is considered to be analogous to the claimed invention because it is in the same field of program loading. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi in view of Iwabuchi in view of Dastidar in view of Noro to incorporate the teachings of Potonniee and include that the at least one processor, individually and/or collectively, is configured to: identify that the preparation for executing the application has occurred based on at least one of spare capacity of the first memory, speed of the processor, or average usage of the processor. Doing so would allow for the system to execute applications using limited resources while keeping track of memory capacity. “Provision can be made that this deployment of medium priority elements is carried out only if the performance or capacities of the terminal are sufficient (step 8)…” [Potonniee ¶ 64].
With regard to claim 13, Bavishi in view of Iwabuchi in view of Dastidar in view of Noro teaches the method of claim 12, as referenced above. Bavishi in view of Dastidar in view of Noro fails to explicitly teach further comprising identifying that the preparation for executing the application has occurred based on at least one of spare capacity of the first memory, speed of a processor of the electronic apparatus, or average usage of the processor.
However, Potonniee teaches further comprising identifying that the preparation for executing the application has occurred based on at least one of spare capacity of the first memory, speed of a processor of the electronic apparatus, or average usage of the processor. “Provision can be made that this deployment of medium priority elements is carried out only if the performance or capacities of the terminal are sufficient (step 8), or that these elements are deployed in order of priority until the available resources (for example in terms of memory capacity) of the terminal reach a predefined minimum threshold, or else, in the case of an asynchronous deployment, the number of deployments initiated in parallel is limited according to the available resources of the terminal, so as not to slow down, in a way appreciable to the user, the execution of the application in progress” [Potonniee ¶ 64].
Potonniee is considered to be analogous to the claimed invention because it is in the same field of program loading. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bavishi in view of Iwabuchi in view of Dastidar in view of Noro to incorporate the teachings of Potonniee and include identifying that the preparation for executing the application has occurred based on at least one of spare capacity of the first memory, speed of the processor, or average usage of a processor of the electronic apparatus. Doing so would allow for the system to execute applications using limited resources while keeping track of memory capacity. “Provision can be made that this deployment of medium priority elements is carried out only if the performance or capacities of the terminal are sufficient (step 8)…” [Potonniee ¶ 64].
Response to Arguments
Applicant's arguments filed 12/18/25 have been fully considered but they are not persuasive. Applicant argues in substance:
I. In the rejection of claim 1, the Office Action relies on the memory components 112A to 112N (see Fig. 1 of Bavishi) as corresponding to the claimed second memory. However, Bavishi fails to disclose storing data of processes as recited in claim 1. For example, the Office Action relies on operations related to the evict queue 218 of Bavishi for storing data of the process switched over to the inactivated state (see page 11 of the Office Action). Similarly, the Office Action relied on the caching component 113 and the evict queue 218 and other queues in the caching component 113 of Bavishi in the rejection of claim 3 (see pages 23 and 24). However, the operations related to the evict queue 218 in Bavishi do not include: "identify a first process among the plurality of processes that is in the inactivated state and store data of the first process in the first area of the second memory by the sequential access method, identify a second process among the plurality of processes not in the inactivated state and store data of the second process in the second area of the second memory by the random access method, and based on an event that the first process stored in the first area of the second memory is restored from the inactivated state to an activated state, load the data of the first process stored in the first area into the first memory."
The other applied references fail to overcome at least these deficiencies of Bavishi because they fail to disclose storing data of processes in the first memory and/or the second memory, as recited in claim 1.
At least for these reasons, Bavishi, Dastidar and Noro, alone or in combination, fail to disclose the combination of features recited in claim 1.
a) Examiner respectfully disagrees. As detailed in the rejection above, Bavishi teaches storing data of processes: “At operation 610, the processing device receives a request to read data stored at a memory sub-system. The request to read data can be sent from an application executing on the host system” [Bavishi ¶ 68]. Bavishi further teaches identify a first process among the plurality of processes that is in the inactivated state [Bavishi ¶ 46] and store data of the first process in the second memory by the sequential access method [Bavishi ¶ 51].
Further, the limitations of: “based on an event that the first process stored in the first area of the second memory is restored from the inactivated state to an activated state, load the data of the first process stored in the first area into the first memory” is taught by Noro [Noro ¶ 64, 70].
Applicant’s further arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
II. The Section 101 rejection is also respectfully traversed. As explained above in connection with the art rejection, the subject matter of claim 1 is NOT conventional, and is NOT generic, as it is not disclosed or suggested by the cited art. And the claimed subject matter is certainly not performed in the human mind. For example, operations including "identify a first process among the plurality of processes that is in the inactivated state and store data of the first process in the first area of the second memory by the sequential access method,""identify a second process among the plurality of processes not in the inactivated state and store data of the second process in the second area of the second memory by the random access method," and/or "based on an event that the first process stored in the first area of the second memory is restored from the inactivated state to an activated state, load the data of the first process stored in the first area into the first memory" cannot be performed in the human mind, at least because they relate to storing specific data in specific of memory.
The claimed subject matter is tied to an electronic apparatus including a first memory, a second memory, wherein the second memory comprises a first area configured to store and retrieve data using sequential access method and a second area configured to store and retrieve data using random access method, and at least one processor comprising processing circuitry. Furthermore, the claims are integrated into a practical application at least because they provide a specific improvements over prior systems. For example, the claimed features provide a technical improvement over the prior art because they provide for using first and second memory more efficiently, executing an application more quickly, improves access speed of data, and/or preventing unintentional swap-in (see e.g., paragraphs [0007], [0025], [0047], [0051] and [0097]- [0103]).
a) Examiner respectfully disagrees. As is detailed in the rejection above, the recited identifying is considered an abstract idea because it can be preformed in the human mind. A person can identify a process or a plurality of processes. The data storage and loading are additional elements of the claim which amount to insignificant extra solution activity. Further the “electronic apparatus including a first memory, a second memory, wherein the second memory comprises a first area configured to store and retrieve data using sequential access method and a second area configured to store and retrieve data using random access method, and at least one processor comprising processing circuitry” are also considered additional claim elements which amount to generic computing components and technological environment/ field of use.
In response to applicant's argument that the claims provide specific improvements of the invention, it is noted that the features upon which applicant relies (i.e., “provide for using first and second memory more efficiently, executing an application more quickly, improves access speed of data, and/or preventing unintentional swap-in”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). It is not clear from the current claim language that the improvements Applicant argues are implemented. The arguments have been considered but were not found to be persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
When responding to this Office Action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 CFR 1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARI F RIGGINS whose telephone number is (571)272-2772. The examiner can normally be reached Monday-Friday 7:00AM-4:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bradley Teets can be reached at (571) 272-3338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.F.R./Examiner, Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197
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