Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 02/19/26
(b) Priority date: 06/24/22
(c) Invention: EDA tool to convert FPGA into ASIC.
Rejoinder
Pursuant to the procedures set forth in MPEP § 821.04(a), the restriction requirement as set forth in the Office action mailed (dated below), is hereby withdrawn and claim/claims (listed below) hereby rejoined and fully examined for patentability under 37 CFR 1.104
Withdrawn office action date: 02/12/26.
Rejoined claim date: 02/19/26.
Final claim list after rejoined: 1-20.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1-20, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record “Madurawe” <US 20070152708 A1>.(As to claim 1, 10, 16, Madurawe discloses):
1. (original) A computer system for protecting a circuit design for an application specific integrated circuit, the computer system comprising [0003: “design conversion from a field programmable device (FPGA) to different density metal programmable application specific devices (MPGA)”]:
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a logic circuit replacement tool for generating a transformed circuit design for the application specific integrated circuit by replacing first logic circuitry in a first module [0007: “conversion from an FPGA implementation to an MPGA or ASIC implementation typically requires a complete redesign””] [Fig. 19B-D further depicts conversion of FPGA into ASIC (19D). It provides significant area benefit while getting the same desired functionality from reduced set of circuitries]
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in at least a portion of the circuit design with a first configurable circuit that performs a first logic function of the first logic circuitry when a first bitstream stored in first storage circuits in the first configurable circuit configures the first configurable circuit [Fig. 16 and 17 depicts how a portion of circuit design converts into desired configuration using stored bit stream. Fig. 16 depicts how a single bit of a bit-stream (logic 1 or logic 0) connects or disconnects O1 and I1. Fig. 17 depicts the same concept for multiple bit stream to build multiple configurable connections],
wherein the transformed circuit design comprises the first configurable circuit in the first module [Fig. 18D and Fig. 19D are ASIC equivalent transformed circuit comprises the first configuration in the first module coming from FPGA equivalent circuit 18A and 19A].
(As to claim 2, Madurawe discloses):
2. (original) The computer system of claim 1, wherein the first configurable circuit comprises a lookup-table circuit [079: “these SRAM cells are embedded in truth table logic (also called Look-Up-Table) based architectures.”].
(As to claim 3, 11, 17, Madurawe discloses):
3. (original) The computer system of claim 1, wherein the logic circuit replacement tool is configured to identify a second module of second logic circuitry for replacement in the circuit design [Fig. 18A, tool identified second module (121d4) is ASIC replacement of first FPGA design (121b2)],
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wherein the logic circuit replacement tool generates the transformed circuit design by replacing the second logic circuitry in the second module with a second configurable circuit that performs a second logic function of the second logic circuitry when a second bitstream stored in second storage circuits in the second configurable circuit configures the second configurable circuit [0087: “FIG. 18A shows a first embodiment of an FPGA constructed as a regular 2D FPGA or a modular 3D FPGA. It may have configuration circuits in the same module layers as the transistors as in conventional FPGAs. It may have configuration circuits in a second module layer positioned above a first module layer that comprises logic circuits as presented in FIG. 1”],
and wherein the transformed circuit design comprises the second configurable circuit in the second module [0087: “It may have configuration circuits in a second module”].
(As to claim 4, 19, Madurawe discloses):
4. (original) The computer system of claim 3, wherein the first module and the second module are arranged in a hierarchy [Fig. 19A, module 1921, 1931 maintains a hierarchy (1931 under 1921)],
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and wherein the second module is a sub- module of the first module [Fig. 19 A; note: second module (1931, the inner block) is a sub-set of the first module (1921, the outer block)].
(As to claim 5, 12, 18, Madurawe discloses):
5. (original) The computer system of claim 3, wherein the logic circuit replacement tool is configured to provide a multiplexer circuit in the transformed circuit design that is configurable to select an output signal of only one of the first configurable circuit or the second configurable circuit for transmission to a third module in the transformed circuit design [Fig. 12, the multiplexer data inputs are S0..S15 and the final data output is F, configurable circuits A-B and C-D. The various combination of control inputs A-B helps generate the 2nd level and C-D 3rd level transformed design using the multiplexer (detail in Fig. 17)].
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(As to claim 6, 14, 20, Madurawe discloses):
6. (original) The computer system of claim 3, wherein the first configurable circuit comprises a first lookup table circuit, and wherein the second configurable circuit comprises a second lookup table circuit that is a different size than the first lookup table circuit [Fig. 12, refer to lookup table under control input A-B (2nd), and C-D (3rd) having different sizes (4 in 2nd, 1 in 3rd].
(As to claim 7, 15, Madurawe discloses):
7. (original) The computer system of claim 1, wherein the logic circuit replacement tool generates the transformed circuit design by replacing the first configurable circuit with second configurable circuits that perform the first logic function of the first logic circuitry when a second bitstream is stored in second storage circuits in the second configurable circuits and used to configure the second configurable circuits, and wherein the second configurable circuits combined are smaller than the first configurable circuit [Refer to claim 6 rejection. Note that, the configurable bitstream helps store and configure the values of control inputs (A..D) ].
(As to claim 8, 13, Madurawe discloses):
8. (original) The computer system of claim 1, wherein the first configurable circuit is configurable to be prevented from being functional by loading all zero values into the first storage circuits [Fig. 12. Note: Logically, the configurable bits A=0, B=0 in the first block will prevent that block to be functional].
(As to claim 9, Madurawe discloses):
9. (original) The computer system of claim 1, wherein the first storage circuits are register circuits responsive to at least one clock signal [Fig. 14, notice the storage circuit (SRAM) in pass through register circuits enabled (write enable) with clock signal].
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Conclusion
The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851
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