, DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 -13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the second master controller" in line 2. There is insufficient antecedent basis for this limitation in the claim.
It appears that claim 10 should depend from claim 9, which introduces the second master controller.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 10-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshio (US 2005/0242779).
As to claims 1 and 8, Yoshio discloses in figure 1, a protection circuit of a battery module [see figure 1, element 1A] , including:
a master microcontroller [microcontroller (2)] :
a slave microcontroller [element 36] connected to the master microcontroller:
a charging path switch [switch SW1];
a discharging path switch [switch SW2]: and
a switch controller [controller (31)] connected to the master microcontroller, the slave microcontroller [element 36], the charging path switch, and the discharging path switch: wherein when the master microcontroller periodically sends a pulse signal [see ¶0052] to the slave microcontroller. the master microcontroller enables the switch controller, and then the switch controller enabled is used to control the turning on or off of the charging path switch or the discharging path switch: if the slave microcontroller doesn't receive the pulse signal, the slave microcontroller disables the switch controller [see ¶0052].
As to claim 2, Yoshio discloses in figures 1-2 and 4, wherein when the master microcontroller is in a normal state, the master microcontroller periodically sends the pulse signal to the slave microcontroller, and enables the switch controller [see ¶0052]; when the master microcontroller is in an abnormal state, the master microcontroller is unable to send the pulse signal to the slave microcontroller, the slave microcontroller disables the switch controller [see ¶0030, ¶0033, ¶0048 and ¶0052 and also see figures 2 and 4, the microcontroller outputs clock signal for the watchdogs (36) when the clock Stops the IC1 detected and Watchdog Fault signal makes the SW1 and SW2 in off states].
As to claim 3 , Yoshio discloses in figures 1 and 9, wherein the battery module further includes a power management system: when the master microcontroller is in the abnormal state, the power management system will perform a system restart procedure to the battery module; if the master microcontroller is able to resume from the abnormal state to the normal state after the system restart procedure has performed, the master microcontroller periodically sends the pulse signal to the slave microcontroller again, and enables the switch controller again [see ¶0004, ¶0075; noted that the logic circuit (37) sends reset signal to the microcomputer (2) and the microcomputer enters in reset mode and after reset mode the Master controller (micro controller (2) ) resumes normal operations and sending control clock signal to the watch dog (3); see figure 9].
As to claim 4, Yoshio discloses in figures 1-9, if the master microcontroller is in the abnormal state, the switch controller is always latched in a disabled state by the slave microcontroller before the power management system has not yet performed the system restart procedure to the battery module [the slave controller (watchdog (36)) outputs signals based on master controller clock signal to turn on and off the switching devices; see ¶004 and ¶0075].
As to claim 5 , Yoshio discloses in figures 1-9, wherein the battery module includes a battery unit having a plurality of battery cells [battery cells Cell 1-Cell 3], the protection circuit further includes a positive electrode line and a negative electrode line [positive terminals and negative terminals of the battery cells are connected with positive and negative electrical lines] ; the positive electrode line is connected between an inner positive electrode of the battery unit and an outer positive electrode of the battery module [see figure 1, the positive battery cell terminal is connected to the Pack + terminal], the negative electrode line is connected between an inner negative electrode of the battery unit and an outer negative electrode of the battery module [see figure 1, the negative battery cells terminal is connected to the PACK -terminal], and the charging path switch [SW1] and the discharging path switch [SW2] are configured on the positive electrode line or the negative electrode line [see figure 1].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and14 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshio in view of Lee et al. (US 2008/0129247), hereinafter Lee.
As to claim 9, Yoshio discloses in figures 1-9, f microcontroller connected to the master microcontroller; a discharging path switch; and the microcontroller, the second slave microcontroller, and the discharging path switch; wherein when the master microcontroller periodically sends a pulse signal to the slave microcontroller, the second master microcontroller enables the second switch controller, and then the second switch controller enabled is used to control the turning on or off of the discharging path switch; if the second slave microcontroller doesn't receive the second pulse signal, the second slave microcontroller disables the second switch controller [noted that Yoshio discloses a master microcontroller (2) with slave controller (36) and the master microcontroller sends pulse signals for slave master; see ¶0052 and 075].
Yoshio does not disclose explicitly, a second master microcontroller and a second slave microcontroller.
Lee discloses in figure 3, a second master microcontroller [master module in battery pack (7)] ; a second slave [slave module in battery pack 7] microcontroller connected to the second master microcontroller; a discharging path switch [Sub switch]; and a second switch controller connected to the second master microcontroller[noted that each battery pack contains SUB SW, master module and slave module].
It would have been obvious to a person having ordinary skill in the art at the time the invention was made to use plurality of master microcontroller and slave controllers in Yoshio’s apparatus as taught by Lee in order to increase accuracy of the battery cells monitoring.
As to claim 14, Yoshio discloses in figures 1-9, wherein the battery module includes a battery unit having a plurality of battery cells [battery cells Cell 1-Cell 3], the protection circuit further includes a positive electrode line and a negative electrode line [positive terminals and negative terminals of the battery cells are connected with positive and negative electrical lines] ; the positive electrode line is connected between an inner positive electrode of the battery unit and an outer positive electrode of the battery module [see figure 1, the positive battery cell terminal is connected to the Pack + terminal], the negative electrode line is connected between an inner negative electrode of the battery unit and an outer negative electrode of the battery module [see figure 1, the negative battery cells terminal is connected to the PACK -terminal], and the charging path switch [SW1] and the discharging path switch [SW2] are configured on the positive electrode line or the negative electrode line [see figure 1].
Claims 10 -13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshio in view of Lee, and in view of Kim et al. (US 2011/0305926), hereinafter Kim.
As to claim 10, neither Yoshio nor Lee discloses, wherein when the first master microcontroller is in an abnormal state, the first master microcontroller is unable to send the first pulse signal to the first slave microcontroller, the first slave microcontroller disables the first switch controller; when the second master microcontroller is in an abnormal state, the second master microcontroller is unable to send the second pulse signal to the second slave microcontroller, the second slave microcontroller disables the second switch controller.
Kim discloses in figure 1, wherein when the first master microcontroller [ the micro controller element 130 is considered as a master controller] is in an abnormal state, the first master microcontroller is unable to send the first pulse signal to the first slave microcontroller [the controller (120) considered as slave microcontroller and during abnormal state the master controller (130) unable to send signale to slave controller (120) which detects abnormality in the master controller (130)] , the first slave microcontroller disables the first switch controller; when the second master microcontroller is in an abnormal state, the second master microcontroller is unable to send the second pulse signal to the second slave microcontroller, the second slave microcontroller disables the second switch controller [the switch controller (124) of the slave controller (120) sends signal to turn off the charging and discharging switches ; see ¶0030-0034].
It would have been obvious to a person having ordinary skill in the art at the time the invention was made to use slave controller of Yoshio to disable charging and discharging switches when the master controller is in fault to protect the battery from excessive currents which can dame or destroy the battery.
Noted that Claim 10 is considered as being dependent upon claim 9 (see claim objection above)
As to claim 11, Yoshio discloses in figures 1 and 9, wherein the battery module further includes a power management system: when the master microcontroller is in the abnormal state, the power management system will perform a system restart procedure to the battery module; if the master microcontroller is able to resume from the abnormal state to the normal state after the system restart procedure has performed, the master microcontroller periodically sends the pulse signal to the slave microcontroller again, and enables the switch controller again [see ¶0004, ¶0075; noted that the logic circuit (37) sends reset signal to the microcomputer (2) and the microcomputer enters in reset mode and after reset mode the Master controller (micro controller (2) ) resumes normal operations and sending control clock signal to the watch dog (3); see figure 9].
As to claim 12 , Yoshio discloses in figures 1-9, if the first master microcontroller is in the abnormal state, the switch controller is always latched in a disabled state by the first slave microcontroller before the power management system has not yet performed the system restart procedure to the battery module [the slave controller (watchdog (36)) outputs signals based on master controller clock signal to turn on and off the switching devices; see ¶004 and ¶0075 and Lee discloses having plurality of slave and master controllers].
As to claim 13, Yoshio discloses in figures 1-9, if the second master microcontroller is in the abnormal state, the switch controller is always latched in a disabled state by the second slave microcontroller before the power management system has not yet performed the system restart procedure to the battery module [the slave controller (watchdog (36)) outputs signals based on master controller clock signal to turn on and off the switching devices; see ¶004 and ¶0075 noted that Lee discloses to use additional master and slave controllers].
Allowable Subject Matter
Claims 6-7 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
For claim 6; primarily, the prior art of record does not disclose or suggest in the claimed combination: the second positive electrode line is connected between the inner positive electrode of the battery unit and a second outer positive electrode of the battery module, the negative electrode line is connected between an inner negative electrode of the battery unit and an outer negative electrode of the battery module, the charging path switch is configured on the first positive electrode line, and the discharging path switch is configured on the second positive electrode line.
For claim 7:primarily, the prior art of record does not disclose or suggest in the claimed combination: the second negative electrode line is connected between the inner negative electrode of the battery unit and a second outer negative electrode of the battery module, the charging path switch is configured on the first negative electrode line, and the discharging path switch is configured on the second negative electrode line.
For claim 15:primarily, the prior art of record does not disclose or suggest in the claimed combination: the second positive electrode line is connected between the inner positive electrode of the battery unit and a second outer positive electrode of the battery module, the negative electrode line is connected between an inner negative electrode of the battery unit and an outer negative electrode of the battery module, the charging path switch is configured on the first positive electrode line, and the discharging path switch is configured on the second positive electrode line.
For claim 16:primarily, the prior art of record does not disclose or suggest in the claimed combination: the second negative electrode line is connected between the inner negative electrode of the battery unit and a second outer negative electrode of the battery module, the charging path switch is configured on the first negative electrode line, and the discharging path switch is configured on the second negative electrode line.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL BERHANU whose telephone number is (571)272-8430. The examiner can normally be reached M_F.
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/SAMUEL BERHANU/Primary Examiner, Art Unit 2859