CTFR 18/125,552 CTFR 100706 DETAILED ACTION This Office Action is in response to communications filed on January 30 th , 2026 for Application No. 18/125,552, in which claims 1-13 are presented for examination. The amendments filed on January 30 th , 2026 have been entered, where claims 1, 3-5, 9, and 11 are amended. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 6-11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Nishi et al. (hereinafter Nishi) (Patent Pub. No. US 2021/0279559 A1) in view of Rose et al. (hereinafter Rose) (Patent Pub. No. US 2013/0311413 A1), Noack et al. (hereinafter Noack) ( “Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS” ), and Chen et al. (hereinafter Chen) ( “On the Design of a Low Power Compact Spiking Neuron Cell Based on Charge-Coupled Synapses” ). Regarding Claim 1 , Nishi teaches a spike neural network circuit comprising ( Fig. 5 and Para. [0058], “FIG. 5 is a diagram illustrating an example of the configuration of a spiking neural network device 100 according to the first embodiment. As illustrated in FIG. 5, the spiking neural network device 100 of the present embodiment includes a synaptic element 120, a neuron circuit 110, a synaptic potentiator 140, a synaptic depressor 150, and a determinator 160” ) : a weight storage configured to receive an input spike signal and to output data based on a weight ( Fig. 5 , where the “SYNAPTIC ELEMENT 120” , which is a weight storage because weights are stored in it, see subcomponent “WEIGHT STORAGE 121” , receives the “SPIKE SIGNAL” and outputs “SYNAPTIC SIGNAL” data; Para. [0059], “The synaptic element 120 has weight storage 121 for storing a variable weight. The synaptic element 120 receives a spike signal (first spike signal). When receiving the spike signal, the synaptic element 120 transfers, to the neuron circuit 110, a synaptic signal whose intensity is adjusted according to the weight held by the weight storage 121” , where the outputted “synaptic signal” data is “adjusted according to the weight” ) ; . . . a voltage-to-current conversion circuit configured to receive the [output data comprising] . . . a current, and to integrate the current to generate a membrane voltage ( Fig. 7 , where a conversion circuit, “INTEGRATION CIRCUIT 111” , receives the “SYNAPTIC CURRENT” output data, see Para. [0071], “The synaptic current corresponds to a synaptic signal and is inputted to the neuron circuit 110” , in order to generate the membrane voltage, “MEMBRANE POTENTIAL” ; Para. [0072], “The integration circuit 111 integrates the inputted synaptic current to convert the same to a voltage called a membrane potential” ; where, the “INTEGRATION CIRCUIT 111” is within the broadest reasonable interpretation of a to-current conversion circuit because the conversion circuit must perform a conversion, “convert the same” , to generate a “voltage” output) ; and a neuron circuit configured to receive the membrane voltage and a threshold voltage ( Fig. 7 , where the “NEURON CIRCUIT 110” internally receives the “MEMBRANE POTENTIAL” from its “INTEGRATION CIRCUIT 111” subcomponent; Para. [0060], “the neuron circuit 110 integrates the inputted synaptic signal and fires when the integrated value exceeds a predetermined threshold” , where “predetermined” demonstrates the “threshold” was set at a prior point and, therefore, accessing the “threshold” , either from an external component or internally from memory, is within the broadest reasonable interpretation of configured to receive; Fig. 7 , alternatively, “THRESHOLD COMPARATOR CIRCUIT 112” can itself be considered the neuron circuit because it is a “CIRCUIT” that is a functional component of a “NEURON” ; Para. [0073], “The threshold comparator circuit 112 compares the membrane potential outputted from the integration circuit 111 with the predetermined threshold” ) and to generate an output spike signal based on the received membrane voltage and the received threshold voltage ( Para. [0073], “The spike generation circuit 113 generates and outputs a spike voltage when the membrane potential exceeds the threshold. The generation of such a spike voltage in the neuron circuit 110 is referred to as firing” , where “spike voltage” is within the broadest reasonable interpretation of an output spike signal, see generally Para. [0036], “spike voltage signals” ; Fig. 7 , where the “SPIKE VOLTAGE” is the output of the “NEURON CIRCUIT 110” , and more specifically, subcomponent “THRESHOLD COMPARATOR CIRCUIT 112” , as indicated by the arrow symbol) . Nishi does not explicitly disclose . . . a charge sharing synaptic circuit configured to generate a synaptic voltage based on the output data, the charge sharing synaptic circuit comprising: a first capacitor including a plurality of internal capacitors having different capacitances, the charge sharing synaptic circuit being configured to selectively connect each internal capacitor to one of a plurality of voltages based on a corresponding bit of the output data; and a second capacitor, the charge sharing synaptic circuit being configured to share charge between the plurality of internal capacitors and the second capacitor to generate the synaptic voltage; a switched capacitor circuit configured to naturally discharge the generated synaptic voltage; . . . synaptic voltage, to convert the synaptic voltage into . . . However, Rose teaches . . . [an artificial synapse for neuromorphic hardware systems, comprising] ( Abstract, “a trainable artificial synapse for neuromorphic hardware systems” ) a charge sharing synaptic circuit configured to generate a synaptic voltage based on the output data, the charge sharing synaptic circuit comprising ( Para. [0029], “The synaptic circuit shown in FIG. 1 achieves . . . tasks through charge sharing” , where the “charge sharing” “synaptic circuit” generates a synaptic voltage, “increase the voltage Vc 90” , based on current, “charge . . . pass[ing] through” the circuit, that is output to the circuit, see Para. [0030], “The charge is then allowed to pass through the driving NMOS transistor WN 80 to increase the voltage V c 90 across the summation capacitance 100 . . . Thus, the amount of charge and the associated voltage V c 90 is weighted according to the total memristance values M 20 at all inputs” ; see also Para. [0035], “Referring to FIG. 4 provides an example of how multiple synaptic circuits 130 can be connected and then buffered to produce an amplified version of the weighted sum of the inputs. As can be seen in FIG. 4, the circuit consists of n synaptic inputs all driving node V.sub.c 90” and Fig. 4 , where the “multiple synaptic circuits 130” and “summation capacitance 100” , once “connected” , can reasonably be collectively referred to as the charge sharing synaptic circuit) : . . . a plurality of internal . . . [components] , the charge sharing synaptic circuit being configured to selectively connect each . . . [component] to one of a plurality of voltages . . . ( Para. [0035], “Referring to FIG. 4 provides an example of how multiple synaptic circuits 130 can be connected and then buffered to produce an amplified version of the weighted sum of the inputs. As can be seen in FIG. 4, the circuit consists of n synaptic inputs all driving node V.sub.c 90” and Fig. 4 , where the “multiple synaptic circuits 130” are a plurality of internal components that are selectively “connected” to one of a plurality of voltages, “V in1 ” through “V in(n) ” ) ; a . . . capacitor, the charge sharing synaptic circuit being configured to share charge between the plurality of internal . . . [components] and the . . . capacitor to generate the synaptic voltage ( Para. [0029], “The synaptic circuit shown in FIG. 1 achieves . . . tasks through charge sharing” , where the “charge sharing” “synaptic circuit” generates a synaptic voltage, “increase the voltage Vc 90” , based on current, “charge . . . pass[ing] through” the circuit, that is output to the circuit, see Para. [0030], “The charge is then allowed to pass through the driving NMOS transistor WN 80 to increase the voltage V c 90 across the summation capacitance 100 . . . Thus, the amount of charge and the associated voltage V c 90 is weighted according to the total memristance values M 20 at all inputs” , where the “voltage” is generator between the capacitor, “summation capacitance 100” , and the internal components of the “synaptic circuit” , see Para. [0010], “The invention relies on charge sharing at the output to enable the summation of signals from multiple synapses” ) . Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the spike neural network, wherein a weight storage generates a weighted synaptic current as output of Nishi with the artificial synapse for neuromorphic hardware systems, wherein a charge sharing synaptic circuit generates a synaptic voltage based on a weighted synaptic current, wherein the charge sharing synaptic circuit comprises internal components selectively connected to voltages and the charge sharing between the components and a capacitor is used to generate the synaptic voltage of Rose in order to generate a summation of voltages from multiple synaptic components ( Rose, Para. [0029], “The CMOS circuitry within the overall neural circuits must perform two major tasks: (1) amplify the voltage swing at voltage node V n (.DELTA.V n ) 50 and (2) provide an output that can be summed together with the outputs of other synapses. The synaptic circuit shown in FIG. 1 achieves the above mentioned tasks through charge sharing” ; Rose, Abstract, “The invention relies on charge sharing at the output to enable the summation of signals from multiple synapses at the input node of a neuron circuit, implemented using a CMOS amplifier circuit” ), which will contribute to a more energy efficient system (compare Nishi, Para. [0034], “implementing the artificial intelligence by GPUs is highly energy intensive . . . which will be a constraint on learning at the edge” with Rose, Para. [0037], “the energy consumption of the circuit is very low, on the order of femtojoules (fj) or 10 -2 joules” ). Additionally, Noack teaches [a neuromorphic system composed of circuits, comprising] ( Pg. 1, Abstract, “we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits” ) . . . . . . [performing actions] based on a corresponding bit of the output data . . . ( Pg. 8, Col. 1, Para. 2, “The scaling of the PSC is done via binary weighted capacitors” and Pg. 4, Col. 2, Para. 2, “With the period of the matrix column cycle, the resulting exponentially decaying PSC voltage is sampled on the 4-bit binary-weighted capacitor C W and transferred to the neuron circuit” ) a switched capacitor circuit configured to naturally discharge the generated synaptic voltage ( Pg. 3, Col. 2, Para. 4, “Between incoming spikes an exponential decay of V U , V R and V PSC is performed by SC leaky integrator circuits” , where “SC” are “switched capacitor (SC) circuits” , see Pg. 1, Abstract, “we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits” , and where “preform[ing]” “exponential decay of . . . V psc ” is within the broadest reasonable interpretation of naturally discharging the generated synaptic voltage); [and] . . . [a] voltage [receiving neuron circuit configured to receive the] synaptic voltage ( Pg. 4, Col. 1, Para. 2, “With the period of the matrix column cycle, the resulting exponentially decaying PSC voltage is sampled on the 4-bit binary-weighted capacitor CW and transferred to the neuron circuit” , where the “neuron circuit” receives the “PSC voltage” to convert it into a current, “charge” received over time, see Pg. 8, Col. 1, Para. 2, “This binary out put is used to scale the PSC generated by the presynaptic adaptation circuit (see “Weight Scaling and Charge Transmission” in Figure 3). Therefore, each synapse has two 4-bit weights for LTP and LTD stored in a RAM (see Figure 1), which is chosen accordingly to the synapse state and transmitted to the weight scaling circuit. The scaling of the PSC is done via binary weighted capacitors, transferring charge to the neuron circuit” ), to convert the synaptic voltage into [a current] . . . . Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the spike neural network, wherein a synaptic current is output from a weight storage; the synaptic current is converted into a synaptic voltage by a charge sharing synaptic circuit; and the output, which is now the synaptic voltage, is transmitted to a neuron circuit for conversion processes that generate a membrane voltage of Nishi in view of Rose with the neuromorphic system composed of circuits, comprising a switched capacitor circuit configured to naturally discharge the generated synaptic voltage and a neuron circuit that receives the synaptic voltage, to perform actions based on bits of output data and convert the synaptic voltage into a current, of Noack in order to achieve stable and fast neural network functionality by implementing controlled leakage before transmission of the synaptic voltage to the neuron circuit ( Noack, Pg. 1, Abstract, “when running neural networks on a neuromorphic IC . . . The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds” ; see also Noack, Pg. 4, Col. 2, Para. 1, “Especially the concept of isolating capacitors by low leakage switches makes it possible to reach time constants up to 600 ms” ), which contributes to energy efficiency (compare Nishi, Para. [0034], “implementing the artificial intelligence by GPUs is highly energy intensive . . . which will be a constraint on learning at the edge” with Noack, Pg. 4, col. 2, Para. 1, “our solution is much more area and power efficient and satisfies our leakage constraints” see also Noack, Pg. 4, Col. 2, Para. 2, “With the period of the matrix column cycle, the resulting exponentially decaying PSC voltage is sampled on the 4-bit binary-weighted capacitor C W and transferred to the neuron circuit” , where the above-described advantages are, in part, achieved through use of the “the 4-bit binary-weighted capacitor C W ” before being “transferred to the neuron circuit” ). Furthermore, Chen teaches . . . [a synaptic circuit, comprising] ( Pg. 1511, Col. 1, Abstract, “A charge-coupled silicon synapse with a floating diffusion output is proposed as the basis for a new electronic, spiking neuron cell. The synapse is formed by a two-stage charge transfer device” , where a “charge-coupled silicon synapse . . . formed by a two-stage charge transfer device” is within the broadest reasonable interpretation of a synaptic circuit; see also Pg. 1517, Col. 1, Para. 2, “We have proposed a charge-coupled silicon synapse exhibiting spiking behaviour for biological-scale SNNs . . . If we restrict the area occupied by the neuron cells to 80% of the total chip area (assumed to be 1cm2), then a simple calculation predicts that 200 thousand standard neuron cells can be fabricated using a single layer submicron process, as compared to a few thousand with existing techniques” ) : a first capacitor including [a plurality of internal] capacitors having different capacitances , . . . [the synaptic circuit being configured to selectively connect each] internal capacitor [to one of a plurality of voltages] . . . ( Pg. 1512, Col. 1, Fig. 1 and Pg. 1512, Col. 1, Para. 1, “The silicon synapse shown in Fig. 1(b) comprises a floating gate integrated into a two-stage charge-coupled device with a heavily doped output terminal. The two MOS capacitors are in close proximity the first having charge storage capability and the second serving to ’clock’ its reading” , where the “first” of the “two MOS capacitors” is a first capacitor, which includes a plurality of internal capacitors, the “input gate” hardware associated with each of “C 0 ” and “C 1 , C 2 , ...,C n ” , which are selectively connected to one of a plurality of voltages, “ V 1 , V 2 , ..., V n ”, see Pg. 1514, Col. 2, Fig. 3 ; Pg. 1514, Col. 1, Para. 4, “The input voltages and coupling coefficients are illustrated in Fig. 3(b), where V 1 , V 2 , ..., V n are the input voltages; C 1 , C 2 , ...,C n are the coupling capacitance between the floating gate and each input gates; C 0 is the coefficient between the floating gate and the substrate; VF is the floating gate voltage” ; and Pg. 1512, Col. 2, Para. 3, “The deeper surface potential well formed in the silicon under the second gate, causes the charge packet to start transferring from the first capacitor to the second and subsequently to the output terminal” , and which are within the broadest reasonable interpretation of having different capacitances because they are assigned distinct coupling capacitances with different variables, “C 1 , C 2 , ...,C n are the coupling capacitance . . . C 0 is the coefficient between the floating gate and the substrate” , and are thus different in form and nature, which are assigned values as “a function” of their associated hardware, see Pg. 1513, Col. 2, Para. 4, “The coupling capacitance C 1 is a function of the length of overlapping between the terminal and the second gate L ov ” , and are thus different in quality) ; [and a] second [capacitor] , . . . [the synaptic circuit being configured to perform actions between the plurality of internal] capacitors [and the] second [capacitor] . . . ( Pg. 1512, Col. 1, Fig. 1 and Pg. 1512, Col. 1, Para. 1, “The silicon synapse shown in Fig. 1(b) comprises a floating gate integrated into a two-stage charge-coupled device with a heavily doped output terminal. The two MOS capacitors are in close proximity the first having charge storage capability and the second serving to ’clock’ its reading” , where the “second” of the “two MOS capacitors” is the second capacitor, which performs actions between the “first” capacitor, which as discussed above includes the plurality of internal capacitors, see Pg. 1512, Col. 1, Para. 1, “The second MOS capacitor is controlled by the presynaptic spike V i which releases the weighted charge packet Q w causing it to be dumped onto the output, floating diffusion. In reality the weights will be stored on the floating gate of the first capacitor as electrons so the charge packet will be formed of holes” ) . Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the charge sharing synaptic circuit configured to generate a synaptic voltage based on bits of output data, which comprises a plurality of internal components selectively connected to a plurality of voltages and a capacitor, wherein the charge sharing is performed between the plurality of components and the capacitor of Nishi in view of Rose and Noack with the synaptic circuit, comprising a first capacitor, which includes a plurality of internal capacitors with different capacitances that are selectively connected to one of a plurality of voltages, and a second capacitor, which is used to perform actions between the internal capacitors of Chen in order to implement the charge sharing functionality of the synaptic circuit ( Rose, Para. [0029], “The synaptic circuit shown in FIG. 1 achieves . . . tasks through charge sharing” ; Rose, Para. [0030], “The charge is then allowed to pass through the driving NMOS transistor WN 80 to increase the voltage V c 90 across the summation capacitance 100 . . . Thus, the amount of charge and the associated voltage V c 90 is weighted according to the total memristance values M 20 at all inputs” ) using customizable internal capacitors to control voltage output, which precludes the need for additional circuitry and reduces power consumption ( Chen, Pg. 1513, Col. 2, Para. 2, “The output signal from the synapse is detected at the floating diffusion structure as follows. Referring to Fig. 2, we exploit the capacitor divider effect of the series combination of the overlap capacitance, C1 and the floating diffusion, CFN, such that a positive potential is induced on the floating diffusion, by the fast rise time pulse at the second electrode. Note that the output/substrate junction is driven into reverse bias and this is also a non-equilibrium, dynamic condition . . . These capacitances can be engineered to provide the necessary ’self-bias’ at the output. This approach precludes the need for bias circuitry and maintains the highly compact nature of the synapse with a commensurate reduction in power consumption” ; see also Chen, Pg. 1514, Col. 1, Para. 4, “The input voltages and coupling coefficients are illustrated in Fig. 3(b), where V 1 , V 2 , ..., V n are the input voltages; C 1 , C 2 , ...,C n are the coupling capacitance between the floating gate and each input gates; C 0 is the coefficient between the floating gate and the substrate; VF is the floating gate voltage” ), which contributes to scalable spike neuron network hardware ( Chen, Pg. 1517, Col. 1, Para. 4, “The charge-coupled synapse is demonstrated to be able to capture the intrinsic dynamics of the real synapse and so can mimic the synaptic plasticity in a spiking neuron cell. The proposed spiking neuron cell has the potential for scalability to produce biologically plausible SNNs in hardware” ). Regarding Claim 6 , Nishi in view of Rose, Noack, and Chen teach the spike neural network circuit of claim 1, wherein the switched capacitor circuit includes a plurality of switches, and is naturally discharged based on operations of the plurality of switches ( Noack, Pg. 3, Col. 2, Para. 4, “Between incoming spikes an exponential decay of V U , V R and V PSC is performed by SC leaky integrator circuits” , where “SC” are “switched capacitor (SC) circuits” , where the plural “circuits” demonstrates a plurality of switches, see Noack, Pg. 1, Abstract, “we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits” , and where “preform[ing]” “exponential decay of . . . V psc ” is within the broadest reasonable interpretation of naturally discharging the generated synaptic voltage, which is based on the operations of the plurality of switches, see Noack, Pg. 5, Fig. 4, “Switch signals for update at an incoming presynaptic spike and for exponential decays of . . . V PSC ” ). The reasons for obviousness were discussed in regard to the rejection of claim 1 above and remain applicable here. Regarding Claim 7 , Nishi in view of Rose, Noack, and Chen teach the spike neural network circuit of claim 6, wherein the plurality of switches operate under control of a plurality of control signals ( Noack, Pg. 5, Fig. 4, “Switch signals for update at an incoming presynaptic spike and for exponential decays of . . . V PSC ” , where the plurality of “switch[es]” operate under a plurality of control “signals” ). The reasons for obviousness were discussed in regard to the rejection of claim 1 above and remain applicable here. Regarding Claim 8 , Nishi in view of Rose, Noack, and Chen teach the spike neural network circuit of claim 7, wherein the plurality of control signals have different periods, respectively ( Noack, Pg. 5, Fig. 4, “Switch signals for update at an incoming presynaptic spike and for exponential decays of . . . V PSC . Dotted lines indicate that decay events can occur independently as well as simultaneously” , where the “decay events” , and therefore the “signals” causing the “decay events” can occur during different, “independent” , periods; see also Noack, Pg. 2, Col. 2, Para. 4, “Time constants are set via counters that govern the switching cycles of the SC circuits” , where “counters” govern the “switching cycles” , which, as shown in fig. 4 , have different periods) . The reasons for obviousness were discussed in regard to the rejection of claim 1 above and remain applicable here. Regarding Claim 9 , Nishi in view of Rose, Noack, and Chen teach the spike neural network circuit of claim 1, wherein the neuron circuit is configured to compare the membrane voltage with the threshold voltage ( Nishi, Fig. 7 , where “112” is a component of “NEURON CIRCUIT 110” ; Nishi, Para. [0073], “The threshold comparator circuit 112 compares the membrane potential outputted from the integration circuit 111 with the predetermined threshold” , where, as discussed above, the “membrane potential” is the membrane voltage, see Nishi, Para. [0072], “The integration circuit 111 integrates the inputted synaptic current to convert the same to a voltage called a membrane potential” and the “ predetermined threshold” is a threshold voltage because it is used for voltage comparison, see Nishi, Para. [0073], “The threshold comparator circuit 112 compares the membrane potential outputted from the integration circuit 111 with the predetermined threshold” ) , and to generate the output spike signal in response to an event that the comparison result indicates that the membrane voltage exceeds the threshold voltage ( Nishi, Para. [0073], “The spike generation circuit 113 generates and outputs a spike voltage when the membrane potential exceeds the threshold. The generation of such a spike voltage in the neuron circuit 110 is referred to as firing” , where “spike voltage” is within the broadest reasonable interpretation of an output spike signal, see generally Nishi, Para. [0036], “spike voltage signals” ; Nishi, Fig. 7 , where the “SPIKE VOLTAGE” is the output of the “NEURON CIRCUIT 110” , and more specifically, subcomponent “THRESHOLD COMPARATOR CIRCUIT 112” , as indicated by the arrow symbol) . Regarding Claim 10 , Nishi in view of Rose, Noack, and Chen teach the spike neural network circuit of claim 1, wherein the membrane voltage increases based on the synaptic voltage ( Nishi, Para. [0072], “The integration circuit 111 integrates the inputted synaptic current to convert the same to a voltage called a membrane potential” , where the membrane voltage, “a voltage called a membrane potential” , increases based on the “synaptic current” because it is directed “convert[ed]” from it, and where, as discussed above and in view of Rose, the output data is converted to synaptic voltage before being received by the conversion circuit, see Rose, Para. [0030], “The charge is then allowed to pass through the driving NMOS transistor WN 80 to increase the voltage V c 90 across the summation capacitance 100 . . . Thus, the amount of charge and the associated voltage V c 90 is weighted according to the total memristance values M 20 at all inputs” ) . The reasons for obviousness were discussed in regard to the rejection of claim 1 above and remain applicable here. Regarding Claim 11 , Nishi in view of Rose, Noack, and Chen teach an operating method of a spike neural network circuit, the method comprising ( Nishi, Fig. 5 and Nishi, Para. [0058], “FIG. 5 is a diagram illustrating an example of the configuration of a spiking neural network device 100 according to the first embodiment. As illustrated in FIG. 5, the spiking neural network device 100 of the present embodiment includes a synaptic element 120, a neuron circuit 110, a synaptic potentiator 140, a synaptic depressor 150, and a determinator 160” , which can be operated for “ a learning method of the spiking neural network” , see Nishi, Para. [0057], “a learning method of the spiking neural network device” ): receiving an input spike signal and outputting data based on a weight ( Nishi, Fig. 5 , where the “SYNAPTIC ELEMENT 120” receives the “SPIKE SIGNAL” and outputs “SYNAPTIC SIGNAL” data; Nishi, Para. [0059], “The synaptic element 120 has weight storage 121 for storing a variable weight. The synaptic element 120 receives a spike signal (first spike signal). When receiving the spike signal, the synaptic element 120 transfers, to the neuron circuit 110, a synaptic signal whose intensity is adjusted according to the weight held by the weight storage 121” , where the outputted “synaptic signal” data is “adjusted according to the weight” ) ; generating a synaptic voltage based on the output data ( Rose, Para. [0029], “The synaptic circuit shown in FIG. 1 achieves . . . tasks through charge sharing” , where the “charge sharing” “synaptic circuit” generates a synaptic voltage, “increase the voltage Vc 90” , based on current, “charge . . . pass[ing] through” the circuit, that is output to the circuit, see Rose, Para. [0030], “The charge is then allowed to pass through the driving NMOS transistor WN 80 to increase the voltage V c 90 across the summation capacitance 100 . . . Thus, the amount of charge and the associated voltage V c 90 is weighted according to the total memristance values M 20 at all inputs” ); naturally discharging the generated synaptic voltage ( Noack, Pg. 3, Col. 2, Para. 4, “Between incoming spikes an exponential decay of V U , V R and V PSC is performed by SC leaky integrator circuits” , where “SC” are “switched capacitor (SC) circuits” , see Noack, Pg. 1, Abstract, “we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits” , and where “preform[ing]” “exponential decay of . . . V psc ” is within the broadest reasonable interpretation of naturally discharging the generated synaptic voltage) ; receiving the synaptic voltage and generating a membrane voltage ( Nishi, Fig. 7 , where a conversion circuit, “INTEGRATION CIRCUIT 111” , receives the “SYNAPTIC CURRENT” output data, see Para. [0071], “The synaptic current corresponds to a synaptic signal and is inputted to the neuron circuit 110” , where, as discussed above, in view of Rose, the output data was converted to synaptic voltage, see Rose, Para. [0030], “The charge is then allowed to pass through the driving NMOS transistor WN 80 to increase the voltage V c 90 across the summation capacitance 100 . . . Thus, the amount of charge and the associated voltage V c 90 is weighted according to the total memristance values M 20 at all inputs” , in order to generate the membrane voltage, “MEMBRANE POTENTIAL” ; Nishi, Para. [0072], “The integration circuit 111 integrates the inputted synaptic current to convert the same to a voltage called a membrane potential” ); comparing the membrane voltage with a threshold voltage ( Nishi, Para. [0073], “The threshold comparator circuit 112 compares the membrane potential outputted from the integration circuit 111 with the predetermined threshold” , where, as discussed above, the “membrane potential” is the membrane voltage, see Nishi, Para. [0072], “The integration circuit 111 integrates the inputted synaptic current to convert the same to a voltage called a membrane potential” and the “ predetermined threshold” is a threshold voltage because it is used for voltage comparison, see Nishi, Para. [0073], “The threshold comparator circuit 112 compares the membrane potential outputted from the integration circuit 111 with the predetermined threshold” ) ; and generating an output spike signal in response to an event that the comparison result indicates that the membrane voltage exceeds the threshold voltage ( Nishi, Para. [0073], “The spike generation circuit 113 generates and outputs a spike voltage when the membrane potential exceeds the threshold. The generation of such a spike voltage in the neuron circuit 110 is referred to as firing” , where “spike voltage” is within the broadest reasonable interpretation of an output spike signal, see generally Nishi, Para. [0036], “spike voltage signals” ; Nishi, Fig. 7 , where the “SPIKE VOLTAGE” is the output of the “NEURON CIRCUIT 110” , and more specifically, subcomponent “THRESHOLD COMPARATOR CIRCUIT 112” , as indicated by the arrow symbol) , wherein generating the synaptic voltage based on the output data comprises ( Rose, Para. [0029], “The synaptic circuit shown in FIG. 1 achieves . . . tasks through charge sharing” , where the “charge sharing” “synaptic circuit” generates a synaptic voltage, “increase the voltage Vc 90” , based on current, “charge . . . pass[ing] through” the circuit, that is output to the circuit, see Rose, Para. [0030], “The charge is then allowed to pass through the driving NMOS transistor WN 80 to increase the voltage V c 90 across the summation capacitance 100 . . . Thus, the amount of charge and the associated voltage V c 90 is weighted according to the total memristance values M 20 at all inputs” ) : selectively charging a plurality of binary-weighted internal capacitors based on respective bits of the output data ( Chen, Pg. 1514, Col. 2, Fig. 3 ; Chen, Pg. 1514, Col. 1, Para. 4, “The input voltages and coupling coefficients are illustrated in Fig. 3(b), where V 1 , V 2 , ..., V n are the input voltages; C 1 , C 2 , ...,C n are the coupling capacitance between the floating gate and each input gates; C 0 is the coefficient between the floating gate and the substrate; VF is the floating gate voltage” ; and Chen, Pg. 1512, Col. 2, Para. 3, “The deeper surface potential well formed in the silicon under the second gate, causes the charge packet to start transferring from the first capacitor to the second and subsequently to the output terminal” , where “C 1 , C 2 , ...,C n ” are a plurality of internal capacitors, which are selectively charged by the “coupl[ed]” “input voltages” , “ V 1 , V 2 , ..., V n ”, which, when integrated into the system of Nishi in view of Rose and Noack, are binary weighted capacitors based on respective bits of the output data, see Noack, Pg. 8, Col. 1, Para. 2, “The scaling of the PSC is done via binary weighted capacitors” and Noack, Pg. 4, Col. 2, Para. 2, “With the period of the matrix column cycle, the resulting exponentially decaying PSC voltage is sampled on the 4-bit binary-weighted capacitor C W and transferred to the neuron circuit” ; see also Nishi, Para. [0071], “The weight value may be stored as digital data in the memory circuit” ; Nishi, Para. [0117], “Here, the synapse is a binary synapse with a weight value of only 0 or 1” ) ; and sharing charge between the plurality of internal capacitors and a second capacitor to generate the synaptic voltage ( Rose, Para. [0029], “The synaptic circuit shown in FIG. 1 achieves . . . tasks through charge sharing” , where the “charge sharing” “synaptic circuit” generates a synaptic voltage, “increase the voltage Vc 90” , based on current, “charge . . . pass[ing] through” the circuit, that is output to the circuit, see Rose, Para. [0030], “The charge is then allowed to pass through the driving NMOS transistor WN 80 to increase the voltage V c 90 across the summation capacitance 100 . . . Thus, the amount of charge and the associated voltage V c 90 is weighted according to the total memristance values M 20 at all inputs” , where in view of Chen, the “charge sharing” is between the plurality of internal capacitors, “C 1 , C 2 , ...,C n ” , and the “second” capacitor, see Chen, Pg. 1514, Col. 2, Fig. 3 ; Chen, Pg. 1514, Col. 1, Para. 4, “The input voltages and coupling coefficients are illustrated in Fig. 3(b), where V 1 , V 2 , ..., V n are the input voltages; C 1 , C 2 , ...,C n are the coupling capacitance between the floating gate and each input gates; C 0 is the coefficient between the floating gate and the substrate; VF is the floating gate voltage” ; and Chen, Pg. 1512, Col. 2, Para. 3, “The deeper surface potential well formed in the silicon under the second gate, causes the charge packet to start transferring from the first capacitor to the second and subsequently to the output terminal” ) . The reasons for obviousness were discussed in regard to the rejection of claim 1 above and remain applicable here. Regarding Claim 13 , the additional elements of the dependent claim are substantially the same as the limitations of Claim 10, therefore it is rejected under the same rationale . 07-21-aia AIA Claim s 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Nishi in view of Rose, Noack, Chen, and Akopyan et al. (hereinafter Akopyan) (Pat. Pub. No. US 2017/0286825 A1) . Regarding Claim 2 , Nishi in view of Rose, Noack, and Chen teach the spike neural network circuit of claim 1, wherein the input spike signal includes an input spike event ( Nishi, Fig. 5 , where the “SYNAPTIC ELEMENT 120” receives the “SPIKE SIGNAL” as an input event, see also Nishi, Abstract, “The synaptic element has a variable weight and outputs, in response to input of a first spike signal, a synaptic signal having intensity adjusted in accordance with the weight” ) . . . . Nishi in view of Rose, Noack, and Chen do not explicitly disclose . . . and axon address information. However, Akopyan teaches . . . [a neural network circuit, wherein a spike input includes, a firing event] and axon address information ( Para. [0032], “In a neural network comprising multiple core circuits 100, firing events are routed between core circuits 100 of the neural network in the form of spike event packets. Each spike event packet may include a firing event or spike event encoded as a binary address representing a target axon 15” ). Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the spike neural network, wherein an input spike signal includes an input spike event of Nishi in view of Rose, Noack, and Chen with the neural network circuit, wherein a spike input includes, a firing event and axon address information of Akopyan in order to link weights for synaptic output generation to axon components ( Akopyan, Para. [0035], “For each entry representing a neuron 11, a dot product may be computed between the vector of active axons 15 in the current sub-timestep and the synaptic connectivity information maintained in said entry, i.e., the synaptic weights” , which is effectuated by a decoder, see Akopyan, Para. [0032], “Each spike event packet may further include a timestep and a sub-timestep indicating when a firing event encapsulated in said spike event packet was generated. A decoder of each core circuit 100 may be configured for receiving and decoding spike event packets” ), to allow for resource sharing that reduces the required physical space of the system and also reduces power consumption ( Akopyan, Para. [0068], “By sharing one or more neuron attributes or parameters, repeated networks of neurons and axons that are found on a neurosynaptic chip may be localized to a smaller number of the cores on the chip. As a result, a given collection of neurosynaptic computations may require less physical space on a neurosynaptic chip and/or less power than non-multiplexed cores” ). Regarding Claim 3 , Nishi in view of Rose, Noack, Chen, and Akopyan teach the spike neural network circuit of claim 2, wherein the weight storage includes a weight memory configured to store the weight ( Nishi, Para. [0070] – [0071], “The weight storage 121 is, for example, a memory circuit including a memory element . . . The weight value may be stored as digital data in the memory circuit and may be stored as analog data” ) , and an axon address decoder, and the axon address decoder is configured to control the weight memory so as to output the data based on the axon address information ( Akopyan, Para. [0032], “Each spike event packet may further include a timestep and a sub-timestep indicating when a firing event encapsulated in said spike event packet was generated. A decoder of each core circuit 100 may be configured for receiving and decoding spike event packets” , where the “decoder” is an axon address decoder because it “decod[es] spike event packets” , which include “axon” “address[es]” , see Akopyan, Para. [0032], “In a neural network comprising multiple core circuits 100, firing events are routed between core circuits 100 of the neural network in the form of spike event packets. Each spike event packet may include a firing event or spike event encoded as a binary address representing a target axon 15” , which controls the “weight” memory output by linking weights for “synaptic” output generation to “active axon” components, see Akopyan, Para. [0035], “For each entry representing a neuron 11, a dot product may be computed between the vector of active axons 15 in the current sub-timestep and the synaptic connectivity information maintained in said entry, i.e., the synaptic weights” ) . The reasons for obviousness were discussed in regard to the rejection of claim 2 above and remain applicable here . 07-21-aia AIA Claim s 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Nishi in view of Rose, Noack, Chen, and Ishikawa et al. (hereinafter Ishikawa) (Pat. Pub. No. US 2010/0259432 A1) . Regarding Claim 4 , Nishi in view of Rose, Noack, and Chen teach the spike neural network circuit of claim 1 . . . (see the rejection of Claim 1 above for a detailed discussion of these disclosures). Nishi in view of Rose, Noack, and Chen do not explicitly disclose . . . wherein a sum of capacitances of the plurality of internal capacitors of the first capacitor is smaller than a capacitance of the second capacitor. However, Ishikawa teaches [a voltage generating circuit,] wherein a sum of capacitances of the plurality of internal capacitors of the first capacitor is smaller than a capacitance of the second capacitor ( Fig. 7 ; Para. [0049], “The reference voltage generating circuit 320 includes 3 capacitors C11, C12 and C13 having a capacitance ratio 1:2:4, and 3 capacitors C21, C22 and C23 having a capacitance ratio 1:2:4” , where “C11, C12 and C13” are internal capacitors of the first capacitor, “C R1 ” , and “C21, C22 and C23” are internal capacitors of the second capacitor, “C R2 ” , see Fig. 9 and Para. [0054], “The equivalent circuit includes a series circuit in which an upper limit reference capacitor C R1 receiving the power supply voltage Vcc and a lower limit reference capacitor C R2 receiving the ground voltage GND are connected in series. The upper limit reference capacitor C R1 has a capacitance corresponding to a sum of the capacitances of the first group of capacitors C11, C12 and C13, that is, 1Co+2Co+4Co=7Co, where Co is an arbitrary constant . . . On the other hand, the lower limit reference capacitor C R2 has a capacitance corresponding to a sum of the capacitances of the second group of capacitors C21, C22 and C23, that is, 1Co+2Co+4Co=7Co” , where a sum of capacitances of the plurality of internal capacitors is any amount resulting from addition of two or more capacities, such as combining “1Co+2Co” , which is smaller than a capacitance of the second capacitor, such as “4Co” or “7Co” ). Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the spike neural network, wherein a charge sharing circuit, comprised of a first capacitor with a plurality of internal capacitors and a second capacitor, is used to generate a synaptic voltage of Nishi in view of Rose, Noack, and Chen with a voltage generating circuit that includes a first and second capacitor, wherein the first capacitor includes a plurality of internal capacitors and a capacitance sum of the plurality of values is smaller than a capacitance of the second capacitor of Ishikawa in order to allow for adjustable voltage generation ( Ishikawa, Para. [0064], “Accordingly, by changing the connections of the capacitors C11, C12, C13, C21, C22 and C23 within the reference voltage generating circuit 420, it becomes possible to adjust the reference width in steps from (16/33)Vcc to Vcc” ), enabled by capacitors with shared capacitance ratios ( Ishikawa, Para. [0054], “The equivalent circuit includes a series circuit in which an upper limit reference capacitor C.sub.R1 receiving the power supply voltage Vcc and a lower limit reference capacitor C.sub.R2 receiving the ground voltage GND are connected in series” ; Ishikawa, Para. [0058], “FIG. 11, a reference voltage generating circuit 420 includes 3 capacitors C11, C12 and C13 having a capacitance ratio 1:2:4, and 3 capacitors C21, C22 and C23 having a capacitance ratio 1:2:4” ), which as discussed above requires a capacitance sum of the of the plurality of values is smaller than a capacitance of the second capacitor, and which can be tuned for case-specific uses and circumstances (see generally Ishikawa, Para. [0078], “Accordingly, in such cases where the analog input signal VIP or VIM would not be appropriately converted into the digital code by the ADC 500, the reference width VRH-VRL is adjusted to become the same as the amplitude of the analog input signal VIP or VIM” and Ishikawa, Para. [0101], “Therefore, the ADC in accordance with the embodiment described above internally generates the reference voltages from the power supply voltage Vcc and the ground voltage GND, and adjusts the reference width of the reference voltages” ). Regarding Claim 5 , Nishi in view of Rose, Noack, Chen, and Ishikawa teach the spike neural network circuit of claim 4, wherein the charge sharing synaptic circuit is configured to generate the synaptic voltage ( Nishi, Fig. 5 and Nishi, Para. [0058], “FIG. 5 is a diagram illustrating an example of the configuration of a spiking neural network device 100 according to the first embodiment” , where in view of Rose, the “spiking neural network” includes a “charge sharing” “synaptic circuit” , see Rose, Para. [0029], “The synaptic circuit shown in FIG. 1 achieves . . . tasks through charge sharing” and Rose, Para. [0030], “The charge is then allowed to pass through the driving NMOS transistor WN 80 to increase the voltage V c 90 across the summation capacitance 100 . . . Thus, the amount of charge and the associated voltage V c 90 is weighted according to the total memristance values M 20 at all inputs” ) based on a capacitance ratio between the first capacitor and the second capacitor ( Ishikawa, Para. [0061], “the reference voltage generating circuit 420 generates the reference voltages VRH and VRL in order to obtain a reference width (16/30)Vcc” , which is based on the capacitance ratio of “1:2:4” that is shared between both the first and the second capacitor, see Ishikawa, Fig. 11 and Ishikawa, Para. [0058], “FIG. 11, a reference voltage generating circuit 420 includes 3 capacitors C11, C12 and C13 having a capacitance ratio 1:2:4, and 3 capacitors C21, C22 and C23 having a capacitance ratio 1:2:4” ). The reasons for obviousness were discussed in regard to the rejection of claim 1 above, for the combination with Rose, and in regard to the rejection of claim 4 above, for the combination with Ishikawa, and remain applicable here . 07-21-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Nishi in view of Rose, Noack, Chen, and Daily et al. (hereinafter Daily) (Pat No. US 9,020,870 B1) . Regarding Claim 12 , Nishi in view of Rose, Noack, and Chen teach the method of claim 11, further comprising: initializing . . . the membrane voltage in response to generating the output spike signal ( Nishi, Para. [0045], “After firing, the membrane potential of the neuron j is reset to a certain value, which is called a reset potential” , where “reset[ting] to a certain value” is initializing the membrane voltage, which occurs after the “firing” of the output spike voltage, see Nishi, Para. [0073], “The spike generation circuit 113 generates and outputs a spike voltage when the membrane potential exceeds the threshold. The generation of such a spike voltage in the neuron circuit 110 is referred to as firing” ). While Nishi in view of Rose, Noack, and Chen teach . . . the synaptic voltage and (where, in view of Rose, the synaptic current, see Nishi, Fig. 5 , where the “SYNAPTIC ELEMENT 120” receives the “SPIKE SIGNAL” and outputs “SYNAPTIC SIGNAL” , is converted into synaptic voltage, see Rose, Para. [0029], “The synaptic circuit shown in FIG. 1 achieves . . . tasks through charge sharing” , where the “charge sharing” “synaptic circuit” generates a synaptic voltage, “increase the voltage Vc 90” , based on current, “charge . . . pass[ing] through” the circuit, that is output to the circuit, see Rose, Para. [0030], “The charge is then allowed to pass through the driving NMOS transistor WN 80 to increase the voltage V c 90 across the summation capacitance 100 . . . Thus, the amount of charge and the associated voltage V c 90 is weighted according to the total memristance values M 20 at all inputs” ), Nishi in view of Rose, Noack, and Chen do not explicitly disclose . . . initializing the synaptic voltage . . . in response to generating the output . . . . However, Daily teaches [a system using spiking neural networks, comprising] ( Pg. 26, Col. 5, Ln. 17-18, “The system uses a spiking neural network” ) . . . initializing the synaptic voltage . . . in response to generating the output . . . ( Pg. 32, Col. 18, Ln. 28-44, “During the experiments, a "entire-hard-reset" was used instead of STDP . . . The "entire-hard-reset" means that the initial state is always made the same before any input; i.e., to reset all voltages and synaptic currents to a default value. . . . Resetting the network before inputs means there is no dynamic state beforehand, so only the inputs and the delays and learned weights of the connections are going to trigger a PCG” , where “reset all voltages and synaptic currents” is within the broadest reasonable interpretation of initializing and includes the synaptic voltage; additionally, it is logically required for the output to be generated before the “entire-hard-reset” because the output is dependent on the “dynamic state” , see also Pg. 28, Col. 10, Ln. 41-64, “1) Present an input pattern to the first layer of neurons through the spike encoder which converts the input pattern into multiple spike trains that act as input to the neurons in the network (which causes neuron firing). 2) Wait until the neuron firing in the network has subsided or stopped . . . 4) Repeat steps (1) through (3)” , where the next round of inputs, “Repeat steps (1)” , is in response to generating an output, “ 2) Wait until the neuron firing in the network has subsided or stopped” , and therefore, the “entire-hard-reset” is in response to generating the output spike) . Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the spike neural network, wherein the membrane voltage is initialized in response to generating the output spike signal of Nishi in view of Rose, Noack, and Chen with the system using spiking neural networks, comprising initializing the synaptic voltage in response to generating an output of Daily in order to eliminate residual voltages, which may unintendedly skew future outputs ( Daily, Pg. 32, Col. 18, Ln. 41-44, “Resetting the network before inputs means there is no dynamic state beforehand, so only the inputs and the delays and learned weights of the connections are going to trigger a PCG” ), using a method that has been shown to achieve the best results ( Daily, Pg. 32, Col. 18, Ln. 36-41, “Knusel tried a variety of resets, including just resetting neuron voltages (partial-hard), and setting either neurons only or neurons and synapses to random values to approximate the history of past inputs ("entire-random-" or "partial-random-reset"), vs. no reset, and got his best results with the entire-hard-reset” ). Response to Arguments Applicant's arguments filed on January 30th, 2026 have been fully considered. Each argument is addressed in detail below. I. Applicant argues the objections to the claims should be withdrawn (Applicant’s Remarks, 1/30/2026, Pg. 5-6, Section “Objections to the Claims”). Applicant’s amendments have overcome each and every objection to the claims, as previously set forth in the November 19 th , 2025 Office Action. As a result, these objections have been withdrawn. II. Applicant argues the rejections to the claims, under the doctrine of nonstatutory double patenting, should be withdrawn (Applicant’s Remarks, 1/30/2026, Pg. 6-9, Section “Rejections of Claims under Obviousness-type Double Patenting”). Applicant’s amendments have overcome each and every rejection to the claims, under the doctrine of nonstatutory double patenting, as previously set forth in the November 19 th , 2025 Office Action. As a result, these rejections have been withdrawn. III. Applicant argues the rejections to the claims, under 35 U.S.C. 103, should be withdrawn (Applicant’s Remarks, 1/30/2026, Pg. 9-14, Section “Rejections of Claims under 35 U.S.C. § 103”). In response to Applicant’s amendments, the previously communicated rejections under 35 U.S.C. § 103, have been withdrawn. However, Applicants arguments are not persuasive in light of the new grounds for rejection, under 35 U.S.C. § 103, discussed in detail above. The new grounds of rejection rely on new prior art of record to teach the new combination of elements in the amended independent claims, which were not presented in this arrangement in any of the previously presented claims. As a result, Applicant’s arguments are rendered moot. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW BRYCE GOLAN whose telephone number is (571)272-5159. The examiner can normally be reached Monday through Friday, 8:00 AM to 5:00 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexey Shmatov can be reached at (571) 270-3428. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW BRYCE GOLAN/Examiner, Art Unit 2123 /ALEXEY SHMATOV/Supervisory Patent Examiner, Art Unit 2123 Application/Control Number: 18/125,552 Page 2 Art Unit: 2123 Application/Control Number: 18/125,552 Page 3 Art Unit: 2123 Application/Control Number: 18/125,552 Page 4 Art Unit: 2123 Application/Control Number: 18/125,552 Page 5 Art Unit: 2123 Application/Control Number: 18/125,552 Page 6 Art Unit: 2123 Application/Control Number: 18/125,552 Page 7 Art Unit: 2123 Application/Control Number: 18/125,552 Page 8 Art Unit: 2123 Application/Control Number: 18/125,552 Page 9 Art Unit: 2123 Application/Control Number: 18/125,552 Page 10 Art Unit: 2123 Application/Control Number: 18/125,552 Page 11 Art Unit: 2123 Application/Control Number: 18/125,552 Page 12 Art Unit: 2123 Application/Control Number: 18/125,552 Page 13 Art Unit: 2123 Application/Control Number: 18/125,552 Page 14 Art Unit: 2123 Application/Control Number: 18/125,552 Page 15 Art Unit: 2123 Application/Control Number: 18/125,552 Page 16 Art Unit: 2123 Application/Control Number: 18/125,552 Page 17 Art Unit: 2123 Application/Control Number: 18/125,552 Page 18 Art Unit: 2123 Application/Control Number: 18/125,552 Page 19 Art Unit: 2123 Application/Control Number: 18/125,552 Page 20 Art Unit: 2123 Application/Control Number: 18/125,552 Page 21 Art Unit: 2123 Application/Control Number: 18/125,552 Page 22 Art Unit: 2123 Application/Control Number: 18/125,552 Page 23 Art Unit: 2123 Application/Control Number: 18/125,552 Page 24 Art Unit: 2123 Application/Control Number: 18/125,552 Page 25 Art Unit: 2123 Application/Control Number: 18/125,552 Page 26 Art Unit: 2123 Application/Control Number: 18/125,552 Page 27 Art Unit: 2123
Prosecution Insights