DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed on May 22nd, 2026. The amendments are linked to the original application filed on May 23rd, 2023.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2022-0065968, filed on May 30th, 2022.
Response to Amendment
Regarding Claim Rejections – 35 U.S.C. 103
The applicant argues the provided prior art Morie, “fails to teach or suggest a pulse generator that generates a plurality of modulation pulses from a single input spike signal, much less as claimed.”. The examiner has reviewed the specification, remarks and proposed amendments and has found the applicants argument persuasive. The claims are interpreted by the examiner using the broadest reasonable interpretation, BRI, per the MPEP 2111, which states, “The broadest reasonable interpretation does not mean the broadest possible interpretation. Rather, the meaning given to a claim term must be consistent with the ordinary and customary meaning of the term (unless the term has been given a special definition in the specification), and must be consistent with the use of the claim term in the specification and drawings. Further, the broadest reasonable interpretation of the claims must be consistent with the interpretation that those skilled in the art would reach.”. The amendments made as well as the provided remarks have changed the BRI of the claim and the examiner no longer relies on Morie to teach a “pulse generator” as claimed.
Next, the applicant argues the provided prior art Oh fails to also teach the use of a pulse generator as claimed. The examiner has reviewed the specification, remarks and proposed amendments and has found the applicants argument persuasive. Further, the examiner would like to note the proposed art Oh qualifies as an exception to the conditions of patentability under 35 U.S.C. 102(b)(1)(A), which states: “DISCLOSURES MADE 1 YEAR OR LESS BEFORE THE EFFECTIVE FILING DATE OF THE CLAIMED INVENTION.—A disclosure made 1 year or less before the effective filing date of a claimed invention shall not be prior art to the claimed invention under subsection (a)(1) if— (A) the disclosure was made by the inventor or joint inventor or by another who obtained the subject matter disclosed directly or indirectly from the inventor or a joint inventor; or …”. Oh was published within one year of the filing of this application and lists the same inventors and assignee. Therefore, The examiner is/was unable to use Oh as prior art to teach any limitations in this application. Because of this, the examiner no longer relies on Oh to teach any element of any claim.
Finally, the applicant argues the provided arts Yajima and Garg fails to teach the limitations not taught by Morie and Oh. As stated above, the art Oh qualifies for exception to the conditions of patentability under 35 U.S.C. 102(b)(1)(A) and therefore Oh cannot be relied upon to teach claimed invention. Because of this, further arguments including Oh with any combination of arts is considered moot at this time.
As stated above, the examiner is unable to rely on Oh to teach the claimed invention as it qualifies as an exception to the conditions for patentability. As a result, the examiner is required to reconsider the previous non-final rejection before submitting a final action. After reconsideration of the claims and specification, the examiner has raised a new rejection under 35 U.S.C. 112(b), see 112(b) rejection below, as well as an objection to the title of the invention, see title objection below. Next, the claims were reinterpreted and a full and thorough search of arts was performed. During this search the examiner noted a combination of arts, compliant 35 U.S.C. 102[3], able to teach the claimed subject matter. The examiner believes a person of ordinary skill in the art would be motivated to combine the concepts or information in the proposed prior arts to teach the claimed invention. Therefore, after reconsideration, the current claims have been rejected under 35 U.S.C. 103, see 103 rejection below.
Specification Objection - Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
Claim 1:
“a pulse generator configured to receive a single input spike signal, and to generate a first modulation pulse and a second modulation pulse activated during times of different lengths based on the single input spike signal;”
“a first switch configured to deliver a first calculation signal generated from the first current source array to the membrane capacitor, in response to the first modulation pulse; and”
“a second switch configured to deliver a second calculation signal generated from the second current source array to the membrane capacitor, in response to the second modulation pulse.”
Claim 4:
“wherein the membrane capacitor is configured to: accumulate the first calculation signal during a time interval when the first modulation pulse is activated; and”
Claim 6:
“wherein a channel width of the first transistor is configured to be same as a channel width of the second transistor.”
Claim 7:
“wherein the weight memory is configured to store a weight in form of a binary number”
Claim 10:
“a neuron circuit configured to generate an output spike signal, when a voltage level of the membrane capacitor is higher than a threshold voltage level.”
Claim 11:
“a clock generator configured to generate a clock signal in response to the single input spike signal;”
“a counter configured to count the number of times the clock signal toggles;”
“a first pulse output unit configured to output the first modulation pulse activated before a time point when the counted value is greater than a first reference value from a time point when the single input spike signal is received; and”
“a second pulse output unit configured to output the second modulation pulse activated before a time point when the counted value is greater than a second reference value from the time point when the single input spike signal is received.”
Claim 12:
“a pulse generator configured to receive a single input spike signal and generate first and second modulation pulses activated during times of different lengths based on the single input spike signal;”
“a first switch connected between the first node and an output line and configured to operate in response to the first modulation pulse;”
“a second switch connected between the second node and the output line and configured to operate in response to the second modulation pulse; and”
Claim 17:
“a clock generator connected with the first output terminal and configured to generate a clock signal;”
“a counter configured to receive the single input spike signal and count the number of times the clock signal toggles;”
“a first comparator configured to compare a value counted by the counter with a first reference value to generate first and second control signals;”
“a second comparator configured to compare the counted value with a second reference value to generate third and fourth control signals;”
“wherein the first reset terminal is configured to receive the fourth control signal.”
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4, 6, 7, 10, 11, 12, and 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-Al A 35 U.S.C. 112, the applicant), regards as the invention.
Claim Limitations:
Claim 1:
“a pulse generator configured to receive a single input spike signal, and to generate a first modulation pulse and a second modulation pulse activated during times of different lengths based on the single input spike signal;”
“a first switch configured to deliver a first calculation signal generated from the first current source array to the membrane capacitor, in response to the first modulation pulse; and”
“a second switch configured to deliver a second calculation signal generated from the second current source array to the membrane capacitor, in response to the second modulation pulse.”
Claim 4:
“wherein the membrane capacitor is configured to: accumulate the first calculation signal during a time interval when the first modulation pulse is activated; and”
Claim 6:
“wherein a channel width of the first transistor is configured to be same as a channel width of the second transistor.”
Claim 7:
“wherein the weight memory is configured to store a weight in form of a binary number”
Claim 10:
“a neuron circuit configured to generate an output spike signal, when a voltage level of the membrane capacitor is higher than a threshold voltage level.”
Claim 11:
“a clock generator configured to generate a clock signal in response to the single input spike signal;”
“a counter configured to count the number of times the clock signal toggles;”
“a first pulse output unit configured to output the first modulation pulse activated before a time point when the counted value is greater than a first reference value from a time point when the single input spike signal is received; and”
“a second pulse output unit configured to output the second modulation pulse activated before a time point when the counted value is greater than a second reference value from the time point when the single input spike signal is received.”
Claim 12:
“a pulse generator configured to receive a single input spike signal and generate first and second modulation pulses activated during times of different lengths based on the single input spike signal;”
“a first switch connected between the first node and an output line and configured to operate in response to the first modulation pulse;”
“a second switch connected between the second node and the output line and configured to operate in response to the second modulation pulse; and”
Claim 17:
“a clock generator connected with the first output terminal and configured to generate a clock signal;”
“a counter configured to receive the single input spike signal and count the number of times the clock signal toggles;”
“a first comparator configured to compare a value counted by the counter with a first reference value to generate first and second control signals;”
“a second comparator configured to compare the counted value with a second reference value to generate third and fourth control signals;”
“wherein the first reset terminal is configured to receive the fourth control signal.”
invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The disclosure of this claim is devoid of any structure that performs the function in the claim. This claim discloses an apparatus which does not further teach the structure which the functions are performed on. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre- AIA 35 U.S.C. 112, second paragraph.
Applicant may:
Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and M PEP§§ 608.0l(o) and 2181.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 6, 8, and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation, “wherein a first current source for generating a current of a smallest magnitude among current sources of the first current source array generates a current of the same magnitude as a second current source for generating a current of a smallest magnitude among current sources of the second current source array.” (Emphasis added). The term “smallest magnitude” in this claim is undefined. It is unclear what the smallest amount is and/or how it is differentiated from any other “small magnitude”. One of ordinary skill in the art would not be able to determine the metes and bounds of the claim because the term “smallest magnitude” is undefined and therefore this claim is rejected under 35 U.S.C. 112(b) for being indefinite. For examination purposes the claim will be interpreted to mean, “wherein a first current source for generating a current of a smallest magnitude among current sources of the first current source array generates a current of the same magnitude as a second current source for generating a current of a smallest magnitude among current sources of the second current source array.” Claim 6 depends on rejected claim 5 and is also rejected under 35 U.S.C. 112(b) by virtue of this dependency. Appropriate correction is required.
Claim 8 recites the limitation, “wherein the weight in the form of the binary number includes first to N+Mth bits (where N is a natural number of 1 or more) corresponding to a sequential size,” (Emphasis added). The variable “M” has not been defined in the claims and it is unclear as to what value “M” is related and/or bound to. One of ordinary skill in the art would not be able to determine the metes and bounds of the claimed subject matter because “M” is undefined and can be any value or amount, therefore, this claim is rejected under 35 U.S.C. 112(b) for being indefinite. For examination purposes the variable “M” will be interpreted to mean a designated value, per interpretation of the claim and the specification. Appropriate correction is required.
Claim 9 recites the limitation, “wherein the first bit is a least significant bit for the weight, and” (Emphasis added). The term “least significant” bits or address locations in byte addressing schemes is a known term of art. However, in this context, the byte addressing scheme is undefined and therefore the bits indices of the address is also undefined. This would lead to one of ordinary skill in the art to be unsure as to what the locations in the address and/or how the “least significant” is determined and/or used in this claim. Therefore, it is unclear as to what the claimed “least significant” is or pertains to and as a result this claim is rejected under 35 U.S.C. 112(b) for being indefinite. For examination purposes, the term “least significant” will be interpreted to mean a specified bit in a designated index of the binary number which is defined as a significant bit. Appropriate correction is required.
Claim 9 further recites the limitation, “wherein the N+Mth bit is a most significant bit for the weight.” (Emphasis added). The term “most significant” bits or address locations in byte addressing schemes is a known term of art. However, in this context, the byte addressing scheme is undefined and therefore the bits indices of the address is also undefined. This would lead to one of ordinary skill in the art to be unsure as to what the locations in the address and/or how the “most significant” is determined and/or used in this claim. Therefore, it is unclear as to what the claimed “most significant” is or pertains to and as a result this claim is rejected under 35 U.S.C. 112(b) for being indefinite. For examination purposes, the term “most significant” will be interpreted to mean a specified bit in a designated index of the binary number which is defined as a significant bit. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al, (Park et al, “THRESHOLD VARIATION COMPENSATION OF NEURONS IN SPIKING NEURAL NETWORKS”, US 2022/0058480 A1, Filed Dec. 2nd, 2020, hereinafter “Park”) in view of Beidas et al, (Beidas et al, “SPIKING NEURON CIRCUITS AND METHODS”, US 2023/0100670 A1, Filed Sep. 24th, 2021, hereinafter “Beidas”).
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Regarding claim 1, Park discloses, “first and second current source arrays controlled based on a weight memory;” (Fig. 4; As seen in the figure, Park discloses a synapse array contains multiple sets of synapses in an array. The different neurons inputs are propagated to one or more synapse in the array and processed. Further as known in the art, the synapses are used to weight the incoming spikes during processing before the spike is propagated further.)
“a membrane capacitor;” (Detailed Description, pp. 5, [0071]; “As the current is inputted in each input event, the membrane potential of the membrane capacitor 11 is charged. When the membrane potential reaches threshold, the membrane capacitor 11 discharges the same and constant amount by the discharge NMOS transistor 15a immediately after the spike generation in each event. That is, the differences in the membrane potential among input events are maintained between before and after discharging.” Park discloses the use of a membrane capacitor and uses it to accumulate signals before propagating a new signal or pulse.)
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“a first switch configured to deliver a first calculation signal generated from the first current source array to the membrane capacitor, in response to the first modulation pulse; and” (Fig 4; As seen in figure 4 this system contains a multitude of weighted synapses used to process input signals. These signals are then propagated and evaluated by neurons. In this publication the neurons contain switches and capacitors to process signals further.) and (Figure 5; This figure discloses the neuron used to process the spikes received from the synapse array. The figure discloses a firing unit which contains circuitry to calculate and modify the input spike. This will deliver a calculated pulse to reference 15 which is a membrane capacitor. This teaches a system which can deliver a calculated pulse after receiving a spike from a synapse array and deliver that calculated spike to the membrane capacitor.)
“a second switch configured to deliver a second calculation signal generated from the second current source array to the membrane capacitor, in response to the second modulation pulse.” (Fig 4; As seen in figure 4 this system contains a multitude of weighted synapses used to process input signals. These signals are then propagated and evaluated by neurons. In this publication the neurons contain switches and capacitors to process signals further.) and (Figure 5; This figure discloses the neuron used to process the spikes received from a multitude synapse of synapses. As disclosed in figures 4 and 5, the system is designed to use one or more synapses, interpreted to be the current source arrays. These are connected to one or more neurons, which are interpreted to be the switches. The figure discloses a firing unit which contains circuitry to calculate and modify the input spike. This will deliver a calculated pulse to reference 15 which is a membrane capacitor. This teaches a system which can deliver a calculated pulse after receiving a spike from a synapse array and deliver that calculated spike to the membrane capacitor.)
Park fails to explicitly disclose:
“A spike neural network circuit, comprising:”
“a pulse generator configured to receive a single input spike signal, and to generate a first modulation pulse and a second modulation pulse activated during times of different lengths based on the single input spike signal;”
However, Beidas discloses, “A spike neural network circuit, comprising:” (Detailed Description, pp. 19, [0207]; “The computing system 1300 may include components which may include hardware components and/or software components. The computing system may include one or more processors 1301, e.g. a graphics processing unit 1302, a hardware acceleration unit 1303, a neuromorphic processing unit 1304, and a central processing unit 1305. The one or more processors 1301 may be implemented in one processing unit, e.g. a system on chip (SOC), or a processor.” This application discloses a neuromorphic circuit for deploying a spiking neural network.)
“a pulse generator configured to receive a single input spike signal, and to generate a first modulation pulse and a second modulation pulse activated during times of different lengths based on the single input spike signal;” (Detailed Description, pp. 7, [0083 -0084]; “The spike detector 502 may include any type of spike or pulse detector that may detect an input spike signal via various methods such as threshold-based detection. The spike detector 502 may include analog circuits or digital circuits that are configured to detect a spike signal. The spike detector 502 may include a plurality of spike detecting elements coupled to the plurality of inputs 501. The spike detector 502 may provide the above-mentioned indications in various manners. The spike detector 502 may be coupled to another component and/or circuit via different signal paths corresponding to each of the plurality of inputs 501, and the spike detector 502 may provide an output signal (e.g. a pulse signal) to another component and/or circuit from the respective signal paths corresponding to one or more inputs from the plurality of inputs 501, which the spike detector 502 has detected an input spike signal to provide the received spike input indication. The spike detector 502 may include a trigger circuit that is configured to provide a trigger signal (e.g. a pulse signal) indicating detection of at least one received input spike signal from the plurality of inputs 502 at an instance of time to provide the received spike indication.” This publication discloses a spiking neural network with neuron which contains a spike detector. This detector is able to input a spike in a SNN and generate an output pulse based on the input. This discloses the use of threshold based detection which indicates receiving spikes of different magnitudes and varying lengths of time.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Park and Beidas. Park teaches spiking neural network architecture that contains neurons and is able to modulate the neural thresholds and values. Beidas teaches spiking neural network circuits that contains a spike detector and generator able to modulate multiple spikes from input spikes. One of ordinary skill would have motivation to combine a spiking neural network system able to house specialize neuromorphic circuits with a specialized neuromorphic circuit able to modulate the spikes and output variable spikes, “The spiking neuron may further include a pulse controller 1207 coupled to the triggerable oscillator 1206 to receive the oscillator signal and configured to provide pulse signals from its output based on the oscillator signal. The pulse controller 1207 may receive a leakage frequency control signal from a leakage frequency input 1208 indicating a desired repetition frequency for the leakage function, and the pulse controller 1207 may output the pulse signals with a pulse repetition frequency indicated by the leakage frequency control signal. The pulse repetition frequency may be defined according to a desired leakage response during the design of the neural network. The pulse repetition frequency may be referred to as leakage frequency in this disclosure. Furthermore, the pulse controller 1207 may receive a leakage control signal from a leakage enable input 1209, and the pulse controller 1207 may provide an indication to a leakage controller 1210 based on the leakage enable input to activate or deactivate the leakage controller 1210.” (Beidas, Detailed Description, pp. 18, [0192]).
Regarding claim 5, Park discloses, “wherein a first current source for generating a current of a smallest magnitude among current sources of the first current source array generates a current of the same magnitude as a second current source for generating a current of a smallest magnitude among current sources of the second current source array.” (Detailed Description, pp. 4, [0051]; “The method for discharging the membrane potential of the present inventive concept discharges the membrane potential by the same amount (the amount of the target threshold (
V
t
h
0
)) in all neurons immediately after the spike generation. Thus, the amount of the membrane potential to be charged for the next spike generation are the same as the target threshold (
V
t
h
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) in all neurons, thereby the threshold difference and/or variation among neurons are compensated.” This discloses that the output of on neuron after processing can be the same value as other neurons. Using the BRI of the claims, this would mean this system could produce generate a current of equally small values as other neurons in the network based on a defined threshold potential.)
Regarding claim 10, Park discloses, “a neuron circuit configured to generate an output spike signal, when a voltage level of the membrane capacitor is higher than a threshold voltage level.” (Detailed Description, pp. 6, [0070]; “The spike generation block 303 may be configured to generate a spike signal to be transmitted to a post-synaptic neuron when the membrane potential of the neuron 300 reaches a membrane threshold of the neuron 300. The spike generation block 303 may include a comparator configured to compare the membrane potential of the neuron 300 and a predefined membrane potential threshold value.” As stated, this system will generate an output spike when a certain threshold is met, or overcome, at the membrane capacitor.)
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Regarding claim 12, Park discloses, “a first current source and a second current source;” (Fig. 4; As seen in the figure, Park discloses a synapse array contains multiple sets of synapses in an array. The different neurons inputs are propagated to one or more synapse in the array and processed. Further as known in the art, the synapses are used to weight the incoming spikes during processing before the spike is propagated further.)
“a first weight switch connected between the first current source and a first node and a second weight switch connected between the second current source and a second node;” (Fig 4; As seen in figure 4 this system contains a multitude of weighted synapses used to process input signals. These signals are then propagated and evaluated by neurons. In this publication the neurons contain switches and capacitors to process signals further.) and (Figure 5; This figure discloses the neuron used to process the spikes received from the synapse array. The figure discloses a firing unit which contains circuitry to calculate and modify the input spike. This will deliver a calculated pulse to reference 15 which is a membrane capacitor. This teaches a system which can deliver a calculated pulse after receiving a spike from a synapse array and deliver that calculated spike to the membrane capacitor.)
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“a first switch connected between the first node and an output line and configured to operate in response to the first modulation pulse;” (Detailed Description, pp. 5, [0067]; “FIG. 7 is an example that the threshold adjusting unit 15 comprises a plurality of transistors 15a, 15b, 15c. In this example, with the discharge NMOS transistor 15a, a pass PMOS transistor 15b and a discharge PMOS transistor 15c separating the firing unit (neuron) 13 and the accumulation unit 11, the discharge NMOS transistor 15a can discharge the membrane capacitor 11.” This system discloses a system that is able to use a firing module that contains circuitry able to output a modulated spike to the output line based on the input pulse.)
“a second switch connected between the second node and the output line and configured to operate in response to the second modulation pulse; and” (Detailed Description, pp. 5, [0067]; “FIG. 7 is an example that the threshold adjusting unit 15 comprises a plurality of transistors 15a, 15b, 15c. In this example, with the discharge NMOS transistor 15a, a pass PMOS transistor 15b and a discharge PMOS transistor 15c separating the firing unit (neuron) 13 and the accumulation unit 11, the discharge NMOS transistor 15a can discharge the membrane capacitor 11.” This system discloses a system that is able to use a firing module that contains circuitry able to output a modulated spike to the output line based on the input pulse. As seen in Fig.5, there is a plurality of firing using connected to a plurality of synapses. This teaches an array of n synapse connected to n firing units containing circuitry able to manage and modulate input spikes and pulse.)
“a membrane capacitor connected with the output line.” (Detailed Description, pp. 5, [0071]; “As the current is inputted in each input event, the membrane potential of the membrane capacitor 11 is charged. When the membrane potential reaches threshold, the membrane capacitor 11 discharges the same and constant amount by the discharge NMOS transistor 15a immediately after the spike generation in each event. That is, the differences in the membrane potential among input events are maintained between before and after discharging.” Park discloses the use of a membrane capacitor and uses it to accumulate signals before propagating a new signal or pulse.)
Park fails to explicitly disclose:
“A spike neural network circuit, comprising:”
“a pulse generator configured to receive a single input spike signal and generate first and second modulation pulses activated during times of different lengths based on the single input spike signal;”
However, Beidas discloses, “A spike neural network circuit, comprising:” (Detailed Description, pp. 19, [0207]; “The computing system 1300 may include components which may include hardware components and/or software components. The computing system may include one or more processors 1301, e.g. a graphics processing unit 1302, a hardware acceleration unit 1303, a neuromorphic processing unit 1304, and a central processing unit 1305. The one or more processors 1301 may be implemented in one processing unit, e.g. a system on chip (SOC), or a processor.” This application discloses a neuromorphic circuit for deploying a spiking neural network.)
“a pulse generator configured to receive a single input spike signal and generate first and second modulation pulses activated during times of different lengths based on the single input spike signal;” (Detailed Description, pp. 7, [0083 -0084]; “The spike detector 502 may include any type of spike or pulse detector that may detect an input spike signal via various methods such as threshold-based detection. The spike detector 502 may include analog circuits or digital circuits that are configured to detect a spike signal. The spike detector 502 may include a plurality of spike detecting elements coupled to the plurality of inputs 501. The spike detector 502 may provide the above-mentioned indications in various manners. The spike detector 502 may be coupled to another component and/or circuit via different signal paths corresponding to each of the plurality of inputs 501, and the spike detector 502 may provide an output signal (e.g. a pulse signal) to another component and/or circuit from the respective signal paths corresponding to one or more inputs from the plurality of inputs 501, which the spike detector 502 has detected an input spike signal to provide the received spike input indication. The spike detector 502 may include a trigger circuit that is configured to provide a trigger signal (e.g. a pulse signal) indicating detection of at least one received input spike signal from the plurality of inputs 502 at an instance of time to provide the received spike indication.” This publication discloses a spiking neural network with neuron which contains a spike detector. This detector is able to input a spike in a SNN and generate an output pulse based on the input. This discloses the use of threshold based detection which indicates receiving spikes of different magnitudes and varying lengths of time.)
Claims 2, 3, 4, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Beidas in view of Werner et al, (Werner et al, “MODULATION DEVICE AND METHOD, ARTIFICIAL SYNAPSE COMPRISING SAID MODULATION DEVICE, SHORT TERM PLASTICITY METHOD IN AN ARTIFICIAL NEURAL NETWORK COMPRISING SAID ARTIFICIAL SYNAPSE”, US 11,551,073 B2, Filed Dec. 4th, 2017, hereinafter “Werner”).
Regarding claim 2, Werner discloses, “wherein the first modulation pulse is activated for a shorter time than the second modulation pulse.” (Detailed Description of at least one Embodiment of the Invention, Col. 5, Ln 33-50; “According to any of the embodiments, the control block Ct1 is able to: carry out a first modification of the equivalent conductance
y
i
(
t
)
upon receipt of each clock signal clk, and carry out a second modification of the equivalent conductance
y
i
(
t
)
upon receipt of each input pulse
V
i
n
. The first and second modifications are in opposite directions. Two particular cases are thus possible: either the first modification is an increase in the equivalent conductance and the second modification is a decrease in the equivalent conductance; or the first modification is a decrease in the equivalent conductance and the second modification is an increase in the equivalent conductance. The first modification that takes place at each clock signal clk is preferentially strictly less, in absolute value, than the second modification which takes place at each input pulse
V
i
n
.” Werner teaches a pulse modulation system for Spiking neural networks. This system is able to receive a pulse and generate pulse of different activations times. As stated, the first pulse is shorter than the second pulse.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Park, Beidas, and Werner. Park teaches spiking neural network architecture that contains neurons and is able to modulate the neural thresholds and values. Beidas teaches spiking neural network circuits that contains a spike detector and generator able to modulate multiple spikes from input spikes. Werner teaches a pulse modulation circuit that is able to intake a pulse and output multiple spikes of different currents to a network. One of ordinary skill would have motivation to combine a spiking neural network system able to house specialize neuromorphic circuits with a specialized neuromorphic circuit able to modulate the spikes and output variable spikes as well modulation module that is able to modulate signals. One of ordinary skill in the art could potentially use the overall spiking neural network architecture proposed in Park and modify the output pathways of the network with the circuitry proposed in Beidas and Werner, “The technical field of the invention is that of artificial neural networks, or neuromorphic circuits. The present invention relates to a modulation device and method, as well as an artificial synapse comprising said modulation device and a short term plasticity method in an artificial neural network comprising said artificial synapse. An application field of the present invention is notably signal processing, for example image processing or neural signal processing.” (Technical Field of the Invention, Col. 1)
Regarding claim 3, Werner discloses, “wherein the first modulation pulse and the second modulation pulse are activated from the same time point.” (Detailed Description of at least one embodiment of the invention, Col. 5, Ln 59-64; “The control block Ct1 thereby only emits two distinct types of electrical programming pulses. Each first modification of the equivalent conductance
y
i
(
t
)
is obtained thanks to one or more pulses of the first type, and each second modification of the equivalent conductance
y
i
(
t
)
is obtained thanks to one or more pulses of the second type. Werner discloses a system that will generate two destiny types of pulses. These two pulses are generated from the received single input signal at a given point in time. This teaches that both of the pulses are activated from the same time point or spike event.)
Regarding claim 4, Park discloses, “wherein the membrane capacitor is configured to: accumulate the first calculation signal during a time interval when the first modulation pulse is activated; and” (Detailed Description, pp. 4, [0061]-[0062]; “The accumulation unit 11 of the neuron 10 time integrates and accumulates an input signal (e.g., current) from synapses (dendrite side) 20. The firing unit 13 connects to the accumulation unit 11, and when a charging voltage of the accumulation unit 11 exceeds the threshold by accumulating electric charges, the neuron fires to generate a spike.” This system discloses neurons that are able to store pulses over times and fire when a threshold is met. This will accumulate signals calculated from the firing unit, see fig. 4, and propagate a signal when a threshold is met.)
“accumulate the second calculation signal during a time interval when the second modulation pulse is activated.” (Detailed Description, pp. 4, [0061]-[0062]; “The accumulation unit 11 of the neuron 10 time integrates and accumulates an input signal (e.g., current) from synapses (dendrite side) 20. The firing unit 13 connects to the accumulation unit 11, and when a charging voltage of the accumulation unit 11 exceeds the threshold by accumulating electric charges, the neuron fires to generate a spike.” As seen in figure 4, this system contains a multitude of neurons connected to synapse in an array. The multitude of synapses will propagate multiple signals to multiple different neurons and firing units to process and store the calculated pulses. Finally, the examiner would like to note that figure 5, see fig. 5, discloses “synapses” as in plural number of signals which can be propagates to the multiple firing units to process calculated pulses.)
Regarding claim 13, Werner discloses, “wherein the first modulation pulse is activated for a shorter time than the second modulation pulse.” (Detailed Description of at least one Embodiment of the Invention, Col. 5, Ln 33-50; “According to any of the embodiments, the control block Ct1 is able to: carry out a first modification of the equivalent conductance
y
i
(
t
)
upon receipt of each clock signal clk, and carry out a second modification of the equivalent conductance
y
i
(
t
)
upon receipt of each input pulse
V
i
n
. The first and second modifications are in opposite directions. Two particular cases are thus possible: either the first modification is an increase in the equivalent conductance and the second modification is a decrease in the equivalent conductance; or the first modification is a decrease in the equivalent conductance and the second modification is an increase in the equivalent conductance. The first modification that takes place at each clock signal clk is preferentially strictly less, in absolute value, than the second modification which takes place at each input pulse
V
i
n
.” Werner teaches a pulse modulation system for Spiking neural networks. This system is able to receive a pulse and generate pulse of different activations times. As stated, the first pulse is shorter than the second pulse.)
Regarding claim 14, Werner discloses, “wherein the first modulation pulse and the second modulation pulse are activated from the same time point.” (Detailed Description of at least one embodiment of the invention, Col. 5, Ln 59-64; “The control block Ct1 thereby only emits two distinct types of electrical programming pulses. Each first modification of the equivalent conductance
y
i
(
t
)
is obtained thanks to one or more pulses of the first type, and each second modification of the equivalent conductance
y
i
(
t
)
is obtained thanks to one or more pulses of the second type. Werner discloses a system that will generate two destiny types of pulses. These two pulses are generated from the received single input signal at a given point in time. This teaches that both of the pulses are activated from the same time point or spike event.)
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Beidas and Park in view of Morie et al, (Morie et al, “ARITHMETIC LOGIC UNIT, MULTIPLY-ACCUMULATE OPERATION DEVICE, MULTIPLY-ACCUMULATE OPERATION CIRCUIT, AND MULTIPLY-ACCUMULATE OPERATION SYSTEM”, US 11782680 B2, Filed Jul. 5th, 2019, hereinafter “Morie”).
Regarding claim 6, Morie discloses, “wherein the first current source and the second current source include a first transistor and a second transistor, respectively, and” (First Embodiment, Col. 14, In. 9-10; "The synapse circuit 8 includes a first MOS transistor 20a, a second MOS transistor 20b, and a flip-flop circuit 30." The synapse circuits in this mode also contains transistors.)
“wherein a channel width of the first transistor is configured to be same as a channel width of the second transistor.” (First Embodiment, Col. 14, Ln 34-39; "As the first MOS transistor 20a and the second MOS transistor 20b, for example, similar p-MOS transistors prepared on the basis of the same design parameters (gate width, gate length, etc.) are used. In this embodiment, the first MOS transistor 20a and the second MOS transistor 20b correspond to the weight unit." The parameters of this system requires that the synapse circuits and transistors are similar, this includes channel widths.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Park, Beidas, and Morie. Park teaches spiking neural network architecture that contains neurons and is able to modulate the neural thresholds and values. Beidas teaches spiking neural network circuits that contains a spike detector and generator able to modulate multiple spikes from input spikes. Morie teaches an analog spiking neural network system process operations using analog circuits. One of ordinary skill would have motivation to research multiple different types of spiking neural network architectures. This includes analog systems to execute potentially virtualized networks and/or combine different neuromorphic circuits, as disclosed in Beidas, with the architecture of Morie, “FIG. 14 is a schematic diagram showing a specific con- 50 figuration example of the arithmetic logic unit 200. FIG. 14 shows an arrangement example of circuits for realizing the arithmetic logic unit 200 shown in FIG. 12, for example, and a plurality of analog circuits 203 provided in one layer of the arithmetic logic unit 200 is schematically illustrated. The analog circuits 203 each include the pair of output lines 7, a plurality of synapse circuits 208, and a neuron circuit 209. As shown in FIG. 14, the arithmetic logic unit 200 is a circuit having a crossbar configuration (see FIG. 3) 55 in which the input signal lines 6 and the respective output 60 lines 7 are arranged perpendicular to each other. Further, in the arithmetic logic unit 200, the positive input signal line 6a and the negative input signal line 6b are connected to each of the synapse circuits 208.” (Morie, Second Embodiment, Col. 27, Ln. 50-64)
Regarding claim 16, Morie discloses, “a weight memory storing a binary weight,” (Brief description of the figures, pp. 3, [0042]; "The synapse 121 may include a current source 11, a transistor M1, and a weight memory WM1. The weight memory WM1 may store a weight bit corresponding to a weight W1." The weights in this system store bit values. Using the broadest reasonable interpretation, a bit is considered a binary form of a number.)
“wherein the first weight switch operates based on a first bit of the binary weight, and the second weight switch operates based on a second bit of the binary weight.” (Figure 6, pp. 7; This figure shows the different weights in the synapse zone. As interpreted above, this figure shows a sequential order of the weights in the zone starting with WMk through WMm.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Park, Beidas, and Morie. Park teaches spiking neural network architecture that contains neurons and is able to modulate the neural thresholds and values. Beidas teaches spiking neural network circuits that contains a spike detector and generator able to modulate multiple spikes from input spikes. Morie teaches an analog spiking neural network system process operations using analog circuits. One of ordinary skill would have motivation to research multiple different types of spiking neural network architectures. This includes analog systems able represent weights in a neural network in binary form and still combine the neuromorphic circuits disclosed in Beidas with the analog system proposed in Morie, “FIG. 14 is a schematic diagram showing a specific con- 50 figuration example of the arithmetic logic unit 200. FIG. 14 shows an arrangement example of circuits for realizing the arithmetic logic unit 200 shown in FIG. 12, for example, and a plurality of analog circuits 203 provided in one layer of the arithmetic logic unit 200 is schematically illustrated. The analog circuits 203 each include the pair of output lines 7, a plurality of synapse circuits 208, and a neuron circuit 209. As shown in FIG. 14, the arithmetic logic unit 200 is a circuit having a crossbar configuration (see FIG. 3) 55 in which the input signal lines 6 and the respective output 60 lines 7 are arranged perpendicular to each other. Further, in the arithmetic logic unit 200, the positive input signal line 6a and the negative input signal line 6b are connected to each of the synapse circuits 208.” (Morie, Second Embodiment, Col. 27, Ln. 50-64)
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Park and Beidas in view of Yajima, (Yajima, “Ultra‑low‑power switching circuits based on a binary pattern generator with spiking neurons”, Jan. 21st, 2022, hereinafter “Yajima”).
Regarding claim 7, Park discloses, “wherein the weight memory is configured to store a weight in form of a binary number,” (Detailed Description, pp. 4, [0051]; “The synaptic weight block 301 may include, or may be coupled to, a memory configured to store information indicating a weight. Accordingly, the synaptic weight block 301 may determine the weight based on the information stored in the memory. Furthermore, the synaptic weight block 301 may be configured to determine different weights for a plurality of inputs that the synaptic weight block 301 is configured to receive input spike signals.” The weights used in the synapse are configured to be of specified values. This system is able to store the synapse in binary form in a computing memory system to retrieve for later inference.
“wherein current sources of the first and second current source arrays correspond to weight bits in the form of the binary number, respectively, and” (Detailed Description, pp. 4, [0052]; “In other words, the synaptic weight block 301 may be configured to determine a first weight for an input spike signal that the neuron 300 receives from a first pre-synaptic neuron and a second weight for an input spike signal that the neuron 300 receives from a second pre-synaptic neuron. For example, the synaptic weight block 301 may include a memory (e.g. registers) to store information indicating a weight for each of the plurality of inputs. The synaptic weight block 301 may be configured to provide an output signal to the integration block 302, which the output signal may indicate the determined (stored) weight of an input when the synaptic weight block 301 receives an input spike signal from that input.” The system in park is able to store values of weights in a computing system. This teaches that the weights of the synapses or current arrays are stored in a register or memory cell in binary form.)
Park and Beidas fail to explicitly disclose:
“wherein a time length ratio of the first modulation pulse being activated and the second modulation pulse being activated is determined based on a positional value of bits respectively corresponding to the current sources of the first current source array and a positional value of bits respectively corresponding to the current sources of the second current source array.”
However, Yajima discloses, “wherein a time length ratio of the first modulation pulse being activated and the second modulation pulse being activated is determined based on a positional value of bits respectively corresponding to the current sources of the first current source array and a positional value of bits respectively corresponding to the current sources of the second current source array.” (Simulation of spiking neuron circuit, pp. 5; "In this study, we fabricated a spiking neuron circuit, which is specially designed for waiting time generation in ultra-low power consumption. For the purpose of waiting time generation, the spiking neuron circuit implements the integrate-fire function while all the other biological functions were excluded intentionally. It is also designed to generate a nanosecond-width square pulse wave as the output spike for seamless connection with CMOS logic circuits with a common 1 V supply." This system is able to intake a spike and determine a delay for outputting that spike. This system allows for varying delay times which can include sending a spike based on the weight or voltage of the incoming spike.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Park, Beidas and Yajima. Park teaches spiking neural network architecture that contains neurons and is able to modulate the neural thresholds and values. Beidas teaches spiking neural network circuits that contains a spike detector and generator able to modulate multiple spikes from input spikes. Yajima teaches low power neuromorphic circuits able to be implemented in a spiking neural network. One of ordinary skill would have motivation to combine a spiking neural network system able to house specialize neuromorphic circuits with a specialized neuromorphic circuit able to modulate the spikes and output variable spikes with the circuit designs disclosed in Yajima to potential further modulate pulses based on different time delays, “In this way, we succeeded in experimentally generating an arbitrary waiting time spanning six orders of magnitude from 100 ns to 100 ms on the chip. The circuits and the device parameters for all the other waiting times are also summarized in Supplementary Note” (Yajima, Experiments on spiking neuron circuits, pp. 6)
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Park, Beidas, and Yajima in view of Ramesh et al, (Ramesh et al, “NEURON USING POSITS”, US 2022/0058471 A1, Filed, Aug. 19th, 2020, hereinafter “Ramesh”).
Regarding claim 8, Ramesh discloses, “wherein the weight in the form of the binary number includes first to N+Mth bits (where N is a natural number of 1 or more) corresponding to a sequential size,” (Detailed Description, pp. 11, [0099]; “These neuromorphic operations can be performed on data received by the neuromorphic memory array 530. In anticipation of the neural network being used to detect a particular event represented by the data or a pattern in the data, the neural network can receive a large amount of data (what may be referred to as analog weights 559 in FIG. 5B, described below) used to train the neural network (e.g., using the data sent to the neuron components 525). In one embodiment, as the data including bit strings is received, analog weights can be added to the data values in order to train the neural network for subsequent neuromorphic processing.” This article discloses the use of computing with neuromorphic chips and using binary numbers to store values of weights. This system will use a bit address to denote the different values of weights and data propagated throughout the network.)
“wherein the current sources of the first current source array correspond to the first to Nth bits, respectively,” (Detailed Description, pp. 2, [0026]; “A Type II unum can include n bits and can be described in terms of a "u-lattice" in which quadrants of a circular projection are populated with an ordered set of 2"- 3-1 real numbers. The values of the Type II unum can be reflected about an axis bisecting the circular projection such that positive values lie in an upper right quadrant of the circular projection, while their negative counterparts lie in an upper left quadrant of the circular projection.” The system proposed in this article will use a Type II unum system to represent the values of the weights and data. This bit addresses consists of n bit) and (Detailed Description, pp. 11, [0097]; “A learning event of a neural network operation can represent causal propagation of spikes among neurons, enabling a weight increase for the connecting synapses. A weight increase of a synapse can be represented by an increase in conductivity of a memory cell. A variable resistance memory array (for example a 3D cross-point or self-selecting memory (SSM) array) can mimic an array of synapses, each characterized by a weight, or a memory cell conductance. The greater the conductance, the greater the synaptic weight and the higher the degree of memory learning.” This teaches that the weights values are stored in memory in binary form. The weights values which are applied to the signals are processed with bit based on the location of the synapse in the array, i.e. different columns have different values.)
“wherein the current sources of the second current source array correspond to the N+ 1st to N+Mth bits, respectively, and” (Detailed Description, pp. 2, [0026]; “The values of the Type II unum can be reflected about an axis bisecting the circular projection such that positive values lie in an upper right quadrant of the circular projection, while their negative counterparts lie in an upper left quadrant of the circular projection. The lower half of the circular projection representing a Type II unum can include reciprocals of the values that lie in the upper half of the circular projection. Type II unums generally rely on a look-up table for most operations.” This system discloses a numbering scheme that is used to store weight values in a weight array. As stated in the previous limitation the weights have different weight values according to the location of the weights in the array. Further as stated in this citation, the Type II unum uses circular projection where the positive numbers and negative numbers are differentiated and values may be the n bit plus another value, i.e. m, to change the value of the weight.)
Park, Beidas, and Ramesh fail to explicitly disclose:
“wherein time length of the second modulation pulse being activated is 2N times of time length of the first modulation pulse being activated.”
However, Yajima discloses, “wherein time length of the second modulation pulse being activated is 2N times of time length of the first modulation pulse being activated.” (Simulation of spiking neuron circuit, pp. 5; "The fabricated spiking neuron circuit consists of two parts: one part generates waiting time, and the other part generates a spike (Fig. 3b). In the former part, the input current is created by the ON current or subthreshold current of the transistor under the application of 1 V, and charges the capacitor with the approximately constant current. Then, after a waiting time that is determined by the ratio of the capacitance to the current, the capacitor potential (Vl) reaches the threshold voltage of the inverter (around 0.5 V) and activates the spike generation part as shown in Fig. 3c." This system will generate a spike after a predetermined amount of time. This will intake a spike and wait before sending another spike of differing time lengths.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Park, Beidas, Yajima, and Ramesh. Park teaches spiking neural network architecture that contains neurons and is able to modulate the neural thresholds and values. Beidas teaches spiking neural network circuits that contains a spike detector and generator able to modulate multiple spikes from input spikes. Yajima teaches low power neuromorphic circuits able to be implemented in a spiking neural network. Ramesh teaches a system that is able to store neuromorphic weights and values to binary memory with byte addressing. One of ordinary skill would have motivation to combine a spiking neural network system able to house specialize neuromorphic circuits with a specialized neuromorphic circuit able to modulate the spikes and output variable spikes with the circuit designs disclosed in Yajima to potential further modulate pulses based on different time delays and with a system that is able to store the weights and synapse data disclosed in Park using the methods in Ramesh, ”Systems, apparatuses, and methods related to a neuron using posits are described. An example apparatus may include a memory array including a plurality of memory cells configured to store data. The data can include a plurality of bit strings. The example apparatus may include a neuron component coupled to the memory array. The neuron component can be configured to perform neuromorphic operations on at least one of the plurality of bit strings.” (Ramesh, Detailed Description, pp. 1, [0015])
Regarding claim 9, Ramesh discloses, “wherein the first bit is a least significant bit for the weight, and” (Detailed Description, pp. 8, [0080]; “FIG. 3 is an example of an n-bit universal number, or "unum" with es exponent bits. In the example of FIG. 3, then-bit unum is a posit bit string 331. As shown in FIG. 3, then-bit posit 331 can include a set of sign bit(s) (e.g., a sign bit 333), a set of regime bits (e.g., the regime bits 335), a set of exponent bits (e.g., the exponent bits 337), and a set of mantissa bits (e.g., the mantissa bits 339).” Fig. 3 in this application discloses the bit address example. As shown, the first bit is denoted as a significant bit.)
“wherein the N+Mth bit is a most significant bit for the weight.” (Detailed Description, pp. 8, [0080]; “The mantissa bits 339 can be referred to in the alternative as a "fraction portion" or as "fraction bits," and can represent a portion of a bit string (e.g., a number) that follows a decimal point.” As seen in Fig. 3, the first bit in the address is a significant bit and the remaining bits, consisting of a positions n + another value, i.e. m, holds specified values for specified bit indices in the address.)
Claims 11, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Park, Bedias, and Yajima in view of Garg et al, (Garg et al, “Spiking Neuron Computation With the Time Machine”, Apr. 2012, hereinafter “Garg”).
Regarding claim 11, Beidas discloses, “a first pulse output unit configured to output the first modulation pulse activated before a time point when the counted value is greater than a first reference value from a time point when the single input spike signal is received; and” (Detailed Description, pp. 4, [0054]; “The neuron 300 may provide an output spike signal in response to the value of the predefined metric reaching a predefined threshold. Received input spike signals may adjust the value of the predefined metric based on the corresponding weights for each of the received input spike signal. When the applied weight is an excitatory weight (i.e. when the input spike signal is excitatory), the integration block 302 may adjust the value of the predefined metric towards the predefined threshold according to the scale of the weight.” This system will generate a pulse based on a first input spike. This system will produce an output spike after a point in time when a specified, and modifiable, threshold is met. This system will look up the reference threshold and compare it to the current value stored and fire when the threshold is met.)
Park and Beidas fail to explicitly disclose:
“a clock generator configured to generate a clock signal in response to the single input spike signal;”
“a counter configured to count the number of times the clock signal toggles;”
“a second pulse output unit configured to output the second modulation pulse activated before a time point when the counted value is greater than a second reference value from the time point when the single input spike signal is received.”
However, Garg discloses, “a clock generator configured to generate a clock signal in response to the single input spike signal;” (Asynchronous Counter Design, pp. 145; "The transistor count grows linearly with n. Each counter block shares a global count direction signal and a global clock." This neural network circuit contains a clock and counter. This will generate bit based on the clock and counter value.)
“a counter configured to count the number of times the clock signal toggles;” (Asynchronous Counter Design, pp. 145; "The transistor count grows linearly with n. Each counter block shares a global count direction signal and a global clock. The central idea of the counter is that each bit tells the higher bit when to toggle and the higher bit tells the lower bit when its saturated and cannot toggle anymore." This neural network circuit contains a clock and counter. This will generate bit based on the clock and counter value.)
Park, Beidas, and Garg fail to explicitly disclose:
“a second pulse output unit configured to output the second modulation pulse activated before a time point when the counted value is greater than a second reference value from the time point when the single input spike signal is received.”
However, Yajima discloses, “a second pulse output unit configured to output the second modulation pulse activated before a time point when the counted value is greater than a second reference value from the time point when the single input spike signal is received.” (Simulation of spiking neuron circuit, pp. 5; "The fabricated spiking neuron circuit consists of two parts: one part generates waiting time, and the other part generates a spike (Fig. 3b). In the former part, the input current is created by the ON current or subthreshold current of the transistor under the application of 1 V, and charges the capacitor with the approximately constant current. Then, after a waiting time that is determined by the ratio of the capacitance to the current, the capacitor potential (Vl) reaches the threshold voltage of the inverter (around 0.5 V) and activates the spike generation part as shown in Fig. 3c." This system will generate a spike after a predetermined amount of time. This will intake a spike and wait before sending another spike.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Park, Beidas, Yajima, and Garg. Park teaches spiking neural network architecture that contains neurons and is able to modulate the neural thresholds and values. Beidas teaches spiking neural network circuits that contains a spike detector and generator able to modulate multiple spikes from input spikes. Yajima teaches low power neuromorphic circuits able to be implemented in a spiking neural network. Garg teaches a neural network neuron that utilizes clock and counter analog components. One of ordinary skill would have motivation to combine a spiking neural network system able to house specialize neuromorphic circuits with a specialized neuromorphic circuit able to modulate the spikes. Further one would be able to swap and switch components of Park and Beidas, such as different neurons, with elements and circuitry proposed in Yajima and Garg to implement digital and analog neural architecture, “A major advantage of the TM is that of allowing weights to be set independently and digitally for each connection. This solves the problem of storing weights at dedicated synapses in a neuron array. Since these weights are stored digitally, they are easier to compute and store, as compared to setting analog biases as weights. The TM provides flexibility for routing spikes by allowing arbitrary configurable and recurrent connections between neurons that can be set at the beginning of the computation or changed on the fly as compared to dedicated hardware synapses. The hardware design of the architecture allows for swapping of the low-power integrate-and-fire neuron with any other neuron model which accepts a synaptic injection current directly on to the membrane capacitor.” (Garg, Scaling and Comparison, pp. 153)
Regarding claim 17, Yajima discloses, “a first latch circuit including a first set terminal for receiving the single input spike signal, a first reset terminal, and a first output terminal;” (Figure 1c, pp. 2; This system contains multiple latch gates. This is seen in this figure. The input lint is connected to the S terminal, as well as the output of the gate connects the rest terminal.)
“a second latch circuit including a second set terminal for receiving the first control signal, a second reset terminal for receiving the second control signal, and a second output terminal for outputting the first modulation pulse; and” (figure 1c, pp. 2; This figure shows the use of multiple later gates. These gates are used to send a pulse after a designated amount of time. As seen in the image, the second latch gate inputs the output of the previous in the S terminal and the output of the gate is connected to the Reset terminal.)
“a third latch circuit including a third set terminal for receiving the third control signal, a fourth reset terminal for receiving the fourth control signal, and a third output terminal for outputting the second modulation pulse,” (Figure 1c, pp. 2; "A binary pattern generator, a specially designed pattern generator for purpose of controlling switching circuits. It consists of a chain of waiting time generators with a wide range of preprogrammed waiting times." The description of this figure discloses the use of a chain of set-reset latch gates. These can be connected in sequence to each other and are portable to other parts of the circuit.)
“wherein the first reset terminal is configured to receive the fourth control signal.” (Figure 1c, pp. 2; This system contains multiple latch gates. This is seen in this figure. The input lint is connected to the S terminal, as well as the output of the gate connects the rest terminal.)
Park, Beidas, and Yajima fails to explicitly disclose:
“a clock generator connected with the first output terminal and configured to generate a clock signal;”
“a counter configured to receive the single input spike signal and count the number of times the clock signal toggles;”
“a first comparator configured to compare a value counted by the counter with a first reference value to generate first and second control signals;”
“a second comparator configured to compare the counted value with a second reference value to generate third and fourth control signals;”
However, Garg discloses, “a clock generator connected with the first output terminal and configured to generate a clock signal;” (Asynchronous Counter Design, pp. 145; "The transistor count grows linearly with n. Each counter block shares a global count direction signal and a global clock." This neural network circuit contains a clock and counter. This will generate bit based on the clock and counter value)
“a counter configured to receive the single input spike signal and count the number of times the clock signal toggles;” (Asynchronous Counter Design, pp. 145; "The transistor count grows linearly with n. Each counter block shares a global count direction signal and a global clock. The central idea of the counter is that each bit tells the higher bit when to toggle and the higher bit tells the lower bit when its saturated and cannot toggle anymore." This neural network circuit contains a clock and counter. This will generate bit based on the clock and counter value)
“a first comparator configured to compare a value counted by the counter with a first reference value to generate first and second control signals;” (Asynchronous counter design, pp. 145 "The central idea of the counter is that each bit tells the higher bit when to toggle and the higher bit tells the lower bit when its saturated and cannot toggle any more. When the higher bit is saturated, the lower bit does not ask the higher bit to toggle. Each bit has two input-output pairs to propagate the toggle and saturation information up and down the counter. For each nth counter the ith bit has an input from
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“a second comparator configured to compare the counted value with a second reference value to generate third and fourth control signals;” (Asynchronous counter design, pp. 145 "The central idea of the counter is that each bit tells the higher bit when to toggle and the higher bit tells the lower bit when its saturated and cannot toggle any more. When the higher bit is saturated, the lower bit does not ask the higher bit to toggle. Each bit has two input-output pairs to propagate the toggle and saturation information up and down the counter. For each nth counter the ith bit has an input from
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Regarding claim 18, Yajima discloses, “wherein the first control signal and the third control signal are activated at a time point when the single input spike signal fires,” (Introduction, pp. 2; "In order to generate the arbitrary waiting time and an output spike signal, a technique of spiking neuron circuits with integrate-and-fire function was adopted. The spiking neuron circuits were optimized solely for the purpose of waiting time generation based on the complementary metal oxide semiconductor (CMOS) technology, and any other biological function was not implemented intentionally." This system is able use circuits to intake a pulse or spike and then generate a new spike or pulse. This will send a spike or pulse after a designated amount of time.)
“wherein the second control signal is activated at a first time point when the counted value becomes greater than the first reference value, and” (Simulation of spiking neuron circuit, pp. 5; "It is also designed to generate a nanosecond-width square pulse wave as the output spike for seamless connection with CMOS logic circuits with a common 1 V supply. The fabricated spiking neuron circuit consists of two parts: one part generates waiting time, and the other part generates a spike (Fig. 3b). In the former part, the input current is created by the ON current or subthreshold current of the transistor under the application of 1 V, and charges the capacitor with the approximately constant current." A spike can be generated after a given amount of time. This output can be sent to an output line. This output line carries the spike to other circuits in the system. The broadest reasonable interpretation would teach that this circuit can take in a spike and generate a spike after baked in threshold.) And (Figure le, pp. 2; As seen in the figure, the latch gates can be placed in sequential circuits to get a determined amount of time. This teaches a portable unit able to be placed in different places of a neural circuit.)
“wherein the fourth control signal is activated at a second time point when the counted value becomes greater than the second reference value.” (Simulation of spiking neuron circuit, pp. 5; "It is also designed to generate a nanosecond-width square pulse wave as the output spike for seamless connection with CMOS logic circuits with a common 1 V supply. The fabricated spiking neuron circuit consists of two parts: one part generates waiting time, and the other part generates a spike (Fig. 3b). In the former part, the input current is created by the ON current or subthreshold current of the transistor under the application of 1 V, and charges the capacitor with the approximately constant current." A spike can be generated after a given amount of time. This output can be sent to an output line. This output line carries the spike to other circuits in the system. The broadest reasonable interpretation would teach that this circuit can take in a spike and generate a spike after baked in threshold.) And (Figure le, pp. 2; As seen in the figure, the latch gates can be placed in sequential circuits to get a determined amount of time. This teaches a portable unit able to be placed in different places of a neural circuit.)
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park, Beidas, and Werner in view of Yajima.
Regarding claim 15, Yajima discloses, “wherein a length of a time when the second modulation pulse is activated is 2N times (wherein N is a natural number of 1 or more) a length of a time when the first modulation pulse is activated.” (Simulation of spiking neuron circuit, pp. 5; "The fabricated spiking neuron circuit consists of two parts: one part generates waiting time, and the other part generates a spike (Fig. 3b). In the former part, the input current is created by the ON current or subthreshold current of the transistor under the application of 1V, and charges the capacitor with the approximately constant current. Then, after a waiting time that is determined by the ratio of the capacitance to the current, the capacitor potential (V1) reaches the threshold voltage of the inverter (around O .5 V) and activates the spike generation part as shown in Fig. 3c." This system is able to generate a spike or pulse after a determined amount of time. This time can be programmed to be any set length of time.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Park, Beidas, Yajima and Werner. Park teaches spiking neural network architecture that contains neurons and is able to modulate the neural thresholds and values. Beidas teaches spiking neural network circuits that contains a spike detector and generator able to modulate multiple spikes from input spikes. Yajima teaches low power neuromorphic circuits able to be implemented in a spiking neural network. Werner teaches a pulse modulation circuit that is able to intake a pulse and output multiple spikes of different currents to a network. One of ordinary skill would have motivation to combine a spiking neural network system able to house specialize neuromorphic circuits with a specialized neuromorphic circuit able to modulate the spikes and output variable spikes as well modulation module that is able to modulate signals. One of ordinary skill in the art could potentially use the overall spiking neural network architecture proposed in Park and modify the output pathways of the network with the circuitry proposed in Beidas, Werner, and Yajima, “The technical field of the invention is that of artificial neural networks, or neuromorphic circuits. The present invention relates to a modulation device and method, as well as an artificial synapse comprising said modulation device and a short term plasticity method in an artificial neural network comprising said artificial synapse. An application field of the present invention is notably signal processing, for example image processing or neural signal processing.” (Technical Field of the Invention, Col. 1)
Conclusion
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/PAUL M GALVIN-SIEBENALER/Examiner, Art Unit 2147
/HASSAN MRABI/Primary Examiner, Art Unit 2147
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