DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application, 18125581, filed 03/23/2023 claims foreign priority to CN202210296644.4, filed 03/24/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/05/2024 and 09/23/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
A. a scalar computing unit, a vector computing unit, a matrix computing unit, and a tensor computing unit as specified in claims 26 and 39
B. determine, based on the bit width D indicated by the exponent bit width field, a numerical range E corresponding to the first exponent field during coding, wherein Ei belongs to the numerical range E, and the numerical range E satisfies the following formula: E=(-1)Se x [2D-1, (2D-1)], wherein Se is a sign bit of Ei, and Se is 0 or 1 as specified in claims 29 and 42
C. wherein, when D is equal to 0, Ei=0, wherein, when D is equal to 1, the value of the first exponent field is Es={Se}, and Ei={Se, 1'b1}, and wherein, when D is greater than 1, the value of the first exponent field is Es={Se, TF[2:D]}, and Ei={Se, 1'b1, TF[2:D]}, wherein TF is an amplitude of Ei, 1'b1 is a most significant bit in TF, 1'b1 does not occupy a bit width in the first exponent field, and a bit width of the second exponent field is D+1, wherein TF[2: D] represents remaining bits in the TF except the most significant bit 1'b1, and a bit width occupied by the TF[2:D] in the first exponent field is D-1, and wherein, in Ei, when D is greater than or equal to 1, a next bit of Se is the most significant bit 1'b1 of TF, and 1'b1 represents 1-bit binary data with a value of 1 as specified in claims 30 and 43
D. wherein, when the first exponent field is all is and the first mantissa field is all 0s, the first sign field is 0 or 1, and the first floating point number is positive or negative 0, wherein, when the first exponent field is all is and the first mantissa field is not 0, the first sign field is 0 or 1, and the first floating point number is a subnormal value, wherein, when Se of the first exponent field is 0, TF is all is, and the first mantissa field is all 0s, the first sign field is 0 or 1, and the first floating point number is positive or negative infinity, and wherein, when Se of the first exponent field is 0, TF is all is, and the first mantissa field is not 0, the first sign field is 0 or 1, and the first floating point number is not a number as specified in claims 31 and 44
E. wherein a coding manner of the exponent bit width field is integer coding, wherein a bit width occupied by the exponent bit width field in the total bit width N is DW, and wherein the first processor is further configured to code, by using the integer coding, any value of 0 to
2
D
W
-
1
with the bit width DW occupied by the exponent bit width field, and wherein the bit width D is 0 to
2
D
W
-
1
as specified in claims 32 and 26
F. wherein a coding manner of the exponent bit width field is conventional prefix coding, wherein a bit width occupied by the exponent bit width field in the total bit width N is DW1 or DW2, and DW1 is less than DW2, and wherein the first processor is further configured to code, by using the conventional prefix coding, any one of K1 values with the bit width DW1 occupied by the exponent bit width field, or any one of K2 values with the bit width DW2 occupied by the exponent bit width field, and wherein a maximum value of the Ki values is less than a minimum value of the K2 values, and the bit width D belongs to the Ki values or the K2 values as specified in claims 33 and 47
G. wherein a coding manner of the exponent bit width field is unconventional prefix coding, wherein a bit width occupied by the exponent bit width field in the total bit width N is DW1 or DW2, and DW1 is less than DW2, and wherein the first processor is further configured to code, by using the unconventional prefix coding, any one of P1 values with the bit width DW1 occupied by the exponent bit width field, or any one of P2 values with the bit width DW2 occupied by the exponent bit width field, and wherein a minimum value of the Pi values is greater than a maximum value of the P2 values, and the bit width D belongs to the Pi values or the P2 values as specified in claims 34 and 48
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 36 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 36 recites “A non-transitory computer-readable storage medium, wherein the computer- readable storage medium stores a computer program, and when the computer program is executed by a computer or a processor, the computer program performs the method according to claim 25”. A method is normally performed by a device; therefore, it is unclear how a computer program performs the method according to claim 25. For purposes of examination, this is interpreted as “A non-transitory computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a computer or a processor, the computer or the processor performs the method according to claim 25”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 37 is rejected under 35 U.S.C. 101 because claimed invention is directed to a non-statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because they are drawn to software, per se. Claim 37 recites “A computer program, wherein the computer program comprises instructions, and when the computer program is executed by a computer or a processor, the computer or the processor is enabled for performing the method according to claim 25”. As claimed, the “program” is not embodied in hardware, such as a non-transitory computer-readable storage medium. Therefore, the claim may be reasonably interpreted as software alone, which lacks the necessary physical articles or objects to constitute a machine or manufacture within the meaning of 35 U.S.C. 101. As such, it fails to fall within a statutory category and is therefore directed to non-statutory subject matter.
Claims 25-48 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under Step 1, claims 25-35 a series of steps and, therefore, is a process. Claim 36 recites non-transitory computer-readable storage medium and, therefore, is an article of manufacture. Claim 37 recites a computer program. Claims 38-48 recite an apparatus and, therefore, is a machine.
Under Step 2A prong 1, claim 38 recites
An apparatus comprising:
a first processor configured to:
obtain a first floating point number, wherein the first floating point number comprises a first sign field, an exponent bit width field, a first exponent field, and a first mantissa field, and wherein the exponent bit width field is used for indicating a bit width D occupied by the first exponent field in a total bit width N of the first floating point number; and
obtain normalized data corresponding to the first floating point number based on the first sign field, the exponent bit width field, the first exponent field, and the first mantissa field, wherein the normalized data comprises a second sign field, a second exponent field, and a second mantissa field.
The above limitations of converting a first floating point number encoded in first format into a normalized floating-point format amounts to processing mathematical relationships/calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. The step of “obtain normalized data” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “a first processor”, nothing in the claim element precludes the step from practically being performed in the human mind. For example, but for the “a first processor” language, the claim encompasses manually converting a floating-point number in a “HiFloat” format into a normalized floating-point format as shown in Figure 2 and described in at least paragraphs [0103-0104] using pen and paper. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: a first processor configured to: obtain a first floating point number. However, the additional elements of “a first processor” is recited at a high-level of generality (i.e., as a generic computer component for executing a series of operations) such that it amounts to no more than mere instructions using a generic computer component or merely as a tool to implement the abstract idea or merely reciting the words “apply it” (or an equivalent) with the judicial exception. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2) for more information. The additional elements of “obtain a first floating point number” is merely adding insignificant extra-solution activity, i.e. mere data gathering and is also merely generally linking the use of a judicial exception to a particular technological environment or field of use by limiting the data gathering step to a particular type of data (i.e., a first floating point number comprising a first sign field, an exponent bit width field, a first exponent field, and a first mantissa field). See MPEP 2106.05(h) for more information. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 38 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first processor” is recited at a high-level of generality (i.e., as a generic computer component for executing a series of operations) such that it amounts to no more than mere instructions using a generic computer component or merely as a tool to implement the abstract idea or merely reciting the words “apply it” (or an equivalent) with the judicial exception. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2) for more information. The additional elements of “obtain a first floating point number” is merely adding insignificant extra-solution activity, i.e. mere data gathering and is also merely generally linking the use of a judicial exception to a particular technological environment or field of use by limiting the data gathering step to a particular type of data (i.e., a first floating point number comprising a first sign field, an exponent bit width field, a first exponent field, and a first mantissa field). See MPEP 2106.05(h) for more information. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claims 39-48 recite the same abstract idea as claim 38 by reason of dependence. Further, claim 39 recites further abstract idea of “participate in corresponding computation”; claim 40 recites further details of the abstract idea of obtaining the normalized data by “obtain, based on the first sign field, the second sign field in the normalized data; determine, based on the bit width D indicated by the exponent bit width field, the first exponent field and the first mantissa field from the first floating point number; and obtain, based on the first exponent field and the first mantissa field, the second exponent field and the second mantissa field in the normalized data”; claim 41 recites further details of the abstract idea of the normalized data “wherein a truth value corresponding to the normalized data satisfies the following formula:
X
=
(
-
1
)
S
x
2
E
i
+
E
c
X
(
1
+
M
)
, wherein X is a truth value corresponding to the normalized data, S is a value of the second sign field, wherein the value of the second sign field is the same as that of the first sign field, and S is 0 or 1, and wherein
E
i
is a value of the second exponent field,
E
c
is a preset exponent center and
M
is a value of the second mantissa field”; claim 42 recites further abstract idea of “determine, based on the bit width D indicated by the exponent bit width field, a numerical range E corresponding to the first exponent field during coding, wherein Ei belongs to the numerical range E, and the numerical range E satisfies the following formula: E=(-1)Se x [2D-1, (2D-1)], wherein Se is a sign bit of Ei, and Se is 0 or 1”; claim 43 recites further abstract idea of “wherein, when D is equal to 0, Ei=0, wherein, when D is equal to 1, the value of the first exponent field is Es={Se}, and Ei={Se, 1'b1}, and wherein, when D is greater than 1, the value of the first exponent field is Es={Se, TF[2:D]}, and Ei={Se, 1'b1, TF[2:D]}, wherein TF is an amplitude of Ei, 1'b1 is a most significant bit in TF, 1'b1 does not occupy a bit width in the first exponent field, and a bit width of the second exponent field is D+1, wherein TF[2: D] represents remaining bits in the TF except the most significant bit 1'b1, and a bit width occupied by the TF[2:D] in the first exponent field is D-1, and wherein, in Ei, when D is greater than or equal to 1, a next bit of Se is the most significant bit 1'b1 of TF, and 1'b1 represents 1-bit binary data with a value of 1”; claim 44 recites further abstract idea of “wherein, when the first exponent field is all is and the first mantissa field is all 0s, the first sign field is 0 or 1, and the first floating point number is positive or negative 0, wherein, when the first exponent field is all is and the first mantissa field is not 0, the first sign field is 0 or 1, and the first floating point number is a subnormal value, wherein, when Se of the first exponent field is 0, TF is all is, and the first mantissa field is all 0s, the first sign field is 0 or 1, and the first floating point number is positive or negative infinity, and wherein, when Se of the first exponent field is 0, TF is all is, and the first mantissa field is not 0, the first sign field is 0 or 1, and the first floating point number is not a number”; claim 45 recites further abstract idea of “code the first sign field, the exponent bit width field, the first exponent field, and the first mantissa field according to a value represented by the first data to obtain the first floating point number”; claim 46 recites further the abstract idea of “wherein a coding manner of the exponent bit width field is integer coding, wherein a bit width occupied by the exponent bit width field in the total bit width N is DW, and wherein the first processor is further configured to code, by using the integer coding, any value of 0 to
2
D
W
-
1
with the bit width DW occupied by the exponent bit width field, and wherein the bit width D is 0 to
2
D
W
-
1
”; claim 47 recites further abstract idea of “wherein a coding manner of the exponent bit width field is conventional prefix coding, wherein a bit width occupied by the exponent bit width field in the total bit width N is DW1 or DW2, and DW1 is less than DW2, and wherein the first processor is further configured to code, by using the conventional prefix coding, any one of K1 values with the bit width DW1 occupied by the exponent bit width field, or any one of K2 values with the bit width DW2 occupied by the exponent bit width field, and wherein a maximum value of the Ki values is less than a minimum value of the K2 values, and the bit width D belongs to the Ki values or the K2 values”; and claim 48 recites further details of the abstract idea of “wherein a coding manner of the exponent bit width field is unconventional prefix coding, wherein a bit width occupied by the exponent bit width field in the total bit width N is DW1 or DW2, and DW1 is less than DW2, and wherein the first processor is further configured to code, by using the unconventional prefix coding, any one of P1 values with the bit width DW1 occupied by the exponent bit width field, or any one of P2 values with the bit width DW2 occupied by the exponent bit width field, and wherein a minimum value of the Pi values is greater than a maximum value of the P2 values, and the bit width D belongs to the Pi values or the P2 values” which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular claims 40-41, 43-44 and 46-48 do not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea.
Under step 2A prong 2, claim 39 recites the following additional elements: wherein the first floating point number is used for data storage or data transfer, wherein the normalized data is used for being input to a computing unit, and wherein the computing unit comprises one or more of a scalar computing unit, a vector computing unit, a matrix computing unit, or a tensor computing unit; claim 42 recites the following additional elements: a second processor; and claim 45 recites the following additional elements: a second processor configured to: obtain first data, wherein the first data is a second floating point number in a format different from that of the first floating point number, or the first data is an uncoded operation result, and the operation result comprises a sign bit, an exponent, and a mantissa. However, the additional elements of “a computing unit, wherein the computing unit comprises one or more of a scalar computing unit, a vector computing unit, a matrix computing unit, or a tensor computing unit” in claim 39; “a second processor” in claim 42; and “a second processor” in claim 45 are recited at a high-level of generality (i.e., as a generic computer component for computing; and as a generic component for executing a series of operations) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words “apply it” (or an equivalent) with the judicial exception. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. The additional elements of “wherein the normalized data is used for being input” in claim 39; and “obtain first data, wherein the first data is a second floating point number in a format different from that of the first floating point number, or the first data is an uncoded operation result, and the operation result comprises a sign bit, an exponent, and a mantissa” in claim 45 are merely adding insignificant extra-solution activities, i.e. mere data gathering and are also merely generally linking the use of a judicial exception to a particular technological environment or field of use by limiting the data gathering step to a particular type of data (i.e., using normalized data as input for computation; and a second floating point number or operation result having a different format than the first floating-point number). See MPEP 2106.05(h) for more information. The additional elements of “wherein the first floating point number is used for data storage or data transfer” in claim 39 is also merely adding insignificant extra-solution activity. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under step 2B, claims 39, 42 and 45 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a computing unit, wherein the computing unit comprises one or more of a scalar computing unit, a vector computing unit, a matrix computing unit, or a tensor computing unit” in claim 39; “a second processor” in claim 42; and “a second processor” in claim 45 are recited at a high-level of generality (i.e., as a generic computer component for computing; and as a generic component for executing a series of operations) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea or merely reciting the words “apply it” (or an equivalent) with the judicial exception. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. The additional elements of “wherein the normalized data is used for being input” in claim 39; and “obtain first data, wherein the first data is a second floating point number in a format different from that of the first floating point number, or the first data is an uncoded operation result, and the operation result comprises a sign bit, an exponent, and a mantissa” in claim 45 are merely adding insignificant extra-solution activities, i.e. mere data gathering and are also merely generally linking the use of a judicial exception to a particular technological environment or field of use by limiting the data gathering step to a particular type of data (i.e., using normalized data as input for computation; and a second floating point number or operation result having a different format than the first floating-point number). See MPEP 2106.05(h) for more information. The additional elements of “wherein the first floating point number is used for data storage or data transfer” in claim 39 is also merely adding insignificant extra-solution activity. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Receiving or transmitting data over a network” and “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims do not amount to significantly more than the abstract idea.
Regarding claims 25-35, they are directed to a method practiced by the apparatus of claims 38-44, 46-48 and 45 respectively. All steps performed by the method of claims 25-35 would be practiced by the apparatus of claims 38-44, 46-48 and 45 respectively. Claims 38-44, 46-48 and 45 analysis applies equally to claims 25-35 respectively.
Regarding claim 36, it is directed to a non-transitory computer-readable storage medium storing a computer program when executed by a computer or a processor, the computer program performs the method according to claim 25. Claim 38 (or 25) analysis applies equally to claim 36.
Regarding claim 37, it is directed to a computer program comprising instructions that when executed by a computer or a processor, the computer or the processor performs the method according to claim 25. Claim 38 (or 25) analysis applies equally to claim 37.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 25-28, 33, 35-41, 45 and 47 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Tang et al. (US 20190042243 A1).
Regarding claim 38, Tang teaches an apparatus comprising:
a first processor configured to (Tang Figs. 3-5 and paragraphs [0063-0065, 0068] first processor - execution circuitry 411 or EFP decoding circuitry):
obtain a first floating point number, wherein the first floating point number comprises a first sign field, an exponent bit width field, a first exponent field, and a first mantissa field, and wherein the exponent bit width field is used for indicating a bit width D occupied by the first exponent field in a total bit width N of the first floating point number (Tang Figs. 1-4, 7 and paragraphs [0063-0065] “at least one source (SRC1) 401 is input into execution circuitry 411. For an instruction that is to perform an operation using EFP sources, the source(s) 401, 403 contain EFP data which is input into the execution circuitry”; first floating point number – EFP number; paragraph [0034] “In EFP encoding, there is a sign bit, a self-identifying field, one or more bits to represent an exponent range, and one or more bits to indicate a mantissa”; paragraphs [0036-0038] “when the bit following the sign bit is 0 (the self-identifying field), then the following 3 bits are used to represent the exponent range … when the two bits following the sign bit are 10, then the next 4 bits are used to represent the exponent range … when the two bits following the sign bit are 11, then the next 6 bits are used to represent the exponent range”; paragraph [0081] “At 701, what the exponent width is determined 701. Using FIG. 1 as an example, is the exponent width 4 bits, 6 bits, or 8 bits?”); and
obtain normalized data corresponding to the first floating point number based on the first sign field, the exponent bit width field, the first exponent field, and the first mantissa field, wherein the normalized data comprises a second sign field, a second exponent field, and a second mantissa field (Figs. 4-5 and 7 and paragraphs [0060, 0065, 0068] “EFP values are decoded (unpacked) into standard exponent and mantissa values. This decoding is tied to the encoding choice used by the EFP numbers of the instruction … EFP decoding circuitry 413 decodes any input EFP data into exponent and mantissa components … EFP decoding circuitry 501 and 502 decodes the EFP source data operands into real parts of exponents and mantissas”; paragraphs [0086] “an exponent and a mantissa value are determined based on the exponent value width”; paragraphs [0002, 0030]).
Regarding claim 39, Tang teaches all the limitations of claim 38 as stated above. Further, Tang teaches wherein the first floating point number is used for data storage or data transfer, wherein the normalized data is used for being input to a computing unit to participate in corresponding computation, and wherein the computing unit comprises one or more of a scalar computing unit, a vector computing unit, a matrix computing unit, or a tensor computing unit (Tang Figs. 3-5 and paragraphs [0057, 0063] “execution circuitry to process an instruction utilizing EFP data … One or more of the operands (e.g., source(s) or destination) is to store EFP data”; paragraphs [0066, 0069-0070, 0072] “the decoded exponent and mantissa components are provided to logical and/or arithmetic circuitry 415 … the operands are packed data ( e.g., vector or SIMD registers)”).
Regarding claim 40, Tang teaches all the limitations of claim 38 as stated above. Further, Tang teaches wherein the first processor is specifically configured to:
obtain, based on the first sign field, the second sign field in the normalized data (Tang paragraph [0035]);
determine, based on the bit width D indicated by the exponent bit width field, the first exponent field and the first mantissa field from the first floating point number (Tang Figs. 1-2 and 7; paragraphs [0036-0038, 0081, 0086]); and
obtain, based on the first exponent field and the first mantissa field, the second exponent field and the second mantissa field in the normalized data (Tang paragraphs [0060, 0086]).
Regarding claim 41, Tang teaches all the limitations of claim 40 as stated above. Further, Tang teaches
wherein a truth value corresponding to the normalized data satisfies the following formula:
X
=
(
-
1
)
S
x
2
E
i
+
E
c
X
(
1
+
M
)
, wherein X is a truth value corresponding to the normalized data, S is a value of the second sign field, wherein the value of the second sign field is the same as that of the first sign field, and S is 0 or 1, and wherein
E
i
is a value of the second exponent field,
E
c
is a preset exponent center and
M
is a value of the second mantissa field (Tang paragraphs [0002, 0030, 0036-0038]).
Regarding claim 45, Tang teaches all the limitations of claim 41 as stated above. Further, Tang teaches
wherein the apparatus further comprises a second processor configured to (Tang Figs. 1-2 and 4-5; paragraphs [0067, 0071] second processor – encoding circuit):
obtain first data, wherein the first data is a second floating point number in a format different from that of the first floating point number, or the first data is an uncoded operation result, and the operation result comprises a sign bit, an exponent, and a mantissa (Tang Figs. 1-2 and 4-5; paragraphs [0067, 0071] first data – operation result); and
code the first sign field, the exponent bit width field, the first exponent field, and the first mantissa field according to a value represented by the first data to obtain the first floating point number (Tang Figs. 1-2 and 4-5; paragraphs [0067, 0071]).
Regarding claim 47, Tang teaches all the limitations of claim 38 as stated above. Further, Tang teaches wherein a coding manner of the exponent bit width field is conventional prefix coding, wherein a bit width occupied by the exponent bit width field in the total bit width N is DW1 or DW2, and DW1 is less than DW2, and wherein the first processor is further configured to code, by using the conventional prefix coding, any one of K1 values with the bit width DW1 occupied by the exponent bit width field, or any one of K2 values with the bit width DW2 occupied by the exponent bit width field, and wherein a maximum value of the K1 values is less than a minimum value of the K2 values, and the bit width D belongs to the K1 values or the K2 values (Tang Figs. 1-2 and paragraphs [0036-0038, 0046-0048] DW1 -1; DW2 – 2; any one of K1 values – 0; any one of K2 values – 10, 11).
Regarding claims 25-28, 33 and 35, they are directed to a method practiced by the apparatus of claims 38-41, 47 and 45 respectively. All steps performed by the method of claims 25-28, 33 and 35 would be practiced by the apparatus of claims 38-41, 47 and 45 respectively. Claims 38-41, 47 and 45 analysis applies equally to claims 25-28, 33 and 35 respectively.
Regarding claim 36, it is directed to a non-transitory computer-readable storage medium storing a computer program when executed by a computer or a processor, the computer program performs the method according to claim 25. Claim 38 (or 25) analysis applies equally to claim 36.
Regarding claim 37, it is directed to a computer program comprising instructions that when executed by a computer or a processor, the computer or the processor performs the method according to claim 25. Claim 38 (or 25) analysis applies equally to claim 37.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 32 and 46 are rejected under 35 U.S.C. 103 as being unpatentable over Tang as applied to claims 25 and 38 above, and further in view of Serodio (NPL - “Unum Type-IV: A Floating-Point Unit with Dynamically Varying Exponent and Mantissa Sizes”).
Regarding claim 46, Tang teaches all the limitations of claim 38 as stated above.
Tang does not explicitly teach wherein a coding manner of the exponent bit width field is integer coding, wherein a bit width occupied by the exponent bit width field in the total bit width N is DW, and wherein the first processor is further configured to code, by using the integer coding, any value of 0 to
2
D
W
-
1
with the bit width DW occupied by the exponent bit width field, and wherein the bit width D is 0 to
2
D
W
-
1
.
However, on the same field of endeavor, Serodio discloses wherein a coding manner of an exponent bit width field is integer coding, wherein a bit width occupied by the exponent bit width field in the total bit width N is DW, and coding, by using the integer coding, any value of 0 to
2
D
W
-
1
with the bit width DW occupied by the exponent bit width field, and wherein the bit width D is 0 to
2
D
W
-
1
(Serodio section 3.1 page 13-14; Fig. 3.1 Equations (3.2) an exponent bit width – Exponent size; “The Exponent Size (Exp Size) is a small unsigned integer, which has a width defined by the parameter EXP_SZ_W, and can assume a value in the range from 0 to
2
E
X
P
_
S
Z
_
W
-
1
”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tang using Serodio and configure the exponent bit width field to be coded using integer coding to allow for tapered accuracy and higher accuracy for numbers that are close to 1 (Serodio section 3.1 page 14).
Therefore, the combination of Tang as modified in view of Serodio teaches wherein a coding manner of the exponent bit width field is integer coding, wherein a bit width occupied by the exponent bit width field in the total bit width N is DW, and wherein the first processor is further configured to code, by using the integer coding, any value of 0 to
2
D
W
-
1
with the bit width DW occupied by the exponent bit width field, and wherein the bit width D is 0 to
2
D
W
-
1
.
Regarding claim 32, it is directed to a method practiced by the apparatus of claim 46. All steps performed by the method of claim 32 would be practiced by the apparatus of claim 46. Claim 46 analysis applies equally to claim 32.
Claims 34 and 48 are rejected under 35 U.S.C. 103 as being unpatentable over Tang as applied to claims 25 and 38 above, and further in view of Kim et al. US 20160085507 A1), hereinafter Kim.
Regarding claim 48, Tang teaches all the limitations of claim 38 as stated above. Further, Tang teaches
wherein a coding manner of the exponent bit width field is (Tang Figs. 1-2 and paragraphs [0036-0038, 0046-0048] DW1 -1; DW2 – 2; any one of P1 values – 0; any one of P2 values – 10, 11).
Tang does not explicitly teach unconventional prefix coding, wherein a minimum value of the P1 values is greater than a maximum value of the P2 values.
However, on the same field of endeavor, Kim discloses coding an exponent size wherein a lower value encodes a larger exponent bit size and a higher value encodes a smaller bit size (Kim Fig. 4 and paragraphs [00665-0066]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tang using Kim and configure the exponent bit width field to be coded using unconventional prefix coding and extend the concept of Fig. 4 of Kim to Fig. 6 such that a value 0 corresponds to an exponent bit width of N+3; 1 corresponds to an exponent bit width of N+2; 10 corresponds to an exponent bit width of N+1; and 11 corresponds to an exponent bit width of N. It is obvious from Figs. 3-6 of Kim that the exponent size can be coded using either unconventional or conventional prefix coding. Therefore, one of ordinary skill in the art could have substituted the conventional prefix coding of Tang for unconventional prefix coding of Kim, and the results of the substitution would have been predictable because both scheme encodes the bit width of the exponent field. See MPEP 2141 subsection III(A).
Therefore, the combination of Tang as modified in view of Kim wherein a coding manner of the exponent bit width field is unconventional prefix coding, wherein a bit width occupied by the exponent bit width field in the total bit width N is DW1 or DW2, and DW1 is less than DW2, and wherein the first processor is further configured to code, by using the unconventional prefix coding, any one of P1 values with the bit width DW1 occupied by the exponent bit width field, or any one of P2 values with the bit width DW2 occupied by the exponent bit width field, and wherein a minimum value of the P1 values is greater than a maximum value of the P2 values, and the bit width D belongs to the P1 values or the P2 values.
Regarding claim 34, it is directed to a method practiced by the apparatus of claim 48. All steps performed by the method of claim 34 would be practiced by the apparatus of claim 48. Claim 48 analysis applies equally to claim 34.
Allowable Subject Matter
Claims 29-31 and 42-44 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten to overcome the 35 U.S.C. 101 rejection discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art references cited explicitly teach or suggest, in combination with other limitations of the claims, determine, based on the bit width D indicated by the exponent bit width field, a numerical range E corresponding to the first exponent field during coding, wherein Ei belongs to the numerical range E, and the numerical range E satisfies the following formula: E=(-1)Se x [2D-1, (2D-1)], wherein Se is a sign bit of Ei, and Se is 0 or 1 as recited in claims 29 and 42.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Morris (US 3742198 A) related to a tapered floating point representation comprising a first fixed-length field that is subdivided into a variable length exponent field and a variable length fraction field, and a second fixed-length field that serves to specify the size of the variable length exponent field as shown in Fig. 2. Further, Morris discloses using integer coding in the exponent bit width field to code the width of the exponent field.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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