DETAILED ACTION
The instant application having Application No. 18/126,107 filed on 3/24/2023 is presented for examination by the examiner. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 11-12 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
As per Claim 11, it recites “adding data from the first accumulator to data from the accumulator” (emphasis added). There is insufficient antecedent basis for the limitation “the accumulator”, and it is therefore unclear if “the accumulator” is meant to antecedently refer to the first accumulator or the second accumulator.
For examination purposes, the Examiner interprets the limitation as reading “adding data from the first accumulator to data from the second accumulator”.
Claim 12 is rejected for the reasons presented above, due to its dependency upon rejected Claim 11.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-11 and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moore et al. (US 7,424,503).
As per Claim 1, Moore discloses a processor comprising: one or more processor cores, wherein a processor core of the one or more processor cores includes a first data path configured to: add a first portion of a block of data to a first lane of a set of lanes of a first accumulator to produce a first sum and a first carry-out bit; store the first sum in the first lane of the set of lanes of the first accumulator; and add the first carry-out bit to a second lane of the set of lanes of the first accumulator (Abstract and Figures 3-4 and Column 1, lines 6-11, 31-36 and Column 2, lines 13-35, a pipelined accumulator for a digital signal processor comprises a lower accumulator partition, i.e. lane, for the 24 least significant bits (LSBs) of input data and an upper accumulator partition, i.e. lane, for the 24 most significant bits (MSBs) of the input data, wherein the LSB sum is stored at the output of the lower partition e.g. at 440, and a single carry bit is output and added to the upper partition from the lower partition).
As per Claim 2, Moore discloses the processor of claim 1, wherein the processor core further includes a second data path configured to: add a second portion of the block of data to a first lane of a set of lanes of a second accumulator to produce a second sum and a second carry-out bit; store the second sum in the first lane of the set of lanes of the second accumulator; and add the first carry-out bit to a second lane of the set of lanes of the second accumulator, wherein the first portion of the block of data is different from the second portion of the block of data (Figure 5 and Column 2, lines 36-53, a pipelined accumulator may comprise N partitions, wherein e.g. partitions 200 and 100 comprise a first data path for adding/accumulating the 2 MSBs of a block of data wherein the carry bit from lane 200 is provided and added to lane 100, and partitions 500 and 400 comprise a second data path for adding/accumulating the 2 LSBs of a block of data wherein the carry bit from lane 500 is provided and added to lane 400).
As per Claim 3, Moore discloses the processor of claim 2, wherein the first portion of the block of data includes a most significant bit of the block of data and the second portion of the block of data includes a least significant bit of the block of data (Figure 5 and Column 2, lines 36-53, a pipelined accumulator may comprise N partitions, wherein e.g. partitions 200 and 100 comprise a first data path for adding/accumulating the 2 MSBs of a block of data wherein the carry bit from lane 200 is provided and added to lane 100, and partitions 500 and 400 comprise a second data path for adding/accumulating the 2 LSBs of a block of data wherein the carry bit from lane 500 is provided and added to lane 400).
As per Claim 4, Moore discloses the processor of claim 2, wherein the one or more processor cores are configured to add data from the first accumulator to data from the second accumulator (Figure 5 and Column 2, lines 36-53, a pipelined accumulator may comprise N partitions, wherein carry bits are added from each lower partition to the next adjacent upper partition, i.e. a carry bit from the lower accumulator lanes (i.e. first data path comprising the first accumulator) is added to the upper accumulator lanes (i.e. second data path comprising the second accumulator)).
As per Claims 8-11, they are method claims comprising the same limitations as recited in Claims 1-4, respectively. Thus, Claims 8-11 are rejected under the same rationale(s) as presented in the above rejection(s) of Claims 1-4.
As per Claim 15, Moore discloses a processor, comprising: one or more processor cores, wherein a processor core of the one or more processor cores includes a first data path configured to: store a first sum of a first portion of a block of data and data in a first lane of a set of lanes of a first accumulator in the first lane of the set of lanes of the first accumulator; and based on the first sum, add a first carry-out bit to a second lane of the set of lanes of the first accumulator (Abstract and Figures 3-4 and Column 1, lines 6-11, 31-36 and Column 2, lines 13-35, a pipelined accumulator for a digital signal processor comprises a lower accumulator partition, i.e. lane, that sums the 24 least significant bits (LSBs) of input data with an accumulator value and stores the resulting sum, and an upper accumulator partition, i.e. lane, that sums the 24 most significant bits (MSBs) of the input data with a single carry bit output from the lower partition).
As per Claim 16, Moore discloses the processor of claim 15, wherein the processor core further includes a second data path configured to: store a second sum of a second portion of a block of data and data in a first lane of a set of lanes of a second accumulator in the first lane of the set of lanes of the second accumulator; and based on the second sum, add a second carry-out bit to a second lane of the set of lanes of the second accumulator, wherein the first portion of the block of data is different from the second portion of the block of data (Figure 5 and Column 2, lines 36-53, a pipelined accumulator may comprise N partitions, wherein e.g. partitions 200 and 100 comprise a first data path for adding/accumulating the 2 MSBs of a block of data and storing the sum e.g. in 140 and 240, wherein the carry bit from lane 200 is provided and added to lane 100; and partitions 500 and 400 comprise a second data path for adding/accumulating the 2 LSBs of a block of data and storing the sum e.g. in 440 and 540, wherein the carry bit from lane 500 is provided and added to lane 400).
As per Claims 17-18, they recite the same limitations as in Claims 3-4. Thus, Claims 17-18 are rejected under the same rationale(s) as presented in the above rejection(s) of Claims 3-4.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Moore in view of Xiu (US 2021/0224035).
As per Claim 6, Moore discloses the processor of claim 1, wherein the first data path comprises a first adder configured to: add the first portion of the block of data to data in the first lane of the set of lanes of the first accumulator to produce the first sum, and generate the first carry-out bit based on the first sum (Figures 3-4 and Column 2, lines 13-35, the lower partition adds the 24 LSBs of the input data to the feedback accumulator value 424 to generate a sum, wherein the carry bit output is necessarily the most significant bit of the lower partition sum).
Moreover, Xiu similarly discloses a pipelined/partitioned accumulator, and further teaches generating the first carry-out bit based on the first sum (Figure 2 and Paragraphs 0008 and 0025-0026, the carry bit from a lower partition to a higher partition of a decomposed accumulator is the most significant bit of the lower partition sum).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the teachings of Xiu with that of Moore because Xiu provides additional information that applied to the operation of a decomposed accumulator, and also provides for reducing or replacing lower partitions with a simpler and faster circuit in order to achieve faster operation while maintaining accuracy (Xiu, Paragraphs 0029-0030, 0039 and 0041).
As per Claims 13 and 20, they are method and apparatus claims comprising the same limitations as recited in Claim 6. Thus, Claims 13 and 20 are rejected under the same rationale as presented in the above rejection of Claim 6.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Moore in view of Schulte et al. (US 7,593,978).
As per Claim 7, Moore does not explicitly disclose the processor of claim 1, wherein the first data path includes one or more inverters configured to invert the first portion of the block of data.
However, Schulte teaches a pipelined accumulator wherein the first data path includes one or more inverters configured to invert the first portion of the block of data (Figures 1-2 and Column 2, lines 56-64 and Column 4, lines 30-52, input(s) to the multi-stage pipelined accumulator may be inverted via inverters in order to perform accumulative subtraction).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the accumulator features taught by Schulte with the accumulator of Moore because it provides for additional functionality such as subtraction and vector operation(s) (Schulte, Column 3, lines 31-39).
As per Claim 14, it is a method claim comprising the same limitations as recited in Claim 7. Thus, Claim 14 is rejected under the same rationale as presented in the above rejection of Claim 7.
Allowable Subject Matter
Claims 5 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Xiu (US 2011/0238721) – discloses a pipelined accumulator circuit including N cascaded adders, wherein each adder feeds a sum output back to itself and outputs carry information to a next adjacent adder stage
Kim et al. (US 2021/0064339) – discloses a pipelined accumulator comprising a first lane comprising a ripple carry adder for adding/accumulating a least significant portion of an input value, e.g. Areg[m-1:0], and a second lane for adding/accumulating a most significant portion of an input value, e.g. Areg[n-1:m], wherein the carry generated from the first lane is input and added to the second lane
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW SANDIFER whose telephone number is (571)270-5175. The examiner can normally be reached Mon-Fri 9:30am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW D SANDIFER/Primary Examiner, Art Unit 2151
