Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 16, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8, 10-11, 14-15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over
Harikumar et al. (U.S. Patent Application Publication US 20090144531 A1, hereinafter “Harikumar”) in view of Sari (U.S. Patent Application Publication US 20190361764 A1), Chen et al. (U.S. Patent Application Publication US 20160283438 A1, hereinafter “Chen”), and Kim et al. (U.S. Patent Application Publication US 20170228241 A1, hereinafter “Kim”).
With regard to claim 1, Harikumar discloses:
A processor (“Apparatus 100 may comprise a dual processor computer system 101 that comprises a first processor 102 and a second processor 103.”, para [0007], fig 1) comprising:
a first core die associated with a first operating system and including one or more processor cores (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1),
a second core die associated with a second operating system and including one or more processor cores (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1),
Harikumar does not disclose:
wherein the one or more processor cores of the first core die are configured to execute an instruction to produce a first result;
wherein the one or more processor cores of the second core die are configured to execute the instruction to produce a second result
and wherein the second operating system is different from the first operating system; and
a voting circuitry configured to generate an output resulting from the processor executing the instruction based on the first result and the second result.
Sari discloses:
wherein the one or more processor cores of the first core die are configured to execute an instruction to produce a first result (“a result from executing the first procedure on the first core of the first processor”, para [0013]);
wherein the one or more processor cores of the second core die are configured to execute the instruction to produce a second result (“a result from executing the first procedure on the second core of the first processor”, para [0013])
Both the systems of Harikumar and Sari deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar in view of Sari to increase reliability.
Chen discloses:
and wherein the second operating system is different from the first operating system (“Different types of OS may be built on processors designed according to different instruction set architectures (ISAs). For example, Intel® Architecture (IA) is a type of ISA on which Windows OS may operate, and ARM® is another type of ISA on which Android may operate.”, para [0003]); and
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to improve processing flexibility.
Kim discloses:
a voting circuitry configured to generate an output resulting from the processor executing the instruction based on the first result and the second result ("The processing unit PU-1 further includes not only processing elements PE(1-1) to PE(1-3) but also a voter VT-1 and a share register SR-1.”, para [0034], “The voter VT-1 selects, using a majority-vote system, one among the results Re(1-1), Re(1-2) and Re(1-3) generated from the three processing elements PE(1-1), PE(1-2) and PE(1-3) and generates a selected result Re1. For example, in the case where the results Re(1-1) and Re(1-2) have the same value while only the result Re(1-3) has a different value, the result Re1 selected by the voter VT-1 has the same value as that of the results Re(1-1) and Re(1-2). The processing unit PU-1 outputs only the result Re1. If the results Re(1-1), Re(1-2) and Re(1-3) have all different values, the voter VT-1 is not able to select one value. In this case, the select module SM-1 outputs an exception signal ES.”, para [0049], “The processing elements PE(1-1), PE(1-2) and PE(1-3) perform in parallel the same work CFD(1) and output the results Re(1-1), Re(1-2) and Re(1-3). It may be assumed that the structures of the processing elements PE(1-2) and PE(1-3) are the same as that of the processing element PE(1-1). The results Re(1-1), Re(1-2) and Re(1-3) are inputted to the voter VT-1.”, para [0055]).
Both the systems of Harikumar and Kim deal with processors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Kim “to increase the reliability” (Kim, para [0056]).
With regard to claim 2, Harikumar as modified discloses the processor of claim 1.
Harikumar further discloses:
further comprising: a third core die associated with a third operating system and including one or more processor cores (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1),
Harikumar as modified does not disclose however, Sari discloses:
wherein the one or more processor cores of the third core die are configured to execute the instruction to produce a third result (“a result from executing the first procedure on the first core of the second processor”, para [0014], fig 1).
Both the systems of Harikumar and Sari deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Sari to increase processor reliability.
With regard to claim 3, Harikumar as modified discloses the processor of claim 2.
Harikumar as modified does not disclose however, Kim discloses:
wherein the voting circuitry is configured to generate the output of the instruction by the processor based upon the first result, the second result, and the third result ("The processing unit PU-1 further includes not only processing elements PE(1-1) to PE(1-3) but also a voter VT-1 and a share register SR-1.”, para [0034], “The voter VT-1 selects, using a majority-vote system, one among the results Re(1-1), Re(1-2) and Re(1-3) generated from the three processing elements PE(1-1), PE(1-2) and PE(1-3) and generates a selected result Re1. For example, in the case where the results Re(1-1) and Re(1-2) have the same value while only the result Re(1-3) has a different value, the result Re1 selected by the voter VT-1 has the same value as that of the results Re(1-1) and Re(1-2). The processing unit PU-1 outputs only the result Re1. If the results Re(1-1), Re(1-2) and Re(1-3) have all different values, the voter VT-1 is not able to select one value. In this case, the select module SM-1 outputs an exception signal ES.”, para [0049], “The processing elements PE(1-1), PE(1-2) and PE(1-3) perform in parallel the same work CFD(1) and output the results Re(1-1), Re(1-2) and Re(1-3). It may be assumed that the structures of the processing elements PE(1-2) and PE(1-3) are the same as that of the processing element PE(1-1). The results Re(1-1), Re(1-2) and Re(1-3) are inputted to the voter VT-1.”, para [0055]).
Both the systems of Harikumar and Kim deal with processors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Kim “to increase the reliability” (Kim, para [0056]).
With regard to claim 4, Harikumar as modified discloses the processor of claim 1.
Harikumar as modified does not disclose however, Chen discloses:
wherein: the one or more processor cores of the first core die are associated with a first instruction set architecture (ISA); the one or more processor cores of the second core die are associated with a second ISA; and the second ISA is different from the first ISA (“The heterogeneous cores may include at least one core designed according to a first ISA type, and at least one core designed according to a second ISA type, where the first and second ISA types are different.”, para [0023]).
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to execute multiple kinds of workloads.
With regard to claim 5, Harikumar as modified discloses the processor of claim 4.
Harikumar as modified does not disclose however, Chen discloses:
further comprising: a first input/output (I/O) die (e.g. CL, 972, fig 9) associated with the first ISA and connected to the first core die; and a second I/O die (e.g. CL, 982, fig 9) associated with the second ISA and connected to the second core die (“The heterogeneous cores may include at least one core designed according to a first ISA type, and at least one core designed according to a second ISA type, where the first and second ISA types are different.”, para [0023], “In one embodiment, processors 970, 980 may implement hybrid cores as described above. Processors 970, 980 may include integrated memory and I/O control logic (“CL”) 972 and 982”, para [0088], fig 9).
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to increase fault isolation.
With regard to claim 8, Harikumar discloses:
A method (“Now referring to FIG. 2, an embodiment of a method 200 is illustrated.”, para [0020], fig 2) comprising:
(“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1);
(“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1) and
Harikumar does not disclose:
executing, on a first core die of a processor, an instruction to produce a first result,
executing, on a second core die of the processor, the instruction to produce a second result,
wherein the second operating system is different from the first operating system; and
generating, by voting circuitry of the processor, an output resulting from the processor executing the instruction based on the first result and the second result.
Sari discloses:
executing, on a first core die of a processor, an instruction to produce a first result (“a result from executing the first procedure on the first core of the first processor”, para [0013]),
executing, on a second core die of the processor, the instruction to produce a second result (“a result from executing the first procedure on the second core of the first processor”, para [0013]),
Both the systems of Harikumar and Sari deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar in view of Sari to increase reliability.
Chen discloses:
wherein the second operating system is different from the first operating system (“Different types of OS may be built on processors designed according to different instruction set architectures (ISAs). For example, Intel® Architecture (IA) is a type of ISA on which Windows OS may operate, and ARM® is another type of ISA on which Android may operate.”, para [0003]);
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to improve processing flexibility.
Kim discloses:
generating, by voting circuitry of the processor, an output resulting from the processor executing the instruction based on the first result and the second result ("The processing unit PU-1 further includes not only processing elements PE(1-1) to PE(1-3) but also a voter VT-1 and a share register SR-1.”, para [0034], “The voter VT-1 selects, using a majority-vote system, one among the results Re(1-1), Re(1-2) and Re(1-3) generated from the three processing elements PE(1-1), PE(1-2) and PE(1-3) and generates a selected result Re1. For example, in the case where the results Re(1-1) and Re(1-2) have the same value while only the result Re(1-3) has a different value, the result Re1 selected by the voter VT-1 has the same value as that of the results Re(1-1) and Re(1-2). The processing unit PU-1 outputs only the result Re1. If the results Re(1-1), Re(1-2) and Re(1-3) have all different values, the voter VT-1 is not able to select one value. In this case, the select module SM-1 outputs an exception signal ES.”, para [0049], “The processing elements PE(1-1), PE(1-2) and PE(1-3) perform in parallel the same work CFD(1) and output the results Re(1-1), Re(1-2) and Re(1-3). It may be assumed that the structures of the processing elements PE(1-2) and PE(1-3) are the same as that of the processing element PE(1-1). The results Re(1-1), Re(1-2) and Re(1-3) are inputted to the voter VT-1.”, para [0055]).
Both the systems of Harikumar and Kim deal with processors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Kim “to increase the reliability” (Kim, para [0056]).
With regard to claim 10, Harikumar as modified discloses the method of claim 8.
Harikumar further discloses:
further comprising:
executing, on a third core die of the processor, (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1)
Harikumar does not disclose:
executing, on a third core die of the processor, the instruction to produce a third result
and wherein the output of the instruction by the processor is generated based on the first result, the second result, and the third result.
Sari discloses:
executing, on a third core die of the processor, the instruction to produce a third result (“a
result from executing the first procedure on the first core of the second processor”, para [0014], fig 1)
Both the systems of Harikumar and Sari deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Sari to increase reliability.
Kim discloses:
and wherein the output of the instruction by the processor is generated based on the first result, the second result, and the third result ("The processing unit PU-1 further includes not only processing elements PE(1-1) to PE(1-3) but also a voter VT-1 and a share register SR-1.”, para [0034], “The voter VT-1 selects, using a majority-vote system, one among the results Re(1-1), Re(1-2) and Re(1-3) generated from the three processing elements PE(1-1), PE(1-2) and PE(1-3) and generates a selected result Re1. For example, in the case where the results Re(1-1) and Re(1-2) have the same value while only the result Re(1-3) has a different value, the result Re1 selected by the voter VT-1 has the same value as that of the results Re(1-1) and Re(1-2). The processing unit PU-1 outputs only the result Re1. If the results Re(1-1), Re(1-2) and Re(1-3) have all different values, the voter VT-1 is not able to select one value. In this case, the select module SM-1 outputs an exception signal ES.”, para [0049], “The processing elements PE(1-1), PE(1-2) and PE(1-3) perform in parallel the same work CFD(1) and output the results Re(1-1), Re(1-2) and Re(1-3). It may be assumed that the structures of the processing elements PE(1-2) and PE(1-3) are the same as that of the processing element PE(1-1). The results Re(1-1), Re(1-2) and Re(1-3) are inputted to the voter VT-1.”, para [0055]).
Both the systems of Harikumar and Kim deal with processors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Kim “to increase the reliability” (Kim, para [0056]).
With regard to claim 11, Harikumar as modified discloses the method of claim 8.
Harikumar as modified does not disclose however, Chen discloses:
wherein: the first core die includes one or more processor cores associated with a first instruction set architecture (ISA); the second core die includes one or more processor cores associated with a second ISA; and the second ISA is different from the first ISA (“The heterogeneous cores may include at least one core designed according to a first ISA type, and at least one core designed according to a second ISA type, where the first and second ISA types are different.”, para [0023]).
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to execute multiple kinds of workloads.
With regard to claim 14, Harikumar discloses:
A processor (“Apparatus 100 may comprise a dual processor computer system 101 that comprises a first processor 102 and a second processor 103.”, para [0007], fig 1) comprising:
a first core die including one or more processor cores (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1),
a second core die including one or more processor cores(“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1)
Harikumar does not disclose:
a first core die including one or more processor cores associated with a first instruction set architecture (ISA),
a second core die including one or more processor cores associated with a second ISA,
wherein the one or more processor cores of the first core die are configured to execute an instruction to produce a first result;
wherein the one or more processor cores of the second core die are configured to execute the instruction to produce a second result
and wherein the second ISA is different from the first ISA; and
a voting circuitry configured to generate an output resulting from the processor executing the instruction based on the first result and the second result.
Chen discloses:
a first core die including one or more processor cores associated with a first instruction set architecture (ISA), a second core die including one or more processor cores associated with a second ISA, and wherein the second ISA is different from the first ISA (“The heterogeneous cores may include at least one core designed according to a first ISA type, and at least one core designed according to a second ISA type, where the first and second ISA types are different.”, para [0023]) ; and
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar in view of Chen to execute multiple kinds of workloads.
Sari discloses:
wherein the one or more processor cores of the first core die are configured to execute an instruction to produce a first result (“a result from executing the first procedure on the first core of the first processor”, para [0013]);
wherein the one or more processor cores of the second core die are configured to execute the instruction to produce a second result (“a result from executing the first procedure on the second core of the first processor”, para [0013]);
Both the systems of Harikumar and Sari deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar in view of Sari to increase reliability.
Kim discloses:
a voting circuitry configured to generate an output resulting from the processor executing the instruction based on the first result and the second result ("The processing unit PU-1 further includes not only processing elements PE(1-1) to PE(1-3) but also a voter VT-1 and a share register SR-1.”, para [0034], “The voter VT-1 selects, using a majority-vote system, one among the results Re(1-1), Re(1-2) and Re(1-3) generated from the three processing elements PE(1-1), PE(1-2) and PE(1-3) and generates a selected result Re1. For example, in the case where the results Re(1-1) and Re(1-2) have the same value while only the result Re(1-3) has a different value, the result Re1 selected by the voter VT-1 has the same value as that of the results Re(1-1) and Re(1-2). The processing unit PU-1 outputs only the result Re1. If the results Re(1-1), Re(1-2) and Re(1-3) have all different values, the voter VT-1 is not able to select one value. In this case, the select module SM-1 outputs an exception signal ES.”, para [0049], “The processing elements PE(1-1), PE(1-2) and PE(1-3) perform in parallel the same work CFD(1) and output the results Re(1-1), Re(1-2) and Re(1-3). It may be assumed that the structures of the processing elements PE(1-2) and PE(1-3) are the same as that of the processing element PE(1-1). The results Re(1-1), Re(1-2) and Re(1-3) are inputted to the voter VT-1.”, para [0055]).
Both the systems of Harikumar and Kim deal with processors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Kim “to increase the reliability” (Kim, para [0056]).
With regard to claim 15, Harikumar as modified discloses the processor of claim 14.
Harikumar further discloses:
wherein: the first core die is associated with a first operating system; the second core die is associated with a second operating system; (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1).
Harikumar does not disclose however, Chen discloses:
and the second operating system is different from the first operating system (“Different types of OS may be built on processors designed according to different instruction set architectures (ISAs). For example, Intel® Architecture (IA) is a type of ISA on which Windows OS may operate, and ARM® is another type of ISA on which Android may operate.”, para [0003])
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to improve processing flexibility.
With regard to claim 17, Harikumar as modified discloses the processor of claim 14.
Harikumar as modified does not disclose however, Chen discloses:
further comprising: a first input/output (I/O) die (e.g. CL, 972, fig 9) associated with the first ISA and connected to the first core die; and a second I/O die (e.g. CL, 982, fig 9) associated with the second ISA and connected to the second core die (“The heterogeneous cores may include at least one core designed according to a first ISA type, and at least one core designed according to a second ISA type, where the first and second ISA types are different.”, para [0023], “In one embodiment, processors 970, 980 may implement hybrid cores as described above. Processors 970, 980 may include integrated memory and I/O control logic (“CL”) 972 and 982”, para [0088], fig 9).
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to increase fault isolation.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Harikumar, Sari, Chen and Kim as applied to claim 8 above, and further in view of Lu et al. (U.S. Patent Application Publication No. US 20230111884 A1, hereinafter “Lu”).
With regard to claim 12, Harikumar as modified discloses the method of claim 8.
Harikumar does not disclose however, Lu discloses:
further comprising: allocating the first core die to a first virtual machine (VM) running the first operating system; and allocating the second core die to a second VM running the second operating system (“The method includes: dividing the multi-core processor to a plurality of virtualization functions, where each virtualization function corresponds to one or a plurality of processing cores; and mapping the virtualization function to a virtual machine.”, para [0021], “This shows that there may be one or a plurality of virtual functions. When there is one virtual function, all the processing cores in the multi-core processor may be divided into single virtual function; and when there are a plurality of virtual functions, the virtual machines may operate independently. Operating independently means that each virtual machine is isolated from each other, and may operate without depending on other virtual machines, and may not be influenced by other virtual machines. Besides, isolation of the present disclosure is based on hardware, so that there is less interference among the virtual machines. Besides, independent operation means that each virtual machine adopts different operating system without affecting each other.”, para [0221], fig 11, fig 20, fig 26).
Both the systems of Harikumar and Lu deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Lu to maintain isolation between workloads.
Claims 6, 13, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Harikumar,
Sari, Chen, and Kim as applied to claims 1, 8, and 14, above, and further in view of Vijayan et al. (U.S. Patent Application Publication No. US 20240036997 A1, hereinafter “Vijayan”).
With regard to claim 6, Harikumar as modified discloses the process of claim 1.
Harikumar further discloses:
further comprising: a third core die including one or more programmable logic devices (“The third partition may comprise a third number of cores and a third number of available system resources.”, para [0023], fig. 1).
However, Harikumar does not explicitly teach programmable logic devices. Vijayan discloses a system resources includes programmable logic (“system resources like processing resources (e.g., a microcontroller, a microprocessor, central processing unit core(s), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), and the like), memory, database transactions, network devices, etc.”, para [0027]).
Both the systems of Harikumar and Vijayan deal with processor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Vijayan to improve decrease processing latency.
With regard to claim 13, Harikumar as modified discloses the method of claim 8.
Harikumar further discloses:
wherein the processor further comprises a third core die including one or more programmable logic devices (“The third partition may comprise a third number of cores and a third number of available system resources.”, para [0023], fig. 1).
However, Harikumar does not explicitly teach programmable logic devices. Vijayan discloses a system resources includes programmable logic (“system resources like processing resources (e.g., a microcontroller, a microprocessor, central processing unit core(s), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), and the like), memory, database transactions, network devices, etc.”, para [0027]).
Both the systems of Harikumar and Vijayan deal with processors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Vijayan to improve decrease processing latency.
With regard to claim 18, Harikumar as modified discloses the processor of claim 14.
Harikumar further discloses:
further comprising: a third core die including one or more programmable logic devices (“The third partition may comprise a third number of cores and a third number of available system resources.”, para [0023], fig. 1).
However, Harikumar does not explicitly teach programmable logic devices. Vijayan discloses a system resources includes programmable logic (“system resources like processing resources (e.g., a microcontroller, a microprocessor, central processing unit core(s), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), and the like), memory, database transactions, network devices, etc.”, para [0027]).
Both the systems of Harikumar and Vijayan deal with processors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Vijayan to improve decrease processing latency.
With regard to claim 19, Harikumar as modified discloses the processor of claim 18.
Vijayan discloses:
wherein the one or more programmable logic devices includes one or more field-programmable gate arrays (“system resources like processing resources (e.g., a microcontroller, a microprocessor, central processing unit core(s), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), and the like), memory, database transactions, network devices, etc.”, para [0027]).
Both the systems of Harikumar and Vijayan deal with processors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Vijayan to improve decrease processing latency.
Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Harikumar, Sari, Chen, and Kim as applied to claims 8 and 14, above, and further in view of Sinha Roy et al. (U.S. Patent Application Publication No. US 20230132500 A1, hereinafter “Sinha Roy”).
With regard to claim 9, Harikumar as modified discloses the method of claim 8.
Harikumar does not disclose however, Sinha Roy discloses:
wherein the instruction is executed on the first core die and the second core die concurrently (“The first cores 630 and the second cores 640 may simultaneously process, in parallel, a same instruction or different instructions.”, para [0079]).
Both the systems of Harikumar and Sinha Roy deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Sinha Roy to improve processor efficiency.
With regard to claim 20, Harikumar as modified discloses the processor of claim 14.
Harikumar does not disclose however, Sinha Roy discloses:
wherein the one or more processor cores of the first core die and the one or more processor cores of the second core die are configured to execute the instruction concurrently (“The first cores 630 and the second cores 640 may simultaneously process, in parallel, a same instruction or different instructions.”, para [0079]).
Both the systems of Harikumar and Sinha Roy deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Sinha Roy to improve processor efficiency.
Allowable Subject Matter
Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be
allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Meriac (U.S. Patent Application Publication No. US 20190391888 A1) discloses “The majority voting unit 315 receives the outputs of each processor 305a-305c and determines a single definitive output 320. If the processors 305a-305c produce the same output, the majority voting unit 315 provides this output as the definitive output 320. If two of the processors 305a-305c provide the same “majority” output but the third provides a differing “minority” output, the majority voting unit 315 provides the majority output as the definitive output 320. The system 300 can thus proceed with its operation flow without interruption regardless of a fault in one of the processors 305a-305c.”, para [0057].
Mace (UK Patent Application Publication No. GB 2565338 A) discloses “Techniques used in existing fault tolerant processors involve using multiple processor cores to execute the same code, with results being compared at the end of each operation, if the results are not identical then the comparison signals an error. Alternatively, where there are more than two cores, a voting system may be used to decide which result is correct (i.e. with the result obtained by the majority of cores being taken as the correct result).”, para [0024].
Hane (“A FAULT-TOLERANT COMPUTER ARCHITECTURE FOR SPACE VEHICLE APPLICATIONS”) discloses “The basic fault-tolerant design produced for this project consists of a number of small hardware units, or “tiles,” that perform the computations required by the system. (The required computations depend on which specific design variant is being considered; variants will be discussed in Chapter 5.) Each tile takes up a rectangular portion of the FPGA chip; the FPGA hardware within this region is configured to create the circuits required by the tile. Depending on the specific system (see Chapter 5), each tile may be a soft processor or a more specialized circuit. At any given time, three tiles are active and connected to a majority voter, providing Triple Modulo Redundancy (TMR). The remaining tiles function as spares, and are held in reset to conserve power. If one of the three active tiles suffers a serious fault, the majority voter will mask its incorrect output, since the outputs of the two good tiles will overrule that of the bad one. The voting circuitry is also able to detect the disagreement of one tile with the other two, and declare the tile that disagrees “damaged. A simple state machine will then handle the process of deactivating the faulty tile, bringing a spare tile online, and re-initializing all three active tiles to a common state (e.g. the closest checkpoint in a processor’s code) before resuming computations. The complexity of the re-initialization, and the time needed, depends on the module type. See Figures 5.2, 5.6, 5.10, and 5.14 for flow diagrams depicting the spare swap/recovery process for each of the four systems.”, last paragraph, pg. 20-first paragraph, pg.21.
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/S.S.N./Examiner, Art Unit 2192
/S. Sough/SPE, Art Unit 2192
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