Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 24, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
In view of Applicant’s amendments, the objection to the drawings is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections
set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8, 10-11, 14-15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over
Harikumar et al. (U.S. Patent Application Publication US 20090144531 A1, hereinafter “Harikumar”) in view of Sari (U.S. Patent Application Publication US 20190361764 A1) and Chen et al. (U.S. Patent Application Publication US 20160283438 A1, hereinafter “Chen”).
With regard to claim 1, Harikumar discloses:
A processor (“Apparatus 100 may comprise a dual processor computer system 101 that comprises a first processor 102 and a second processor 103.”, para [0007], fig 1) comprising:
a first core die associated with a first operating system and including one or more processor cores (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1),
a second core die associated with a second operating system and including one or more processor cores (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1),
Harikumar does not disclose:
wherein the one or more processor cores of the first core die are configured to execute an instruction to produce a first result;
wherein the one or more processor cores of the second core die are configured to execute the instruction to produce a second result
and wherein the second operating system is different from the first operating system
a voting circuitry configured to generate an output of the instruction by the processor based on the first result and the second result.
Sari discloses:
wherein the one or more processor cores of the first core die are configured to execute an instruction to produce a first result (“a result from executing the first procedure on the first core of the first processor”, para [0013]);
wherein the one or more processor cores of the second core die are configured to execute the instruction to produce a second result (“a result from executing the first procedure on the second core of the first processor”, para [0013])
a voting circuitry configured to generate an output of the instruction by the processor based on the first result and the second result (“A processor is an electronic circuit configured to read and execute one or more commands, i.e. a procedure.”, para [0007], “A processor may contain components that are capable of executing one or more commands in and of themselves. These components are referred to as cores”, para [0008], “A controller can be in the form of a separate core, or it can be implemented in one of the aforementioned cores. It is defined as a means for executing steps for comparing results.”, para [0011], “The second core of the first processor is deactivated according to the development, if the results from executing the first procedure on the first core and the second core of the first processor differ from one another, and the result from executing the first procedure on the first core of the first processor and the result from executing the first procedure on the first core of the second processor are the same.”, para [0018]).
Both the systems of Harikumar and Sari deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar in view of Sari to increase reliability.
Chen discloses:
and wherein the second operating system is different from the first operating system (“Different types of OS may be built on processors designed according to different instruction set architectures (ISAs). For example, Intel® Architecture (IA) is a type of ISA on which Windows OS may operate, and ARM® is another type of ISA on which Android may operate.”, para [0003]); and
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to improve processing flexibility.
With regard to claim 2, Harikumar as modified discloses the processor of claim 1.
Harikumar further discloses:
further comprising: a third core die associated with a third operating system and including one or more processor cores (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1),
Harikumar as modified does not disclose however, Sari discloses:
wherein the one or more processor cores of the third core die are configured to execute the instruction to produce a third result (“a result from executing the first procedure on the first core of the second processor”, para [0014], fig 1).
Both the systems of Harikumar and Sari deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Sari to increase processor reliability.
With regard to claim 3, Harikumar as modified discloses the processor of claim 2.
Harikumar as modified does not disclose however, Sari discloses:
wherein the voting circuitry is configured to generate the output of the instruction by the processor based upon the first result, the second result, and the third result (“A processor is an electronic circuit configured to read and execute one or more commands, i.e. a procedure.”, para [0007], “A processor may contain components that are capable of executing one or more commands in and of themselves. These components are referred to as cores”, para [0008], “A controller can be in the form of a separate core, or it can be implemented in one of the aforementioned cores. It is defined as a means for executing steps for comparing results.”, para [0011], “The second core of the first processor is deactivated according to the development, if the results from executing the first procedure on the first core and the second core of the first processor differ from one another, and the result from executing the first procedure on the first core of the first processor and the result from executing the first procedure on the first core of the second processor are the same.”, para [0018]).
Both the systems of Harikumar and Sari deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Sari to increase reliability.
With regard to claim 4, Harikumar as modified discloses the processor of claim 1.
Harikumar as modified does not disclose however, Chen discloses:
wherein: the one or more processor cores of the first core die are associated with a first instruction set architecture (ISA); the one or more processor cores of the second core die are associated with a second ISA; and the second ISA is different from the first ISA (“The heterogeneous cores may include at least one core designed according to a first ISA type, and at least one core designed according to a second ISA type, where the first and second ISA types are different.”, para [0023]).
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to execute multiple kinds of workloads.
With regard to claim 5, Harikumar as modified discloses the processor of claim 4.
Harikumar as modified does not disclose however, Chen discloses:
further comprising: a first input/output (I/O) die (e.g. CL, 972, fig 9) associated with the first ISA and connected to the first core die; and a second I/O die (e.g. CL, 982, fig 9) associated with the second ISA and connected to the second core die (“The heterogeneous cores may include at least one core designed according to a first ISA type, and at least one core designed according to a second ISA type, where the first and second ISA types are different.”, para [0023], “In one embodiment, processors 970, 980 may implement hybrid cores as described above. Processors 970, 980 may include integrated memory and I/O control logic (“CL”) 972 and 982”, para [0088], fig 9).
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to increase fault isolation.
With regard to claim 8, Harikumar discloses:
A method (“Now referring to FIG. 2, an embodiment of a method 200 is illustrated.”, para [0020], fig 2) comprising:
(“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1);
(“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1) and
Harikumar does not disclose:
executing, on a first core die of a processor, an instruction to produce a first result,
executing, on a second core die of the processor, the instruction to produce a second result,
wherein the second operating system is different from the first operating system; and
generating an output of the instruction by the processor based on the first result and the second result.
Sari discloses:
executing, on a first core die of a processor, an instruction to produce a first result (“a result from executing the first procedure on the first core of the first processor”, para [0013]),
executing, on a second core die of the processor, the instruction to produce a second result (“a result from executing the first procedure on the second core of the first processor”, para [0013]),
and generating an output of the instruction by the processor based on the first result and the second result (“A processor is an electronic circuit configured to read and execute one or more commands, i.e. a procedure.”, para [0007], “A processor may contain components that are capable of executing one or more commands in and of themselves. These components are referred to as cores”, para [0008], “A controller can be in the form of a separate core, or it can be implemented in one of the aforementioned cores. It is defined as a means for executing steps for comparing results.”, para [0011], “The second core of the first processor is deactivated according to the development, if the results from executing the first procedure on the first core and the second core of the first processor differ from one another, and the result from executing the first procedure on the first core of the first processor and the result from executing the first procedure on the first core of the second processor are the same.”, para [0018]).
Both the systems of Harikumar and Sari deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar in view of Sari to increase reliability.
Chen discloses:
wherein the second operating system is different from the first operating system (“Different types of OS may be built on processors designed according to different instruction set architectures (ISAs). For example, Intel® Architecture (IA) is a type of ISA on which Windows OS may operate, and ARM® is another type of ISA on which Android may operate.”, para [0003]);
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to improve processing flexibility.
With regard to claim 10, Harikumar as modified discloses the method of claim 8.
Harikumar further discloses:
further comprising:
executing, on a third core die of the processor, (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1)
Harikumar does not disclose however, Sari discloses:
executing, on a third core die of the processor, the instruction to produce a third result (“a
result from executing the first procedure on the first core of the second processor”, para [0014], fig 1)
and wherein the output of the instruction by the processor is generated based on the first result, the second result, and the third result (“A processor is an electronic circuit configured to read and execute one or more commands, i.e. a procedure.”, para [0007], “A processor may contain components that are capable of executing one or more commands in and of themselves. These components are referred to as cores”, para [0008], “A controller can be in the form of a separate core, or it can be implemented in one of the aforementioned cores. It is defined as a means for executing steps for comparing results.”, para [0011], “The second core of the first processor is deactivated according to the development, if the results from executing the first procedure on the first core and the second core of the first processor differ from one another, and the result from executing the first procedure on the first core of the first processor and the result from executing the first procedure on the first core of the second processor are the same.”, para [0018]).
Both the systems of Harikumar and Sari deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Sari to increase reliability.
With regard to claim 11, Harikumar as modified discloses the method of claim 8.
Harikumar as modified does not disclose however, Chen discloses:
wherein: the first core die includes one or more processor cores associated with a first instruction set architecture (ISA); the second core die includes one or more processor cores associated with a second ISA; and the second ISA is different from the first ISA (“The heterogeneous cores may include at least one core designed according to a first ISA type, and at least one core designed according to a second ISA type, where the first and second ISA types are different.”, para [0023]).
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to execute multiple kinds of workloads.
With regard to claim 14, Harikumar discloses:
A processor (“Apparatus 100 may comprise a dual processor computer system 101 that comprises a first processor 102 and a second processor 103.”, para [0007], fig 1) comprising:
a first core die including one or more processor cores (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1),
a second core die including one or more processor cores(“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1)
Harikumar does not disclose:
a first core die including one or more processor cores associated with a first instruction set architecture (ISA),
a second core die including one or more processor cores associated with a second ISA,
wherein the one or more processor cores of the first core die are configured to execute an instruction to produce a first result;
wherein the one or more processor cores of the second core die are configured to execute the instruction to produce a second result
and wherein the second ISA is different from the first ISA; and
a voting circuitry configured to generate an output of the instruction by the processor based on the first result and the second result.
Chen discloses:
a first core die including one or more processor cores associated with a first instruction set architecture (ISA), a second core die including one or more processor cores associated with a second ISA, and wherein the second ISA is different from the first ISA (“The heterogeneous cores may include at least one core designed according to a first ISA type, and at least one core designed according to a second ISA type, where the first and second ISA types are different.”, para [0023]) ; and
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar in view of Chen to execute multiple kinds of workloads.
Sari discloses:
wherein the one or more processor cores of the first core die are configured to execute an instruction to produce a first result (“a result from executing the first procedure on the first core of the first processor”, para [0013]);
wherein the one or more processor cores of the second core die are configured to execute the instruction to produce a second result (“a result from executing the first procedure on the second core of the first processor”, para [0013])
a voting circuitry configured to generate an output of the instruction by the processor based on the first result and the second result (“A processor is an electronic circuit configured to read and execute one or more commands, i.e. a procedure.”, para [0007], “A processor may contain components that are capable of executing one or more commands in and of themselves. These components are referred to as cores”, para [0008], “A controller can be in the form of a separate core, or it can be implemented in one of the aforementioned cores. It is defined as a means for executing steps for comparing results.”, para [0011], “The second core of the first processor is deactivated according to the development, if the results from executing the first procedure on the first core and the second core of the first processor differ from one another, and the result from executing the first procedure on the first core of the first processor and the result from executing the first procedure on the first core of the second processor are the same.”, para [0018]).
Both the systems of Harikumar and Sari deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Sari to increase reliability.
With regard to claim 15, Harikumar as modified discloses the processor of claim 14.
Harikumar further discloses:
wherein: the first core die is associated with a first operating system; the second core die is associated with a second operating system; (“For example, apparatus 100 may be divided into a plurality of partitions such as first partition 106, second partition 105 and third partition 104. The first partition 106 may comprise cores 102A and 102C, the second partition 105 may comprise cores 103B and 103D, and the third partition 104 may comprise cores 102B, 102D, 103A and 103B. In some embodiments, the first partition 104, the second partition 105, and/or the third partition 106 may either execute a first, second or third respective operating system or may function as an administrative or service partition.”, para [0014], fig 1).
Harikumar does not disclose however, Chen discloses:
and the second operating system is different from the first operating system (“Different types of OS may be built on processors designed according to different instruction set architectures (ISAs). For example, Intel® Architecture (IA) is a type of ISA on which Windows OS may operate, and ARM® is another type of ISA on which Android may operate.”, para [0003])
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to improve processing flexibility.
With regard to claim 17, Harikumar as modified discloses the processor of claim 14.
Harikumar as modified does not disclose however, Chen discloses:
further comprising: a first input/output (I/O) die (e.g. CL, 972, fig 9) associated with the first ISA and connected to the first core die; and a second I/O die (e.g. CL, 982, fig 9) associated with the second ISA and connected to the second core die (“The heterogeneous cores may include at least one core designed according to a first ISA type, and at least one core designed according to a second ISA type, where the first and second ISA types are different.”, para [0023], “In one embodiment, processors 970, 980 may implement hybrid cores as described above. Processors 970, 980 may include integrated memory and I/O control logic (“CL”) 972 and 982”, para [0088], fig 9).
Both the systems of Harikumar and Chen deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Chen to increase fault isolation.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Harikumar, Sari, and Chen
as applied to claim 8 above, and further in view of Lu et al. (U.S. Patent Application Publication No. US 20230111884 A1, hereinafter “Lu”).
With regard to claim 12, Harikumar as modified discloses the method of claim 8.
Harikumar does not disclose however, Lu discloses:
further comprising: allocating the first core die to a first virtual machine (VM) running the first operating system; and allocating the second core die to a second VM running the second operating system (“The method includes: dividing the multi-core processor to a plurality of virtualization functions, where each virtualization function corresponds to one or a plurality of processing cores; and mapping the virtualization function to a virtual machine.”, para [0021], “This shows that there may be one or a plurality of virtual functions. When there is one virtual function, all the processing cores in the multi-core processor may be divided into single virtual function; and when there are a plurality of virtual functions, the virtual machines may operate independently. Operating independently means that each virtual machine is isolated from each other, and may operate without depending on other virtual machines, and may not be influenced by other virtual machines. Besides, isolation of the present disclosure is based on hardware, so that there is less interference among the virtual machines. Besides, independent operation means that each virtual machine adopts different operating system without affecting each other.”, para [0221], fig 11, fig 20, fig 26).
Both the systems of Harikumar and Lu deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Lu to maintain isolation between workloads.
Claims 6, 13, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Harikumar,
Sari, and Chen as applied to claims 1, 8, and 14, above, and further in view of Vijayan et al. (U.S. Patent Application Publication No. US 20240036997 A1, hereinafter “Vijayan”).
With regard to claim 6, Harikumar as modified discloses the process of claim 1.
Harikumar further discloses:
further comprising: a third core die including one or more programmable logic devices (“The third partition may comprise a third number of cores and a third number of available system resources.”, para [0023], fig. 1).
However, Harikumar does not explicitly teach programmable logic devices. Vijayan discloses a system resources includes programmable logic (“system resources like processing resources (e.g., a microcontroller, a microprocessor, central processing unit core(s), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), and the like), memory, database transactions, network devices, etc.”, para [0027]).
Both the systems of Harikumar and Vijayan deal with processor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Vijayan to improve decrease processing latency.
With regard to claim 13, Harikumar as modified discloses the method of claim 8.
Harikumar further discloses:
wherein the processor further comprises a third core die including one or more programmable logic devices (“The third partition may comprise a third number of cores and a third number of available system resources.”, para [0023], fig. 1).
However, Harikumar does not explicitly teach programmable logic devices. Vijayan discloses a system resources includes programmable logic (“system resources like processing resources (e.g., a microcontroller, a microprocessor, central processing unit core(s), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), and the like), memory, database transactions, network devices, etc.”, para [0027]).
Both the systems of Harikumar and Vijayan deal with processors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Vijayan to improve decrease processing latency.
With regard to claim 18, Harikumar as modified discloses the processor of claim 14.
Harikumar further discloses:
further comprising: a third core die including one or more programmable logic devices (“The third partition may comprise a third number of cores and a third number of available system resources.”, para [0023], fig. 1).
However, Harikumar does not explicitly teach programmable logic devices. Vijayan discloses a system resources includes programmable logic (“system resources like processing resources (e.g., a microcontroller, a microprocessor, central processing unit core(s), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), and the like), memory, database transactions, network devices, etc.”, para [0027]).
Both the systems of Harikumar and Vijayan deal with processors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Vijayan to improve decrease processing latency.
With regard to claim 19, Harikumar as modified discloses the processor of claim 18.
Vijayan discloses:
wherein the one or more programmable logic devices includes one or more field-programmable gate arrays (“system resources like processing resources (e.g., a microcontroller, a microprocessor, central processing unit core(s), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), and the like), memory, database transactions, network devices, etc.”, para [0027]).
Both the systems of Harikumar and Vijayan deal with processors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Vijayan to improve decrease processing latency.
Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Harikumar, Sari,
and Chen as applied to claims 8 and 14, above, and further in view of Sinha Roy et al. (U.S. Patent Application Publication No. US 20230132500 A1, hereinafter “Sinha Roy”).
With regard to claim 9, Harikumar as modified discloses the method of claim 8.
Harikumar does not disclose however, Sinha Roy discloses:
wherein the instruction is executed on the first core die and the second core die concurrently (“The first cores 630 and the second cores 640 may simultaneously process, in parallel, a same instruction or different instructions.”, para [0079]).
Both the systems of Harikumar and Sinha Roy deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Sinha Roy to improve processor efficiency.
With regard to claim 20, Harikumar as modified discloses the processor of claim 14.
Harikumar does not disclose however, Sinha Roy discloses:
wherein the one or more processor cores of the first core die and the one or more processor cores of the second core die are configured to execute the instruction concurrently (“The first cores 630 and the second cores 640 may simultaneously process, in parallel, a same instruction or different instructions.”, para [0079]).
Both the systems of Harikumar and Sinha Roy deal with processor cores. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine Harikumar as modified in view of Sinha Roy to improve processor efficiency.
Allowable Subject Matter
Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be
allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed December 2, 2025 have been fully considered but they are not persuasive. Applicant asserts that “neither Harikumar, Sari, nor a combination of the two discloses or suggests "a voting circuitry configured to generate an output of the instruction by the processor based on the first result and the second result" as recited by claim 1.” However, the examiner maintains that Sari discloses "a voting circuitry configured to generate an output of the instruction by the processor based on the first result and the second result". Sari discloses a controller (i.e. “voting circuitry”) that is a separate core that is a means for executing steps for comparing results (para [0007], [0008], [0011]). Sari further discloses the controller compares a result from executing the first procedure on the first core (i.e. “first result”) and a result from executing the first procedure on the second core (i.e. “second result”) and deactivates a core based on the comparison (para [0018]). One of ordinary skill in the art would recognize that deactivation of a core would require an instruction (i.e. “output”) for initiating the deactivation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chin (U.S. Patent Application Publication No. US 20120023319 A1) discloses “Hypervisor 730 is a software program that facilitates secure partitioning of resources between the partitions of system 700 and management of the partitions. Hypervisor 130 enables multiple operating systems to run concurrently on system 700. Hypervisor 730 presents a virtual machine to each partition and allocates resources between the partitions. For example, the allocation of memory, processing, and hardware resources, as described above, may be facilitated by hypervisor 730. In one embodiment, hypervisor 130 may run directly on processor 702 as an operating system control.” (Chin, para [0110]) and “Hypervisor 730 may present a virtual machine to each partition. For example, a virtual machine VM1 may be presented to partition P1 and a virtual machine VM2 may be presented to partition P2. Hypervisor 730 may manage multiple operating systems executed by the partitions. Hypervisor 730 may also facilitate the management of various warm memory portions (e.g., warm memory portions 722, 728, and 729) set aside in volatile memory 704.” (Chin, para [0111]).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.S.N./Examiner, Art Unit 2192
/S. SOUGH/SPE, AU 2192