DETAILED ACTION
This action is responsive to the following: the amendments and arguments made after non-final rejection filed on July 30, 2026.
Claims 1-20 are pending. Claims 1, 9, and 18 are Independent. Claims 21-23 are new.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed on July 30, 2026 are entered. Claims 1-20 remain pending. Claims 21-23 are new.
Claim Interpretation
In claims 7 and 8 applicant describes a via connecting the gate of one MOSFET to the gate of another MOSFET of the same type. However, applicant does not describe any other structures used in forming the connection and no other structures are found in the specification making this connection other than essentially a reiteration of the claims with only a via described as making the connection. No obvious structures in the figures or description of the figures match the via described in these claims.
Further, Since CFET chips require a layer of N type devices over a layer of P type devices or vice versa, its understood that all devices of the same type exist on the same layer in the vertical metal stack. It is further understood that vias are used to provide connections through the silicon between the metal layers in a semiconductor wafer. Thus, a via would not be used as the means of connecting two devices within the same layer of the wafer, without also referencing other layers.
Therefore, since no other intermediate connecting structures can be discerned from the description and that the accepted meaning of the term “via” within context is incongruous with CFET technology in this context, the term via is interpreted to just mean an electrical connection in the context of these claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung et al (US 20240312492 A1).
Regarding Independent Claim 1, Chung teaches an apparatus (Fig. 5A: 500A) comprising:
a first write bit line (WBL) (Fig. 5A: BL_FS);
a first P-channel metal oxide semiconductor (PMOS) transistor (Fig. 5A: P3) including a source coupled to the WBL (Fig. 5A: BL_FS);
a first inverter (Fig. 5A: INV2) including an input coupled to a drain of the first PMOS transistor (Fig. 5A: P3);
a second PMOS transistor (Fig. 5A: P3) including a source coupled to an output of the first inverter (Fig. 5A: INV2), the first PMOS transistor (Fig. 5A: P3) and the second PMOS transistor (Fig. 5A: P4) disposed in at least one PMOS layer (Fig. 5B: OD-3, OD-4) configured between a first metal layer (Fig. 5B: M0) and a second metal layer (Fig. 5B: BM0);
and a first via (Fig. 5B: VG1, VG2) connecting (Fig. 5B: WL_FS) a gate (Fig. 5B: G3P, G4P) of the first PMOS transistor (Fig. 5B: P3) and a gate of the second PMOS transistor (Fig. 5B: P4) in the at least one PMOS layer to the first metal layer (Fig. 5B: M0-2, M0-5).
and a first gate connection (Fig. 3A: BCT1) connecting a gate (Fig. 3A: G2) of a first N-channel metal oxide semiconductor (NMOS) transistor (Fig. 3A: N2) of the first inverter (Fig. 2: INV2) to a source or a drain (Fig. 3A: MDLI1) of a second NMOS transistor (Fig. 3A: N1).
Regarding Claim 2, Chung teaches the limitations of Claim 1. Chung further teaches wherein the first metal layer is a Metal0 (M0) layer, the second metal layer is a Metal0b (BM0) layer, and the apparatus further comprising:
a second via connecting the M0 layer to a Metal (M1) layer.
(para 72 “The lowermost metal layer immediately over and in electrical contact with the VD, VG vias is an M0 (metal-zero) layer, a next metal layer immediately over the M0 layer is an M1 layer… A via layer Vn is arranged between and electrically couple the Mn layer and the Mn+1 layer, where n is an integer from zero and up. For example, a via-zero (V0) layer is the lowermost via layer which is arranged between and electrically couple the M0 layer and the M1 layer.”;
para 73 “The back side metal layer closest to the front side (or to the active regions OD3, OD4) is a back side M0 (BM0) layer, a next back side metal layer is a back side M1 (BM1) layer, or the like. A back side via layer BVn is arranged between and electrically couples the BMn layer and the BMn+1 layer, where n is an integer from zero and up. For example, a via layer BV0 is the back side via layer arranged between and electrically couples the BM0 layer and the BM1 layer.”)
Regarding Claim 3, Chung teaches the limitations of Claim 2. Chung further teaches further comprising:
a second WBL (WBLB) (Fig. 2: BLB_BS) coupled to a drain of the second PMOS transistor (Fig. 2: P4);
and a third via (Fig. 3C: BVG1, BVG2) connecting the WBL (Fig. 2: BL_BS) and the WBLB (Fig. 2: BLB_BS) to the BM0 layer (Fig. 3C: BM0-2, BM0-5).
Regarding Claim 4, Chung teaches the limitations of Claim 1. Chung further teaches further comprising:
a first read bit line (RBL) (Fig. 5A: BL_BS);
a first N-channel metal oxide semiconductor (NMOS) transistor (Fig. 5A: N3) including a source coupled to the first RBL (Fig. 5A: BL_BS);
and a second inverter (Fig. 5A: INV1) including an output coupled to a drain of the first NMOS transistor (Fig. 5A: N3).
Regarding Claim 5, Chung teaches the limitations of Claim 4. Chung further teaches further comprising:
a second RBL (Fig. 5A: BLB_BS);
and a second NMOS transistor (Fig. 5A: N4) including a drain coupled to the second RBL (Fig. 5A: BLB_BS), the first NMOS transistor (Fig. 5A: N3) and the second NMOS transistor (Fig. 5A: N4) disposed in at least one NMOS layer (Fig. 4G: OD-1) configured between the first metal layer (Fig. 4G: M0-3) and the PMOS layer (Fig. 4G: OD-3).
Regarding Claim 6, Chung teaches the limitations of Claim 5. Chung further teaches wherein the first inverter (Fig. 5A: INV2) comprises a third NMOS transistor (Fig. 5A: N2) and a third PMOS transistor (Fig. 5A: P2), and the second inverter (Fig. 5A: INV1) comprises a fourth NMOS transistor (Fig. 5A: N1) and a fourth PMOS transistor (Fig. 5A: P1).
Regarding Claim 7, Chung teaches the limitations of Claim 6. Chung further teaches a second via (Fig. 3A: MDLI1, BCT1) connecting a gate (Fig. 3A: G2) of the third NMOS transistor (Fig. 3A: N2) to a drain of the fourth NMOS transistor (Fig. 3A: N1).
Regarding Claim 8, Chung teaches the limitations of Claim 7. Chung further teaches a third via (Fig. 3C: MDLI2, BCT2) connecting a drain of the third PMOS (Fig. 3C: P2) transistor to a gate (Fig. 3C: G1) of the fourth PMOS transistor (Fig. 3C: P1).
Regarding Independent Claim 9, Chung teaches a memory device comprising:
a plurality of interfaces forming one or more bit lines (Fig. 1: BL0, BLn);
and a plurality of register files (Fig. 1: 112) communicatively coupled via at least one of the plurality of interfaces (Fig. 1: BL0, BLn), wherein a register file of the plurality of register files comprises:
a first write bit line (WBL) (Fig. 5A: BL_FS) of the one or more bit lines;
a first P-channel metal oxide semiconductor (PMOS) transistor (Fig. 5A: P3) including a source coupled to the WBL (Fig. 5A: BL_FS);
a second PMOS transistor (Fig. 5A: P3) including a source coupled to an output of the first inverter (Fig. 5A: INV2), the first PMOS transistor (Fig. 5A: P3) and the second PMOS transistor (Fig. 5A: P4) disposed in at least one PMOS layer (Fig. 5B: OD-3, OD-4) configured between a Metal0 (M0) layer (Fig. 5B: M0) and a Metal0b (BM0) layer (Fig. 5B: BM0);
and a first via (Fig. 5B: VG1, VG2) connecting (Fig. 5B: WL_FS) a gate (Fig. 5B: G3P, G4P) of the first PMOS transistor (Fig. 5B: P3) and a gate of the second PMOS transistor (Fig. 5B: P4) in the at least one PMOS layer to the M0 layer (Fig. 5B: M0-2, M0-5).
and a first gate connection (Fig. 3A: BCT1) connecting a gate (Fig. 3A: G2) of a first N-channel metal oxide semiconductor (NMOS) transistor (Fig. 3A: N2) of the first inverter (Fig. 2: INV2) to a source or a drain (Fig. 3A: MDLI1) of a second NMOS transistor (Fig. 3A: N1).
Regarding Claim 10, Chung teaches the limitations of Claim 9. Chung further teaches wherein the memory device is a static random access memory (SRAM) (para 18 “In at least one embodiment, each memory cell comprises a plurality of CFET devices and/or is a dual-port static random-access memory (SRAM) memory cell.”.
Regarding Claim 11, Chung teaches the limitations of Claim 9. Chung further teaches a second via connecting the M0 layer to a Metal1 (M1) layer. (para 72 “The lowermost metal layer immediately over and in electrical contact with the VD, VG vias is an M0 (metal-zero) layer, a next metal layer immediately over the M0 layer is an M1 layer… A via layer Vn is arranged between and electrically couple the Mn layer and the Mn+1 layer, where n is an integer from zero and up. For example, a via-zero (V0) layer is the lowermost via layer which is arranged between and electrically couple the M0 layer and the M1 layer.”)
Regarding Claim 12, Chung teaches the limitations of Claim 11. Chung further teaches wherein the register file further comprises:
a second WBL (WBLB) (Fig. 2: BLB_BS) coupled to a drain of the second PMOS transistor (Fig. 2: P4);
and a third via (Fig. 3C: BVG1, BVG2) connecting the WBL (Fig. 2: BL_BS) and the WBLB (Fig. 2: BLB_BS) to the BM0 layer (Fig. 3C: BM0-2, BM0-5).
Regarding Claim 13, Chung teaches the limitations of Claim 9. Chung further teaches wherein the register file further comprises:
a first read bit line (RBL) (Fig. 5A: BL_BS) of the one or more bit lines;
a first N-channel metal oxide semiconductor (NMOS) transistor (Fig. 5A: N3) including a source coupled to the first RBL (Fig. 5A: BL_BS);
and a second inverter (Fig. 5A: INV1) including an output coupled to a drain of the first NMOS transistor (Fig. 5A: N3).
Regarding Claim 14, Chung teaches the limitations of Claim 13. Chung further teaches wherein the register file further comprises:
a second RBL (Fig. 5A: BLB_BS);
and a second NMOS transistor (Fig. 5A: N4) including a drain coupled to the second RBL (Fig. 5A: BLB_BS), the first NMOS transistor (Fig. 5A: N3) and the second NMOS transistor (Fig. 5A: N4) disposed in at least one NMOS layer (Fig. 4G: OD-1) configured between the M0 layer (Fig. 4G: M0-3) and the PMOS layer (Fig. 4G: OD-3).
Regarding Claim 15, Chung teaches the limitations of Claim 14. Chung further teaches wherein the first inverter (Fig. 5A: INV2) comprises a third NMOS transistor (Fig. 5A: N2) and a third PMOS transistor (Fig. 5A: P2), and the second inverter (Fig. 5A: INV1) comprises a fourth NMOS transistor (Fig. 5A: N1) and a fourth PMOS transistor (Fig. 5A: P1).
Regarding Claim 16, Chung teaches the limitations of Claim 15. Chung further teaches a second via (Fig. 3A: MDLI1, BCT1) connecting a gate (Fig. 3A: G2) of the third NMOS transistor (Fig. 3A: N2) to a drain of the fourth NMOS transistor (Fig. 3A: N1).
Regarding Claim 17, Chung teaches the limitations of Claim 16. Chung further teaches a third via (Fig. 3C: MDLI2, BCT2) connecting a drain of the third PMOS (Fig. 3C: P2) transistor to a gate (Fig. 3C: G1) of the fourth PMOS transistor (Fig. 3C: P1).
Regarding Independent Claim 18, Chung teaches a method for configuring a register file, the method comprising:
forming a first P-channel metal oxide semiconductor (PMOS) transistor (Fig. 5A: P3) and a second PMOS transistor (Fig. 5A: P4) in at least one PMOS layer (Fig. 5B: OD-3, OD-4), the at least one PMOS layer disposed between a first metal layer (Fig. 5B: M0) and a second metal layer (Fig. 5B: BM0);
electrically coupling a source of the first PMOS transistor (Fig. 5A: P3) to a first write bit line (WBL) (Fig. 5A: BL_FS);
electrically coupling an input of a first inverter (Fig. 5A: INV2) to a drain of the first PMOS transistor (Fig. 5A: P3);
electrically coupling a source of the second PMOS transistor (Fig. 5A: P4) to an output of the first inverter (Fig. 5A: INV2),
and forming a first via (Fig. 5B: VG1, VG2) connecting a gate (Fig. 5B: G3P) of the first PMOS transistor (Fig. 5A: P3) and a gate (Fig. 5B: G4P) of the second PMOS transistor (Fig. 5A: P4) in the at least one PMOS layer to the first metal layer (Fig. 5B: M0-2, M0-5).
And forming a first gate connection (Fig. 3A: BCT1) connecting a gate (Fig. 3A: G2) of a first N-channel metal oxide semiconductor (NMOS) transistor (Fig. 3A: N2) of the first inverter (Fig. 2: INV2) to a source or a drain (Fig. 3A: MDLI1) of a second NMOS transistor (Fig. 3A: N1).
Regarding Claim 19, Chung teaches the limitations of Claim 18. Chung further teaches wherein the first metal layer is a Metal0 (M0) layer, the second metal layer is a Metal0b (BM0) layer, and the method further comprising:
forming a second via connecting the M0 layer to a Metal1 (M1) layer; (para 72 “The lowermost metal layer immediately over and in electrical contact with the VD, VG vias is an M0 (metal-zero) layer, a next metal layer immediately over the M0 layer is an M1 layer… A via layer Vn is arranged between and electrically couple the Mn layer and the Mn+1 layer, where n is an integer from zero and up. For example, a via-zero (V0) layer is the lowermost via layer which is arranged between and electrically couple the M0 layer and the M1 layer.”;
para 73 “The back side metal layer closest to the front side (or to the active regions OD3, OD4) is a back side M0 (BM0) layer, a next back side metal layer is a back side M1 (BM1) layer, or the like. A back side via layer BVn is arranged between and electrically couples the BMn layer and the BMn+1 layer, where n is an integer from zero and up. For example, a via layer BV0 is the back side via layer arranged between and electrically couples the BM0 layer and the BM1 layer.”)
electrically coupling a drain of the second PMOS transistor (Fig. 2: P4) to a second WBL (WBLB) (Fig. 2: BLB_BS);
and forming a third via (Fig. 3C: BVG1, BVG2) connecting the WBL (Fig. 2: BL_BS) and the WBLB (Fig. 2: BLB_BS) to the BM0 layer (Fig. 3C: BM0-2, BM0-5).
Regarding Claim 20, Chung teaches the limitations of Claim 18. Chung further teaches electrically coupling a source of a first N-channel metal oxide semiconductor (NMOS) transistor (Fig. 5A: N3) to a first read bit line (RBL) (Fig. 5A: BL_BS);
electrically coupling a drain of the first NMOS transistor (Fig. 5A: N3) to an output of a second inverter (Fig. 5A: INV1);
forming a second via (Fig. 3A: MDLI1, BCT1) connecting a gate (Fig. 3A: G2) of a third NMOS transistor (Fig. 3A: N2) of the first inverter (Fig. 5A: INV2) to a drain of a fourth NMOS transistor (Fig. 3A: N1) of the second inverter (Fig. 5A: INV1);
and forming a third via (Fig. 3C: MDLI2, BCT2) connecting a drain of a third PMOS transistor (Fig. 3C: P2) of the first inverter (Fig. 5A: INV2) to a gate (Fig. 3C: G1) of a fourth PMOS transistor (Fig. 3C: P1) of the second inverter (Fig. 5A: INV1).
Regarding Claim 21, Chung teaches the limitations of Claim 1. Chung further teaches a second gate connection (Fig. 3A: BCT1) connecting a gate of the third PMOS transistor (Fig. 3C: P2) of the first inverter (Fig. 2: INV2) to a source or a drain (Fig. 3C: MDLI 1) of the fourth PMOS transistor (Fig. 3C: P1) of the second inverter (Fig. 2: INV1).
Regarding Claim 22, Chung teaches the limitations of Claim 15. This claim is rejected for the same reasons as Claim 21.
Regarding Claim 23, Chung teaches the limitations of Claim 20. This claim is rejected for the same reasons as Claims 21 and 22.
Response to Arguments
Applicant's arguments filed July 30, 2026 have been fully considered but they are not persuasive.
Applicants arguments deal primarily with the amendments to claims 1, 9 and 18 which all about that a source drain of the pulldown NMOS transistor in an inverter being connected to the gate of the pull down NMOS transistor in the other cross coupled inverted. Applicant’s arguments as to how Chung, which also recites cross coupled inverters made from CFET devices, fails to anticipate this are not persuasive for the following two reasons.
First applicant asserts that MDLI1 structures recited by applicant do not couple the source/drain of the NMOS transistors, however the MDLI structure clearly is clearly making an electrical connection to the source and drain of NMOS transistors based on the figures presented in Chung such as Fig. 4A. This MDLI structure is then directly connected to the BCT structure which connects the source/drain region of the NMOS transistors of one active region to gate structure extending from another active region of NMOS transistors. The BCT structure appears to function identically to the GCN structure in Fig. 14 presented by applicant.
Secondly the “gate connection structure” has no further description other than that the “Indicates a connection between the NMOS poly/gate to the NMOS source/drain.” This is a broad description and the BCT meets this providing a connection the MDLI region which couples multiple source/drain regions of multiple transistor together. Thus as best can be understood applicant’s argument as to how the amendments overcomes the prior art is entirely a semantic argument. The “gate connect structure” appears to be identical to the BCT structure and serve the same purpose.
Therefore, the rejection under 35 U.S.C. 102 is maintained.
Finally, applicant argues that the MDLI and BCT structures are not analogous to the “vias” described in claims 7 and 8. However, based on the interpretation of via from the written description presented by applicant these structures are anticipated by Chung. Therefore, the rejection under 35 U.S.C. 102 of these claims is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/Donald HB Braswell/ Primary Examiner, Art Unit 2825
