DETAILED ACTION
This action is responsive to the following: the application filed on March 27th 2023 and the information disclosure statement filed on January 26, 2026.
Claims 1-20 are pending. Claims 1, 9, and 18 are Independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 26, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung et al (US 20240312492 A1).
Regarding Independent Claim 1, Chung teaches an apparatus (Fig. 5A: 500A) comprising:
a first write bit line (WBL) (Fig. 5A: BL_FS);
a first P-channel metal oxide semiconductor (PMOS) transistor (Fig. 5A: P3) including a source coupled to the WBL (Fig. 5A: BL_FS);
a first inverter (Fig. 5A: INV2) including an input coupled to a drain of the first PMOS transistor (Fig. 5A: P3);
a second PMOS transistor (Fig. 5A: P3) including a source coupled to an output of the first inverter (Fig. 5A: INV2), the first PMOS transistor (Fig. 5A: P3) and the second PMOS transistor (Fig. 5A: P4) disposed in at least one PMOS layer (Fig. 5B: OD-3, OD-4) configured between a first metal layer (Fig. 5B: M0) and a second metal layer (Fig. 5B: BM0);
and a first via (Fig. 5B: VG1, VG2) connecting (Fig. 5B: WL_FS) a gate (Fig. 5B: G3P, G4P) of the first PMOS transistor (Fig. 5B: P3) and a gate of the second PMOS transistor (Fig. 5B: P4) in the at least one PMOS layer to the first metal layer (Fig. 5B: M0-2, M0-5).
Regarding Claim 2, Chung teaches the limitations of Claim 1. Chung further teaches wherein the first metal layer is a Metal0 (M0) layer, the second metal layer is a Metal0b (BM0) layer, and the apparatus further comprising:
a second via connecting the M0 layer to a Metal (M1) layer.
(para 72 “The lowermost metal layer immediately over and in electrical contact with the VD, VG vias is an M0 (metal-zero) layer, a next metal layer immediately over the M0 layer is an M1 layer… A via layer Vn is arranged between and electrically couple the Mn layer and the Mn+1 layer, where n is an integer from zero and up. For example, a via-zero (V0) layer is the lowermost via layer which is arranged between and electrically couple the M0 layer and the M1 layer.”;
para 73 “The back side metal layer closest to the front side (or to the active regions OD3, OD4) is a back side M0 (BM0) layer, a next back side metal layer is a back side M1 (BM1) layer, or the like. A back side via layer BVn is arranged between and electrically couples the BMn layer and the BMn+1 layer, where n is an integer from zero and up. For example, a via layer BV0 is the back side via layer arranged between and electrically couples the BM0 layer and the BM1 layer.”)
Regarding Claim 3, Chung teaches the limitations of Claim 2. Chung further teaches further comprising:
a second WBL (WBLB) (Fig. 2: BLB_BS) coupled to a drain of the second PMOS transistor (Fig. 2: P4);
and a third via (Fig. 3C: BVG1, BVG2) connecting the WBL (Fig. 2: BL_BS) and the WBLB (Fig. 2: BLB_BS) to the BM0 layer (Fig. 3C: BM0-2, BM0-5).
Regarding Claim 4, Chung teaches the limitations of Claim 1. Chung further teaches further comprising:
a first read bit line (RBL) (Fig. 5A: BL_BS);
a first N-channel metal oxide semiconductor (NMOS) transistor (Fig. 5A: N3) including a source coupled to the first RBL (Fig. 5A: BL_BS);
and a second inverter (Fig. 5A: INV1) including an output coupled to a drain of the first NMOS transistor (Fig. 5A: N3).
Regarding Claim 5, Chung teaches the limitations of Claim 4. Chung further teaches further comprising:
a second RBL (Fig. 5A: BLB_BS);
and a second NMOS transistor (Fig. 5A: N4) including a drain coupled to the second RBL (Fig. 5A: BLB_BS), the first NMOS transistor (Fig. 5A: N3) and the second NMOS transistor (Fig. 5A: N4) disposed in at least one NMOS layer (Fig. 4G: OD-1) configured between the first metal layer (Fig. 4G: M0-3) and the PMOS layer (Fig. 4G: OD-3).
Regarding Claim 6, Chung teaches the limitations of Claim 5. Chung further teaches wherein the first inverter (Fig. 5A: INV2) comprises a third NMOS transistor (Fig. 5A: N2) and a third PMOS transistor (Fig. 5A: P2), and the second inverter (Fig. 5A: INV1) comprises a fourth NMOS transistor (Fig. 5A: N1) and a fourth PMOS transistor (Fig. 5A: P1).
Regarding Claim 7, Chung teaches the limitations of Claim 6. Chung further teaches a second via (Fig. 3A: MDLI1, BCT1) connecting a gate (Fig. 3A: G2) of the third NMOS transistor (Fig. 3A: N2) to a drain of the fourth NMOS transistor (Fig. 3A: N1).
Regarding Claim 8, Chung teaches the limitations of Claim 7. Chung further teaches a third via (Fig. 3C: MDLI2, BCT2) connecting a drain of the third PMOS (Fig. 3C: P2) transistor to a gate (Fig. 3C: G1) of the fourth PMOS transistor (Fig. 3C: P1).
Regarding Independent Claim 9, Chung teaches a memory device comprising:
a plurality of interfaces forming one or more bit lines (Fig. 1: BL0, BLn);
and a plurality of register files (Fig. 1: 112) communicatively coupled via at least one of the plurality of interfaces (Fig. 1: BL0, BLn), wherein a register file of the plurality of register files comprises:
a first write bit line (WBL) (Fig. 5A: BL_FS) of the one or more bit lines;
a first P-channel metal oxide semiconductor (PMOS) transistor (Fig. 5A: P3) including a source coupled to the WBL (Fig. 5A: BL_FS);
a second PMOS transistor (Fig. 5A: P3) including a source coupled to an output of the first inverter (Fig. 5A: INV2), the first PMOS transistor (Fig. 5A: P3) and the second PMOS transistor (Fig. 5A: P4) disposed in at least one PMOS layer (Fig. 5B: OD-3, OD-4) configured between a Metal0 (M0) layer (Fig. 5B: M0) and a Metal0b (BM0) layer (Fig. 5B: BM0);
and a first via (Fig. 5B: VG1, VG2) connecting (Fig. 5B: WL_FS) a gate (Fig. 5B: G3P, G4P) of the first PMOS transistor (Fig. 5B: P3) and a gate of the second PMOS transistor (Fig. 5B: P4) in the at least one PMOS layer to the M0 layer (Fig. 5B: M0-2, M0-5).
Regarding Claim 10, Chung teaches the limitations of Claim 9. Chung further teaches wherein the memory device is a static random access memory (SRAM) (para 18 “In at least one embodiment, each memory cell comprises a plurality of CFET devices and/or is a dual-port static random-access memory (SRAM) memory cell.”.
Regarding Claim 11, Chung teaches the limitations of Claim 9. Chung further teaches a second via connecting the M0 layer to a Metal1 (M1) layer. (para 72 “The lowermost metal layer immediately over and in electrical contact with the VD, VG vias is an M0 (metal-zero) layer, a next metal layer immediately over the M0 layer is an M1 layer… A via layer Vn is arranged between and electrically couple the Mn layer and the Mn+1 layer, where n is an integer from zero and up. For example, a via-zero (V0) layer is the lowermost via layer which is arranged between and electrically couple the M0 layer and the M1 layer.”)
Regarding Claim 12, Chung teaches the limitations of Claim 11. Chung further teaches wherein the register file further comprises:
a second WBL (WBLB) (Fig. 2: BLB_BS) coupled to a drain of the second PMOS transistor (Fig. 2: P4);
and a third via (Fig. 3C: BVG1, BVG2) connecting the WBL (Fig. 2: BL_BS) and the WBLB (Fig. 2: BLB_BS) to the BM0 layer (Fig. 3C: BM0-2, BM0-5).
Regarding Claim 13, Chung teaches the limitations of Claim 9. Chung further teaches wherein the register file further comprises:
a first read bit line (RBL) (Fig. 5A: BL_BS) of the one or more bit lines;
a first N-channel metal oxide semiconductor (NMOS) transistor (Fig. 5A: N3) including a source coupled to the first RBL (Fig. 5A: BL_BS);
and a second inverter (Fig. 5A: INV1) including an output coupled to a drain of the first NMOS transistor (Fig. 5A: N3).
Regarding Claim 14, Chung teaches the limitations of Claim 13. Chung further teaches wherein the register file further comprises:
a second RBL (Fig. 5A: BLB_BS);
and a second NMOS transistor (Fig. 5A: N4) including a drain coupled to the second RBL (Fig. 5A: BLB_BS), the first NMOS transistor (Fig. 5A: N3) and the second NMOS transistor (Fig. 5A: N4) disposed in at least one NMOS layer (Fig. 4G: OD-1) configured between the M0 layer (Fig. 4G: M0-3) and the PMOS layer (Fig. 4G: OD-3).
Regarding Claim 15, Chung teaches the limitations of Claim 14. Chung further teaches wherein the first inverter (Fig. 5A: INV2) comprises a third NMOS transistor (Fig. 5A: N2) and a third PMOS transistor (Fig. 5A: P2), and the second inverter (Fig. 5A: INV1) comprises a fourth NMOS transistor (Fig. 5A: N1) and a fourth PMOS transistor (Fig. 5A: P1).
Regarding Claim 16, Chung teaches the limitations of Claim 15. Chung further teaches a second via (Fig. 3A: MDLI1, BCT1) connecting a gate (Fig. 3A: G2) of the third NMOS transistor (Fig. 3A: N2) to a drain of the fourth NMOS transistor (Fig. 3A: N1).
Regarding Claim 17, Chung teaches the limitations of Claim 16. Chung further teaches a third via (Fig. 3C: MDLI2, BCT2) connecting a drain of the third PMOS (Fig. 3C: P2) transistor to a gate (Fig. 3C: G1) of the fourth PMOS transistor (Fig. 3C: P1).
Regarding Independent Claim 18, Chung teaches a method for configuring a register file, the method comprising:
forming a first P-channel metal oxide semiconductor (PMOS) transistor (Fig. 5A: P3) and a second PMOS transistor (Fig. 5A: P4) in at least one PMOS layer (Fig. 5B: OD-3, OD-4), the at least one PMOS layer disposed between a first metal layer (Fig. 5B: M0) and a second metal layer (Fig. 5B: BM0);
electrically coupling a source of the first PMOS transistor (Fig. 5A: P3) to a first write bit line (WBL) (Fig. 5A: BL_FS);
electrically coupling an input of a first inverter (Fig. 5A: INV2) to a drain of the first PMOS transistor (Fig. 5A: P3);
electrically coupling a source of the second PMOS transistor (Fig. 5A: P4) to an output of the first inverter (Fig. 5A: INV2),
and forming a first via (Fig. 5B: VG1, VG2) connecting a gate (Fig. 5B: G3P) of the first PMOS transistor (Fig. 5A: P3) and a gate (Fig. 5B: G4P) of the second PMOS transistor (Fig. 5A: P4) in the at least one PMOS layer to the first metal layer (Fig. 5B: M0-2, M0-5).
Regarding Claim 19, Chung teaches the limitations of Claim 18. Chung further teaches wherein the first metal layer is a Metal0 (M0) layer, the second metal layer is a Metal0b (BM0) layer, and the method further comprising:
forming a second via connecting the M0 layer to a Metal1 (M1) layer; (para 72 “The lowermost metal layer immediately over and in electrical contact with the VD, VG vias is an M0 (metal-zero) layer, a next metal layer immediately over the M0 layer is an M1 layer… A via layer Vn is arranged between and electrically couple the Mn layer and the Mn+1 layer, where n is an integer from zero and up. For example, a via-zero (V0) layer is the lowermost via layer which is arranged between and electrically couple the M0 layer and the M1 layer.”;
para 73 “The back side metal layer closest to the front side (or to the active regions OD3, OD4) is a back side M0 (BM0) layer, a next back side metal layer is a back side M1 (BM1) layer, or the like. A back side via layer BVn is arranged between and electrically couples the BMn layer and the BMn+1 layer, where n is an integer from zero and up. For example, a via layer BV0 is the back side via layer arranged between and electrically couples the BM0 layer and the BM1 layer.”)
electrically coupling a drain of the second PMOS transistor (Fig. 2: P4) to a second WBL (WBLB) (Fig. 2: BLB_BS);
and forming a third via (Fig. 3C: BVG1, BVG2) connecting the WBL (Fig. 2: BL_BS) and the WBLB (Fig. 2: BLB_BS) to the BM0 layer (Fig. 3C: BM0-2, BM0-5).
Regarding Claim 20, Chung teaches the limitations of Claim 18. Chung further teaches electrically coupling a source of a first N-channel metal oxide semiconductor (NMOS) transistor (Fig. 5A: N3) to a first read bit line (RBL) (Fig. 5A: BL_BS);
electrically coupling a drain of the first NMOS transistor (Fig. 5A: N3) to an output of a second inverter (Fig. 5A: INV1);
forming a second via (Fig. 3A: MDLI1, BCT1) connecting a gate (Fig. 3A: G2) of a third NMOS transistor (Fig. 3A: N2) of the first inverter (Fig. 5A: INV2) to a drain of a fourth NMOS transistor (Fig. 3A: N1) of the second inverter (Fig. 5A: INV1);
and forming a third via (Fig. 3C: MDLI2, BCT2) connecting a drain of a third PMOS transistor (Fig. 3C: P2) of the first inverter (Fig. 5A: INV2) to a gate (Fig. 3C: G1) of a fourth PMOS transistor (Fig. 3C: P1) of the second inverter (Fig. 5A: INV1).
Conclusion
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825
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