CTNF 18/126,702 CTNF 76805 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 16 and 19-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Chang et al. US Patent Pub. No. 2021/0375761 . Regarding claim 16, Chang teaches forming a pattern layer, wherein the pattern layer includes a structure for a back side interconnect metal layer (the forming of layer 140) [0085]; forming a transistor layer on the pattern layer (55/64) (Fig 15C) forming a front side interconnect metal layer on the transistor layer, wherein the front side metal layer is electrically coupled with the transistor layer (120)[0071]; and forming the back side metal layer (conductive lines 133, 134) by metallizing the pattern layer[0086]. Regarding claim 19, Chang teaches wherein the pattern layer includes a sacrificial material deposited within an interlayer dielectric; and further comprising replacing the sacrificial material with an electrically conductive material [0078-0086]. Regarding claim 20, Chang teaches wherein the electrically conductive material includes a selected one or more of: copper, aluminum or titanium [0088] . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1 and 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. US Patent Pub. No. 2021/0375761 . Regarding claim 1, Chang teaches a first layer that includes a plurality of transistors (Fig. 15C, 55/64, gate 52A-C [0056]) (transistor array [0122]); a second layer (an interconnect structure 120) above the first layer [0071], the second layer includes a first plurality of contacts (first conductive features 122) that are electrically coupled with a first set of the plurality of transistors [0071]; a third layer below the first layer, the third layer (the second dielectric layer (125) [0081]) includes a second plurality of contacts (a backside interconnect structure 140, [0085]) that are electrically coupled with a second set of the plurality of transistors (transistor array [0122]) (Fig. 15C, 55/64, 54A-C [0056]); and wherein at least one of the first plurality of contacts in the second layer moves away from the first layer, and wherein at least one of the second plurality of contacts in the third layer moves away from the first layer ([0071],[0085]). Chang does not disclose wherein at least one of the first plurality of contacts in the second layer tapers away from the first layer, and wherein at least one of the second plurality of contacts in the third layer tapers away from the first layer. While Chang does not teach the tapering away from the first layer, the examiner takes the position that this is just a design feature and not a technically significant feature (in re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having at least one of the first plurality of contacts in the second layer tapers away from the first layer, and wherein at least one of the second plurality of contacts in the third layer tapers away from the first layer, by choosing the shape of the interconnect (in re Daily) in order to provide power to the transistor array. Regarding claim 4, Chang teaches wherein the first plurality of contacts are directly electrically coupled with the first set of the plurality of transistors, and wherein the second plurality of contacts are directly electrically coupled with the second set of the plurality of transistors (Fig 34 B, first source/drain coupled to second source/drain, [0121]. Regarding claim 5, Chang teaches the second layer is a part of front side interconnect metal layer structure (120) [0072-0073], and wherein the third layer is a part of a back side interconnect metal layer structure (140)[0085-0087]. Regarding claim 6, Chang teaches the at least one of the first plurality of contacts includes a first metal via (120) [0072-0073], and wherein the at least one of the second plurality of contacts includes a second metal via (140) [0085-0087]. Regarding claim 7, Chang teaches the first plurality of contacts or the second plurality of contacts include a selected one or more of: copper, cobalt, molybdenum, ruthenium, or tungsten [0088] . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2-3 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 12-151-07 AIA 07-97 12-51-07 Claim s 9-15 are allowed. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: wherein a slope of a side of one of the first plurality of metal contacts is at a first angle with respect to a plane of the first layer, wherein the first angle is less than 90 o , and wherein a slope of a side of one of the second plurality of metal contacts is at a second angle with respect to the plane of the first layer, wherein the second angle is less than 90 o , as required by claim 9 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WALTER LEE LINDSAY JR whose telephone number is (571)272-1674. The examiner can normally be reached Monday-Thursday 9-7. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allana Lewin Bidder can be reached at 571-272-5560. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WALTER L LINDSAY JR/Supervisory Patent Examiner, Art Unit 2852 Application/Control Number: 18/126,702 Page 2 Art Unit: 2852 Application/Control Number: 18/126,702 Page 3 Art Unit: 2852 Application/Control Number: 18/126,702 Page 4 Art Unit: 2852 Application/Control Number: 18/126,702 Page 5 Art Unit: 2852 Application/Control Number: 18/126,702 Page 6 Art Unit: 2852 Application/Control Number: 18/126,702 Page 7 Art Unit: 2852
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