DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to claim amendments filed 08/12/2025. Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/20/2026 and 02/17/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 5-12, and 14-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claims 1-3 and 5-9 are drawn to method (i.e., a process), claims 10-12 and 14-18 are drawn to a device (i.e., a machine/manufacture), and claims 19-20 are drawn to non-transitory computer readable medium (i.e., a machine/manufacture). As such, claims 1-3, 5-12, and 14-20 are drawn to one of the statutory categories of invention.
Claims 1-3, 5-12, and 14-20 are directed to determining a number of remaining copies of data and a delay for each of a plurality of cables. Specifically, the claims recite “determining, for a given cable of the plurality of cables, a number of remaining copies to be generated, wherein the number of remaining copies of data to be generated comprises a total number of cables in the plurality of cables minus a number of completed copies of data; determining a delay for each of the plurality of cables, wherein the delay for a respective cable is based on: the remaining number of copies of data to be generated, and a length of time to make each copy of data”, which is grouped within the Mathematical Concepts and is similar to the concept of mathematical formulas or equations grouping of abstract ideas in prong one of step 2A of the Alice/Mayo test (See 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50, 52, 54 (January 7, 2019)). Accordingly, the claims recite an abstract idea (See pages 7, 10, Alice Corporation Pty. Ltd. v. CLS Bank International, et al., US Supreme Court, No. 13-298, June 19, 2014; 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50, 53-54 (January 7, 2019)).
This judicial exception is not integrated into a practical application because, when analyzed under prong two of step 2A of the Alice/Mayo test (See 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50, 54-55 (January 7, 2019)), the additional element(s) of the claim(s) such as one or more processors and a non-transitory storage medium merely use(s) a computer as a tool to perform an abstract idea and/or generally link(s) the use of a judicial exception to a particular technological environment. Specifically, the one or more processors and a non-transitory storage medium perform(s) the steps or functions of “determining, for a given cable of the plurality of cables, a number of remaining copies to be generated, wherein the number of remaining copies of data to be generated comprises a total number of cables in the plurality of cables minus a number of completed copies of data; determining a delay for each of the plurality of cables, wherein the delay for a respective cable is based on: the remaining number of copies of data to be generated, and a length of time to make each copy of data”. The use of a processor/computer as a tool to implement the abstract idea and/or generally linking the use of the abstract idea to a particular technological environment does not integrate the abstract idea into a practical application because it requires no more than a computer performing functions that correspond to acts required to carry out the abstract idea. The additional elements do not involve improvements to the functioning of a computer, or to any other technology or technical field (MPEP 2106.05(a)), the claims do not apply or use the abstract idea to effect a particular treatment or prophylaxis for a disease or medical condition (Vanda Memo), the claims do not apply the abstract idea with, or by use of, a particular machine (MPEP 2106.05(b)), the claims do not effect a transformation or reduction of a particular article to a different state or thing (MPEP 2106.05(c)), and the claims do not apply or use the abstract idea in some other meaningful way beyond generally linking the use of the abstract idea to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception (MPEP 2106.05(e) and Vanda Memo). Therefore, the claims do not, for example, purport to improve the functioning of a computer. Nor do they effect an improvement in any other technology or technical field. Accordingly, the additional elements do not impose any meaningful limits on practicing the abstract idea, and the claims are directed to an abstract idea.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because, when analyzed under step 2B of the Alice/Mayo test (See 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50, 52, 56 (January 7, 2019)), the additional element(s) of using a one or more processors and a non-transitory storage medium to perform the steps amounts to no more than using a computer or processor to automate and/or implement the abstract idea of determining a number of remaining copies of data and a delay for each of a plurality of cables. The additional element of “identifying a plurality of cables at a network switch” amounts to mere data gathering, which is a form of insignificant extra-solution activity and is not sufficient to integrate the abstract idea into a practical application. The additional element of “programming optics hardware for the respective cable” merely describes how to generally “apply” the otherwise mental judgements in a generic or general purpose optics environment and is not sufficient to integrate the abstract idea into a practical application. As discussed above, taking the claim elements separately, the one or more processors and a non-transitory storage medium perform(s) the steps or functions of “determining, for a given cable of the plurality of cables, a number of remaining copies to be generated, wherein the number of remaining copies of data to be generated comprises a total number of cables in the plurality of cables minus a number of completed copies of data; determining a delay for each of the plurality of cables, wherein the delay for a respective cable is based on: the remaining number of copies of data to be generated, and a length of time to make each copy of data”. These functions correspond to the actions required to perform the abstract idea. Viewed as a whole, the combination of elements recited in the claims merely recite the concept of determining a number of remaining copies of data and a delay for each of a plurality of cables. Therefore, the use of these additional elements does no more than employ the computer as a tool to automate and/or implement the abstract idea. The use of a computer or processor to merely automate and/or implement the abstract idea cannot provide significantly more than the abstract idea itself (MPEP 2106.05(I)(A)(f) & (h)). Therefore, the claim is not patent eligible.
Dependent claims 2, 3, 8, 11, 12, 17, and 20 generally describe the optics hardware and recite elements that merely describe how to generally “apply” the otherwise mental judgements in a generic or general purpose optics environment and are not sufficient to integrate the abstract idea into a practical application. Dependent claims 5-7, 9, 14-16, and 18 further describe the abstract idea of determining a number of remaining copies of data and a delay for each of a plurality of cables and are not sufficient to integrate the abstract idea into a practical application. Therefore, the dependent claims 2, 3, 5-9, 11, 12, 14-18, and 20 are also not patent eligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 6-10, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Rojas Calvente (US 2025/0088272), hereinafter "Rojas", in view of Matthews et al. (US 12,395,260), hereinafter “Matthews”.
Regarding claims 1, 10, 19, Rojas teaches:
A method or a device, comprising:
one or more processors, the one or more processors configured see Rojas, Fig. 3, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor, and see Rojas, par. [0052]: Based on the detection information provided by each signal detector 111, the controller 110 is configured to determine an individual delay for the individual signal path) to:
identifying, by one or more processors, a plurality of cables at a network switch (see Rojas, Fig. 5, par. [0053]: The method comprises the following steps of the time-alignment subsystem 100: detecting in step S501, on the individual cable 211, an individual copy of an incoming signal received by a corresponding OFE 210, and see Rojas, par. [0047]: The signal copy from an OFE 210 with the longest cable may be detected the latest, and therefore a direct path may be selected without adding any additional delay. For the other signal paths, a corresponding switch may be controlled to select a corresponding delay element, which is inversely correlated to the delay in time of arrival (therefore also inversely proportional to a corresponding cable length), and see Rojas, par. [0045]: The optical transceiver 200 comprises a common baseband module 220, an analog front end, AFE, module 230, a summing amplifier 240, a time-alignment subsystem 100, a plurality of cables 211, and a plurality of OFEs 210, and see Rojas, Fig. 3, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210, and see Rojas, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor; in this case, copies of an incoming signal can be detected on individual cables of a plurality of cables, corresponding to identifying a plurality of cables);
determining, by the one or more processors, a delay for each of the plurality of cables (see Rojas, Fig. 5, par. [0053]: determining, in step S502, an individual delay for an individual signal path of each individual cable 211 based on the detection information, and see Rojas, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor, and see Rojas, par. [0052]: Based on the detection information provided by each signal detector 111, the controller 110 is configured to determine an individual delay for the individual signal path), and
programming, by the one or more processors based on the delay for the respective cable, optics hardware for the respective cable (see Rojas, Fig. 5, par. [0053]: in step S503, selectively adding the individual delay to the individual signal path of each individual cable 211 to improve time-alignment among the plurality of signal paths, and see Rojas, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor, and see Rojas, par. [0052]: Based on the detection information provided by each signal detector 111, the controller 110 is configured to determine an individual delay for the individual signal path; in this case, adding the delay to each signal path of each cable corresponds to programming optics hardware based on the delay).
However, Rojas does not teach:
A non-transitory storage medium, the storage medium including instructions that when executed by one or more processors, cause the one or more processors
determining, by one or more processors, for a given cable of the plurality of cables, a number of remaining copies of data to be generated, wherein the number of remaining copies of data to be generated comprises a total number of cables in the plurality of cables minus a number of completed copies of data;
wherein the delay for a respective cable is based on:
the remaining number of copies of data to be generated, and
a length of time to make each copy of data;
Matthews, in the same field of endeavor, teaches:
A non-transitory storage medium, the storage medium including instructions that when executed by one or more processors, cause the one or more processors (see Matthews, col. 38, lines 55-58: a non-transitory computer readable storage medium, storing software instructions, which when executed by one or more processors cause performance of any of the foregoing methods)
determining, by one or more processors, for a given cable of the plurality of cables, a number of remaining copies of data to be generated, wherein the number of remaining copies of data to be generated comprises a total number of cables in the plurality of cables minus a number of completed copies of data (see Matthews, Fig. 4, col. 20, lines 53-62: Copy information (or CI) is provided by copy information lookup operations 430 for the same source node packet and enqueued (e.g., with a reference counter indicating how many copies to be made, etc.) into a respective queue associated with each egress port of one or more egress ports in the multi-destination group. On dequeuing (after the copy information lookup operations 430), the CI can be used to indicate or determine how many copies (e.g., through the reference counter, etc.) to make from the head of the respective queue, and see col. 21, lines 3-14: The traffic manager can be configured to generate and enqueue up to a specific number of different sets of copy information each clock cycle to egress port(s) specified by the multi-destination lookup table entry or entries and/or bound to the traffic manager. In some operational scenarios, the traffic manager may not be able to generate and enqueue different sets of copy information corresponding to all of the further copies of the multi-destination or broadcast copy of the same source node packet in the same clock cycle, but rather generate and enqueue these sets of copy information at least serially in part, thereby generating enqueue delay variations among the different sets of copy information, and see col. 21, lines 18-26: the traffic manager's generation of sets of copy information for the same source node packet begins at the lowest port number among the egress ports identified in a multi-destination group from the multi-destination table port lookup operations 410 and ends at the highest port number in the MC Group. The lower enqueue delays are hence incurred for egress ports assigned lower port numbers as compared with other egress ports assigned higher port numbers, and see col. 5, lines 20-21: The communication links may be any suitable wired cabling or wireless links; in this case, the determined copy information includes information on how many copies to be made. The associated delay for each position in queue is assigned based on how many copies to be made and position in queue, i.e. the queueing corresponding to determining the number of remaining copies as the total number of paths (i.e. cables) minus completed copies);
wherein the delay for a respective cable is based on:
the remaining number of copies of data to be generated (see Matthews, Fig. 4, col. 22, line 63-col. 23, line 11: the traffic manager may determine or select the specific future time to account for the enqueue/dequeue related delay variations, some or all prior delay variations before the enqueue/dequeue related delay variations incurred by the traffic manager and/or queuing logic of egress ports, and/or some or all subsequent delay variations after the enqueue/dequeue related delay variations incurred by the traffic manager and/or queuing logic of egress ports. These prior and/or subsequent delay variations may include, but are not necessarily limited to only, any, some or all of switching fabric delay variations, replication delay variations, enqueue/dequeue delay variations (e.g., incurred by processing logic or traffic managers of other nodes, etc.), transmit buffer-to-port TX delay variations (e.g., incurred by processing logic or egress ports of other nodes, etc.), ingress-port-to-ingress-buffer delay variations, and see col. 26, lines 29-46: a first copy (corresponding to CI-1) of the received packet may have a first dequeue equalization time (denoted as “DET-1”) to compensate for a relatively large or largest switch delay (or with the largest delay variation relative to the average or minimum delay). As a result, the first copy (P-1 corresponding to CI-1 and DET-1) departs from the queue schedulers 460 to a first transmit buffer of a first port first in accordance with the first dequeue equalization time (DET-1). In comparison, a N-th copy (corresponding to CI-N) of the received packet may have a N-th dequeue equalization time (denoted as “DET-N”) to compensate for a relatively small or smallest switch delay (or with the smallest delay variation relative to the average or minimum delay). As a result, the N-th copy (P-N corresponding to CI-N and DET-N) departs from the queue schedulers 460 to a N-th transmit buffer of a N-th port last in accordance with the N-th dequeue equalization time (DET-N); in this case, changing delay based on position in queue for synchronizing corresponds to the delay being based on number of remaining copies), and
a length of time to make each copy of data (see Matthews, Fig. 3A, col. 21, lines 55-65: As an example of variations in transmit-buffer-to-port-TX delays, as shown in FIG. 3A, physical, electrical or medium related distances (denoted as “d1”, “d2”, . . . “dN-1” and “dN”, where d1<d2< . . . dN-1<dN) from a transmit buffer to individual port logic instances (e.g., MAC, SerDes, etc.) of different egress ports 290-1, 290-2, . . . 290-(N−1), 290-N varies. Additionally, optionally or alternatively, delays and delay variations may be incurred by serialization and deserialization performed as a part of providing packets for transmission by egress ports. Hence, packets can depart earlier from the port 290-1 than the port 290-N; in this case, the delay from the buffer to each cable corresponds to a delay based on length of time to make each copy);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the method of Rojas with the specific delay of Matthews with a reasonable expectation of success. One of ordinary skill in the art would have been motivated to make this modification for the benefit of preventing delay variations in order to synchronize communication (see Matthews, col. 3, lines 15-28 and col. 3, line 63-col. 4, line 9).
Regarding claims 6, 15, the combination of Rojas in view of Matthews teaches the method or device.
Rojas further teaches:
further comprising:
determining, by the one or more processors, a length of each cable (see Rojas, Fig. 3, pars. [0046-0047]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor. The controller 110 measures and determines the difference in time of arrivals of the different copies received by the different OFEs 210. Based on this time difference, the controller 110 decides to apply a correction to this difference in phase (or time of arrival/delay) among the different copies by selectively activating an individual delay element of a corresponding signal path. The signal copy from an OFE 210 with the longest cable may be detected the latest, and therefore a direct path may be selected without adding any additional delay. For the other signal paths, a corresponding switch may be controlled to select a corresponding delay element, which is inversely correlated to the delay in time of arrival (therefore also inversely proportional to a corresponding cable length), and see Rojas, par. [0026]: The controller derives individual delays for different signal paths to compensate the difference in arrival time, and see Rojas, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor, and see Rojas, par. [0052]: Based on the detection information provided by each signal detector 111, the controller 110 is configured to determine an individual delay for the individual signal path; in this case, a difference in time of arrival (corresponding to cable length) is determined, and a delay for shorter cables is determined based on the difference in arrival time); and
determining, by the one or more processors, a second delay based on the length of each cable (see Rojas, Fig. 3, pars. [0046-0047]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor. The controller 110 measures and determines the difference in time of arrivals of the different copies received by the different OFEs 210. Based on this time difference, the controller 110 decides to apply a correction to this difference in phase (or time of arrival/delay) among the different copies by selectively activating an individual delay element of a corresponding signal path. The signal copy from an OFE 210 with the longest cable may be detected the latest, and therefore a direct path may be selected without adding any additional delay. For the other signal paths, a corresponding switch may be controlled to select a corresponding delay element, which is inversely correlated to the delay in time of arrival (therefore also inversely proportional to a corresponding cable length), and see Rojas, par. [0026]: The controller derives individual delays for different signal paths to compensate the difference in arrival time, and see Rojas, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor, and see Rojas, par. [0052]: Based on the detection information provided by each signal detector 111, the controller 110 is configured to determine an individual delay for the individual signal path; in this case, a difference in time of arrival (corresponding to cable length) is determined, and a delay for shorter cables is determined based on the difference in arrival time).
Regarding claims 7, 16, the combination of Rojas in view of Matthews teaches the method or device.
Rojas further teaches:
wherein determining the second delay further comprises:
determining, by the one or more processors, a length of time for the data to travel along the length of each cable(see Rojas, pars. [0046-0047]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor. The controller 110 measures and determines the difference in time of arrivals of the different copies received by the different OFEs 210. Based on this time difference, the controller 110 decides to apply a correction to this difference in phase (or time of arrival/delay) among the different copies by selectively activating an individual delay element of a corresponding signal path. The signal copy from an OFE 210 with the longest cable may be detected the latest, and therefore a direct path may be selected without adding any additional delay. For the other signal paths, a corresponding switch may be controlled to select a corresponding delay element, which is inversely correlated to the delay in time of arrival (therefore also inversely proportional to a corresponding cable length). After the delay compensation, different copies of a same incoming signal will arrive at the summing amplifier substantially synchronized in phase, such as within a certain tolerance range. The number of delay elements 121 to be incorporated in the delay network 120 may depend on the possible length variation of the cables, a granularity requirement on the phase tuning of the system, and/or the tolerance of the system to phase variations, and see Rojas, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor, and see Rojas, par. [0052]: Based on the detection information provided by each signal detector 111, the controller 110 is configured to determine an individual delay for the individual signal path; in this case, determining differences in times of arrival of copies corresponds to determining a length of time for the data to travel along the length of each cable);
comparing, by the one or more processors, the lengths of time (see Rojas, pars. [0046-0047]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor. The controller 110 measures and determines the difference in time of arrivals of the different copies received by the different OFEs 210. Based on this time difference, the controller 110 decides to apply a correction to this difference in phase (or time of arrival/delay) among the different copies by selectively activating an individual delay element of a corresponding signal path. The signal copy from an OFE 210 with the longest cable may be detected the latest, and therefore a direct path may be selected without adding any additional delay. For the other signal paths, a corresponding switch may be controlled to select a corresponding delay element, which is inversely correlated to the delay in time of arrival (therefore also inversely proportional to a corresponding cable length). After the delay compensation, different copies of a same incoming signal will arrive at the summing amplifier substantially synchronized in phase, such as within a certain tolerance range. The number of delay elements 121 to be incorporated in the delay network 120 may depend on the possible length variation of the cables, a granularity requirement on the phase tuning of the system, and/or the tolerance of the system to phase variations, and see Rojas, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor, and see Rojas, par. [0052]: Based on the detection information provided by each signal detector 111, the controller 110 is configured to determine an individual delay for the individual signal path; in this case, detecting the signal copy associated with the longest cable corresponds to comparing the lengths of time); and
determining, by the one or more processors based on the comparison, the second delay for each of the cables (see Rojas, pars. [0046-0047]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor. The controller 110 measures and determines the difference in time of arrivals of the different copies received by the different OFEs 210. Based on this time difference, the controller 110 decides to apply a correction to this difference in phase (or time of arrival/delay) among the different copies by selectively activating an individual delay element of a corresponding signal path. The signal copy from an OFE 210 with the longest cable may be detected the latest, and therefore a direct path may be selected without adding any additional delay. For the other signal paths, a corresponding switch may be controlled to select a corresponding delay element, which is inversely correlated to the delay in time of arrival (therefore also inversely proportional to a corresponding cable length). After the delay compensation, different copies of a same incoming signal will arrive at the summing amplifier substantially synchronized in phase, such as within a certain tolerance range. The number of delay elements 121 to be incorporated in the delay network 120 may depend on the possible length variation of the cables, a granularity requirement on the phase tuning of the system, and/or the tolerance of the system to phase variations, and see Rojas, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor, and see Rojas, par. [0052]: Based on the detection information provided by each signal detector 111, the controller 110 is configured to determine an individual delay for the individual signal path; in this case, determining differences in times of arrival of copies corresponds to determining a length of time for the data to travel along the length of each cable. Detecting the signal copy associated with the longest cable corresponds to comparing the lengths of time. The longest cable is not delayed and the other cables are delayed, corresponding to determining the delay based on the comparison).
Regarding claims 8, 17, the combination of Rojas in view of Matthews teaches the method or device.
Rojas further teaches:
further comprising programming, by the one or more processors based on the second delay for the respective cable, the optics hardware for the respective cable (see Rojas, Fig. 5, par. [0053]: in step S503, selectively adding the individual delay to the individual signal path of each individual cable 211 to improve time-alignment among the plurality of signal paths, and see Rojas, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor, and see Rojas, par. [0052]: Based on the detection information provided by each signal detector 111, the controller 110 is configured to determine an individual delay for the individual signal path; in this case, adding the delay to each signal path of each cable corresponds to programming optics hardware based on the delay).
Regarding claims 9, 18, the combination of Rojas in view of Matthews teaches the method or device.
Rojas further teaches:
wherein the delay for each cable allows for the data transmitted via respective cables to arrive at respective destinations synchronously (see Rojas, par. [0026]: The controller derives individual delays for different signal paths to compensate the difference in arrival time. For example, the controller may decide to assign a largest delay value to an individual signal path corresponding to the OFE that first detects the incoming signal. The controller may decide to assign a shortest delay value or no delay to another individual signal path corresponding to the OFE that last detects the incoming signal. The goal is to make signal copies from different paths arrive at the baseband substantially synchronized after being compensated with individual delay values).
Claims 2-4, 11-13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Rojas in view of Dinu, and further in view of Chen, and further in view of Froc, as applied to claims 1, 6-10, and 15-19 above, and further in view of Lakshmikantha et al. (US 2017/0078176), hereinafter “Lakshmikantha”.
Regarding claims 2, 11, 20, the combination of Rojas in view of Matthews teaches the method or device or non-transitory storage medium.
However, the combination of Rojas in view of Matthews does not teach:
wherein the optics hardware comprises ingress and egress optics hardware.
Lakshmikantha, in the same field of endeavor, teaches:
wherein the optics hardware comprises ingress and egress optics hardware (see Lakshmikantha, Fig. 1A, par. [0045]: A centralized network delay measurement approach is proposed according to one embodiment. The approach is illustrated in FIG. 1A. Network elements 132 and 134 are the ingress and egress network elements of a traffic flow respectively, i.e., the traffic flow enters the network 100 through the network element 132 and exits the network 100 through the network element 134).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the optics hardware of the combination of Rojas in view of Matthews with the ingress and egress optics hardware of Lakshmikantha with a reasonable expectation of success. One of ordinary skill in the art would have been motivated to make this modification for the benefit of efficiently measuring delay of a traffic flow (see Lakshmikantha, par. [0007]).
Regarding claims 3, 12, the combination of Rojas in view of Matthews teaches the method or device.
The combination of Rojas in view of Matthews does not teach, but Lakshmikantha teaches:
wherein programming the optics hardware comprises programming at least one of the ingress optics hardware or the egress optics hardware (see Lakshmikantha, par. [0070]: The network controller may program the ingress and egress network elements to return the measurement packets back to the delay monitor).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the programming the optics hardware of the combination of Rojas in view of Matthews with the programming ingress and egress optics hardware of Lakshmikantha with a reasonable expectation of success. One of ordinary skill in the art would have been motivated to make this modification for the benefit of efficiently measuring delay of a traffic flow (see Lakshmikantha, par. [0007]).
Regarding claims 4, 13, the combination of Rojas in view of Matthews, and further in view of Lakshmikantha, teaches the method or device.
Rojas further teaches:
wherein when programming the optics hardware, the one or more processors are further configured to:
program, based on the delay for the respective cable, the optics hardware (see Rojas, Fig. 5, par. [0053]: in step S503, selectively adding the individual delay to the individual signal path of each individual cable 211 to improve time-alignment among the plurality of signal paths, and see Rojas, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor, and see Rojas, par. [0052]: Based on the detection information provided by each signal detector 111, the controller 110 is configured to determine an individual delay for the individual signal path; in this case, adding the delay to each signal path of each cable corresponds to programming optics hardware based on the delay); and
transmit, based on the delay for each of the plurality of cables, the data synchronously via the plurality of cables (see Rojas, par. [0026]: The controller derives individual delays for different signal paths to compensate the difference in arrival time. For example, the controller may decide to assign a largest delay value to an individual signal path corresponding to the OFE that first detects the incoming signal. The controller may decide to assign a shortest delay value or no delay to another individual signal path corresponding to the OFE that last detects the incoming signal. The goal is to make signal copies from different paths arrive at the baseband substantially synchronized after being compensated with individual delay values; in this case, changing delays to make signal copies arrive at the baseband synchronized corresponds to transmitting the data synchronously based on the delay).
The combination of Rojas in view of Matthews does not teach, but Lakshmikantha teaches:
programming the ingress optics hardware (see Lakshmikantha, par. [0070]: The network controller may program the ingress and egress network elements to return the measurement packets back to the delay monitor);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the programming the optics hardware of the combination of Rojas in view of Matthews with the programming ingress optics hardware of Lakshmikantha with a reasonable expectation of success. One of ordinary skill in the art would have been motivated to make this modification for the benefit of efficiently measuring delay of a traffic flow (see Lakshmikantha, par. [0007]).
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Rojas in view of Matthews, as applied to claims 1, 6-10, and 15-19 above, and further in view of Chen (US 11,165,721), hereinafter “Chen”.
Regarding claims 5, 14, the combination of Rojas in view of Matthews teaches the method or device.
Rojas further teaches a correlation between signal paths and cables (see Rojas, Fig. 5, par. [0053]: The method comprises the following steps of the time-alignment subsystem 100: detecting in step S501, on the individual cable 211, an individual copy of an incoming signal received by a corresponding OFE 210, and see Rojas, par. [0047]: The signal copy from an OFE 210 with the longest cable may be detected the latest, and therefore a direct path may be selected without adding any additional delay. For the other signal paths, a corresponding switch may be controlled to select a corresponding delay element, which is inversely correlated to the delay in time of arrival (therefore also inversely proportional to a corresponding cable length), and see Rojas, par. [0045]: The optical transceiver 200 comprises a common baseband module 220, an analog front end, AFE, module 230, a summing amplifier 240, a time-alignment subsystem 100, a plurality of cables 211, and a plurality of OFEs 210, and see Rojas, par. [0046]: The signal detectors 111 will detect different copies of the incoming signal on individual cables or signal paths connected to the more than one OFEs 210. The detection information will be provided to a controller 110, which may be a CPU, a programmable logic, or a micro-processor).
The combination of Rojas in view of Matthews does not teach, but Chen teaches:
further comprising copying, by a replication engine, the data to be transmitted via the plurality of cables (see Chen, Fig. 4, col. 14, lines 10-18: At step 416, the forwarding engine, e.g., the fabric and/or an ASIC in the fabric, replicates the multicast packet to generate copies of the multicast packet to be forwarded via the fabric to the egress pipeline of each identified output interface. For instance, if the forwarding engine and/or CPU determines an output interface includes an output port belonging to the multicast group, the packet replication is forwarded via the fabric to the output interface for egress processing; in this case, the forwarding engine corresponds to a replication engine), wherein a total number of copies made by the replication engine corresponds to the total number of cables in the plurality of cables minus one (see Chen, Figs. 1 and 4, col. 13, line 61-col. 14, line 1: At step 414, the forwarding engine, e.g., an application specific integrated circuit (ASIC) in the fabric, and looks up and identifies output interfaces with ports that belong to the multicast group. An output interface, such as interface 206A depicted in FIG. 2, may comprise many output ports, such as ports 216A. The forwarding engine and/or CPU identifies, from the multicast group map, which interfaces include ports that belong to the multicast group; in this case, copies may be made for each port (corresponding to a cable) except the uplink port (i.e. for all cables except one)).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the method or device of the combination of Rojas in view of Matthews with the copying by a replication engine of Chen with a reasonable expectation of success. One of ordinary skill in the art would have been motivated to make this modification for the benefit of minimizing memory and bandwidth use (see Chen, col. 16, lines 14-21).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Miller et al. (US 2022/0311510) teaches a method and apparatus are described that can be used to equalize the latency in fiber optic distribution links within data centers containing multiple pods.
Ponce Garcia et al. (US 2020/0089438) teaches devices and methods for calibrating communication lines using delays.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB J BALLOWE whose telephone number is (571)270-0410. The examiner can normally be reached MON-FRI 7:30-5.
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/C.J.B./Examiner, Art Unit 2419
/Nishant Divecha/Supervisory Patent Examiner, Art Unit 2419
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