DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 15, 2026 has been entered. Claims 1, 3, 4, 7-18, 68, and 116-119 are under consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pothukuchi et al. (US 11,217,573 B2, herein “Pothukuchi”).
Pothukuchi discloses a system (Fig. 3: 300) comprising:
a first optical input/output module comprising a first group of photonic integrated circuits arranged in a two-dimensional pattern (sixteen photonic engines 320 distributed on four sides of substrate 305 with an array of 2x2 on each side) comprising at least two rows and at least two columns of photonic integrated circuits (photonic engines 320, “device for converting optical signals and/or for converting electrical signals to optical signals” Col. 3, lines 40-47), the first group including at least three photonic integrated circuits (first group located on side next to reference number ‘301’), in which each of the at least some of the photonic integrated circuits is configured to receive first optical signals and generate first electrical signals based on the first optical signals (light from fibers at optical input/output 322; Col. 3, lines 40-51), each of at least some of the photonic integrated circuits is configured to receive second electrical signals (from switch circuit and switch die 314 or 210 in Fig. 2A) and generate second optical signals based on the second electrical signals (Col. 3, lines 40-51);
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at least one data processor (switch die 110 of Fig. 1B, and similar configurations in Fig. 2A: “die 210” and Fig. 3: die is below the integrated heat spreader 314; for brevity, examiner shall reference ‘314’ as the die in Fig. 3) that is configured to receive directly or through an interface circuit (Fig. 4A: from 402 to 410, Col. 6, lines 30-43), the first electrical signals generated by at least some of the photonic integrated circuits (from photonic engine 120 or 320), and to transmit directly or through the interface circuit, the second electrical signals (from 210 or 314) to at least some of the photonic integrated circuits (Col. 3, lines 40-51);
wherein the at least one data processor (210 or 314) has a first edge (quadrilateral);
wherein the first group of photonic integrated circuits (120 or 320) is arranged in the two-dimensional pattern on a common substrate (305) of the first optical input/output module and is located on one side of the at least one data processor (210 or 314) adjacent the first edge of the at least one data processor (Fig. 2A and 3, 2x2 array of 320 on side next to reference number ‘301’ adjacent 210 or 314).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 7-11, 13-18, 68, 116, and 119 are rejected under 35 U.S.C. 103 as being unpatentable over Doerr et al. (US 11,432,056 B1, herein “Doerr”) in view of Pothukuchi.
Regarding claim 1, Doerr discloses a system comprising:
a first optical input/output module (array of four tiles 220 plugged into socket 230 is considered the optical/input module, Fig. 2) comprising a first group of photonic integrated circuits (within each tile 220 has PIC 107, Fig. 1, the row of tiles 220 forms the first group), the first group including at least three photonic integrated circuits (four tiles 220 having PIC 107 on each tile), in which each of at least some of the photonic integrated circuits is configured to receive first optical signals and generate first electrical signals based on the first optical signals (from tile 220 to switch die 210, Col. 1, lines 50-60), each of at least some of the photonic integrated circuits is configured to receive second electrical signals and generate second optical signals based on the second electrical signals (from switch die 210 to tile 220, Col. 1, lines 50-60); and
at least one data processor (switch die 210) that is configured to receive, directly or through an interface circuit, the first electrical signals generated by at least some of the photonic integrated circuits (PIC 107/315 sends electrical signals to switch die 210 for switching, Col. 1, lines 50-60), and to transmit, directly or through the interface circuit, the second electrical signals to at least some of the photonic integrated circuits (switch die 210 sends the switched electrical signal to PIC 107/315 to be converted to optical signal, Col. 1, lines 50-60);
wherein the at least one data processor has a first edge (switch die 210 is a quadrilateral);
wherein the first group of photonic integrated circuits (PICs 107/315 on tiles 220/305) is disposed adjacent to the first edge of the at least one data processor (switch die 210).
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Doerr does not teach the first group of photonic integrated circuits having two-dimensional pattern is at least two rows and at least two columns, and wherein the first group of the photonic integrated circuits is arranged in two-dimensional pattern on a common substrate of the first optical input/output module.
Pothukuchi teaches an electronic package (Fig. 3: 300) with a data processor (switch die 110 of Fig. 1B, and similar configurations in Fig. 2A: “die 210” and Fig. 3: die is below the integrated heat spreader 314) with first optical input/output module comprising a first group (side adjacent to reference number ‘301’) of photonic integrated circuits arranged in a two-dimensional pattern comprising at least two rows and at least two columns of photonic integrated circuits (photonic engines 320 arranged in 2x2 array adjacent to data processor 314) located on one side of the at least one data processor (314/210) adjacent the first edge of the data processor.
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the edge coupled optical input/output module of Doerr with the optical input/output module architecture of Pothukuchi by expanding the one-dimensional array to a two-dimensional array. One would be motivated to employ the two-dimensional array input/output module of Pothukuchi to scale communication traffic for large data transmission application (Pothukuchi: BACKGROUND, and Col. 2, line 48 to Col. 3, line 2).
Claim 3. Doerr in view of Pothukuchi (herein “Doerr / Pothukuchi”) teach the invention of claim 1, Doerr further teaches the first optical input/output module (array of four tiles 220 plugged into socket 230) comprises: a plurality of optical connectors (four MPO 215, Fig. 2), in which each optical connector is associated with a photonic integrated circuit (each MPO 215 is associated with each tile 220, and each tile 220 has a PIC 107), the optical connector (215) is coupled to a first surface of the photonic integrated circuit (on tile 220); and
a plurality of sets of first electronic integrated circuits, in which each set of the first electronic integrated circuit is associated with one of the photonic integrated circuits, each set of the first electronic integrated circuits includes at least two electronic integrated circuits (transimpedance amplifier 335 and driver die3 20 on tile 220 with details shown in Fig. 3 on tile 305) that are coupled to the first surface (tile substrate) of the associated photonic integrated circuit (107/210/315).
Claim 4. Doerr / Pothukuchi teach the invention of claim 3, Doerr further teaches each set of the first electronic integrated circuits comprises two electronic integrated circuits (transimpedance amplifier 335 and driver die 320) that are positioned on opposite sides of the optical connector (transimpedance amplifier is to the left of MPO 215 and driver die is to the right of MPO 215) along a plane parallel to the first surface (tile substrate) of the associated photonic integrated circuit (107/210/315).
Claim 7. Doerr / Pothukuchi teach the invention of claim 3, Doerr further teaches each set of the first electronic integrated circuits comprises at least one of an electrical drive amplifier or a transimpedance amplifier (transimpedance amplifier 335).
Claim 8. Doerr / Pothukuchi teach the invention of claim 1, Doerr further teaches:
a substrate (Fig. 2: socket 230) in which a plurality of photonic integrated circuits (tiles 220/305) are mounted on the substrate (socket 230), and
a plurality of sets of second electronic integrated circuits mounted on the substrate each set of second electronic integrated circuits is associated with a photonic integrated circuit (each tile 105/210/305 has a PIC 107/210/315 and a set of electronic integrated circuits 335 and 332; Fig. 2 shows there are four tiles 220 mounted to substrate 230, Col. 2, line 63 to Col. 3, line 6) and electrically coupled to the photonic integrated circuit through one or more signal conductors and/or traces (PIC is wire-bonded and driver 320 and TIA are flip-chip bonded which require conductors Col. 3, lines 7-16, see also circuit diagram in Fig. 4).
Claim 9. Doerr / Pothukuchi teach the invention of claim 8, Doerr further teaches each set of the second electronic integrated circuits comprises three electronic integrated circuits (digital signal processor (DSP) 470, TIA 430, driver 425) that surround three sides of the photonic integrated circuit (PIC 415) along a plane parallel to the first surface of the substrate.
Claim 10. Doerr / Pothukuchi teach the invention of claim 8, and Doerr further teaches each set of second electronic integrated circuits comprises three electronic integrated circuits that surround three sides of the photonic integrated circuit along a plane parallel to a first surface of the substrate.
Doerr / Pothukuchi do not teach the second electronic integrated circuits comprises four electronic integrated circuits that surround four sides of the photonic integrated circuit along a plane parallel to a first surface of the substrate.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to vertically couple the optical connector perpendicular to the plane of the first surface of the photonic integrated circuit to free up an additional side, fourth side, for additional electronic integrated circuits to provide supporting functions to the PIC in high speed processing application. It has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (1977).
Claim 11. Doerr / Pothukuchi teach the invention of claim 8, and Doerr further teaches each set of second electronic integrated circuits comprises a serializers/deserializers module (Fig. 4: DSP 470 comprises SERDES module).
Claim 13. Doerr / Pothukuchi teach the invention of claim 1, and Doerr further teaches the data processor comprises at least one of a network switch (switch die 210).
Claims 14-15. Doerr / Pothukuchi teach the invention of claim 1, and Doerr further teaches a wafer-scale processing module (110 or 205, “a die may refer to a piece of wafer containing electronic and optical components”, Col. 2, lines 53-57 ) comprising a plurality of data processors (switch die 210), in which the first optical input/output module (array of four tiles 220 plugged into socket 230 is considered the optical/input module, Fig. 2) is configured to receive a plurality of first optical signals through at least some of a plurality of optical links (from fibers via MPOs 215), generate a plurality of first electrical signals based on the plurality of first optical signals (via PIC on tile 220), and transmit the plurality of first electrical signals to the data processors (switch die 210) directly or through the interface circuit (Col. 1, lines 50-61, and Col. 2, line 63 to Col. 3, line 6);
the plurality of data processors (switch die 210) are configured to generate a plurality of second electrical signals (from switch die 210) that are transmitted to the first optical input/output modules (to array of four tiles 220 plugged into socket 230) directly or through the interface circuit, the first optical input/output module is configured to generate a plurality of second optical signals based on the plurality of second electrical signals (Col. 1, lines 50-61), and output the plurality of optical signals through at least some of the plurality of optical inks (PIC to fibers via MPO 215).
Claims 16-18. Doerr / Pothukuchi teach the invention of claim 14, but Doerr / Pothukuchi do not teach the processing module comprises a two-dimensional arrangement of at least three rows and three columns of data processor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to increase the number of data processors from 2 processors (Doerr switch die 210) to 4 processors or 9 processors, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (1977). One motivation would be to increase the data processing computing capacity.
Regarding claim 68, Doerr discloses a system comprising:
a wafer-scale processing module (switch 110 in Fig. 1 or 205 in Fig. 2, “a die may refer to a piece of wafer containing electronic and optical components”, Col. 2, lines 53-57 ) comprising an array of data processors (2 switch die 210),
a first optical input/output module (array of four tiles 220 plugged into socket 230 is considered the optical/input module, Fig. 2) comprising a first group of photonic integrated circuits (within each tile 220 has PIC 107, Fig. 1, the row of tiles 220 forms the first group), the first group including at least three photonic integrated circuits (four tiles 220 having PIC 107 on each tile), in which each of at least some of the photonic integrated circuits is configured to receive first optical signals and generate first electrical signals based on the first optical signals (from tile 220 to switch die 210, Col. 1, lines 50-60), each of at least some of the photonic integrated circuits is configured to receive second electrical signals and generate second optical signals based on the second electrical signals (from switch die 210 to tile 220, Col. 1, lines 50-60); and
wherein at least some of the data processors (switch die 210) are configured to receive, directly or through an interface circuit, the first electrical signals generated by at least some of the photonic integrated circuits (PIC 107/315 sends electrical signals to switch die 210 for switching, Col. 1, lines 50-60), and at least some of the data processors are configured to transmit, directly or through the interface circuit, the second electrical signals to at least some of the photonic integrated circuits (switch die 210 sends the switched electrical signal to PIC 107/315 to be converted to optical signal, Col. 1, lines 50-60);
wherein the wafer-scale processing module has a first edge (switch die 210 is a quadrilateral);
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wherein the first group of photonic integrated circuits (PICs 107/315 on tiles 220/305) is disposed adjacent to the first edge of the wafer-scale processing module (switch die 210).
However, Doerr does not teach the first group of photonic integrated circuits having two-dimensional pattern is at least two rows and at least two columns, and wherein the first group of the photonic integrated circuits is arranged in two-dimensional pattern on a common substrate of the first optical input/output module.
Pothukuchi teaches an electronic package (Fig. 3: 300) with a data processor (switch die 110 of Fig. 1B, and similar configurations in Fig. 2A: “die 210” and Fig. 3: die is below the integrated heat spreader 314) with first optical input/output module comprising a first group (side adjacent to reference number ‘301’) of photonic integrated circuits arranged in a two-dimensional pattern comprising at least two rows and at least two columns of photonic integrated circuits (photonic engines 320 arranged in 2x2 array adjacent to data processor 314) located on one side of the at least one data processor (314/210) adjacent the first edge of the data processor.
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the edge coupled optical input/output module of Doerr with the optical input/output module architecture of Pothukuchi by expanding the one-dimensional array to a two-dimensional array. One would be motivated to employ the two-dimensional array input/output module of Pothukuchi to scale communication traffic for large data transmission application (Pothukuchi: BACKGROUND, and Col. 2, line 48 to Col. 3, line 2).
Claim 116. Doerr / Pothukuchi teach the invention of claim 1, Doerr further teaches:
a second optical input/output module (array of four tiles 220 plugged into socket 230 is considered the optical/input module, Fig. 2) comprising a second group of photonic integrated circuits (within each tile 220 has PIC 107, Fig. 1, the row of tiles 220 forms the first group), the second group including at least three photonic integrated circuits (four tiles 220 having PIC 107 on each tile), in which each of at least some of the photonic integrated circuits is configured to receive third optical signals and generate third electrical signals based on the third optical signals (from tile 220 to switch die 210, Col. 1, lines 50-60), each of at least some of the photonic integrated circuits is configured to receive fourth electrical signals and generate fourth optical signals based on the fourth electrical signals (from switch die 210 to tile 220, Col. 1, lines 50-60); and
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wherein the at least one data processor (switch die 210) is configured to receive, directly or through a second interface circuit, the third electrical signals generated by at least some of the photonic integrated circuits (PIC 107/315 sends electrical signals to switch die 210 for switching, Col. 1, lines 50-60) in the second group, and to transmit, directly or through the interface circuit, the fourth electrical signals to at least some of the photonic integrated circuits (switch die 210 sends the switched electrical signal to PIC 107/315 to be converted to optical signal, Col. 1, lines 50-60) in the second group;
wherein the at least one data processor has a second edge (switch die 210 is a quadrilateral);
wherein the second group of photonic integrated circuits (PICs 107/315 on tiles 220/305) is disposed adjacent to the second edge of the at least one data processor (switch die 10).
Doerr does not teach the first group of photonic integrated circuits having two-dimensional pattern is at least two rows and at least two columns, and wherein the first group of the photonic integrated circuits is arranged in two-dimensional pattern on a common substrate of the first optical input/output module.
Pothukuchi teaches an electronic package (Fig. 3: 300) with a data processor (switch die 110 of Fig. 1B, and similar configurations in Fig. 2A: “die 210” and Fig. 3: die is below the integrated heat spreader 314) with second optical input/output module comprising a first group of photonic integrated circuits arranged in a two-dimensional pattern comprising at least two rows and at least two columns of photonic integrated circuits (photonic engines 320 arranged in 2x2 array adjacent to data processor 314) located on the second side/edge of the at least one data processor (314/210) adjacent the first side/edge of the data processor, the second edge being different from the first edge.
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the edge coupled optical input/output module of Doerr with the optical input/output module architecture of Pothukuchi by expanding the one-dimensional array to a two-dimensional array. The expansion of the optical input/output module would apply to all four sides of the data process. One would be motivated to employ the two-dimensional array input/output module of Pothukuchi to scale communication traffic for large data transmission application (Pothukuchi: BACKGROUND, and Col. 2, line 48 to Col. 3, line 2).
Regarding claim 119, Doerr / Pothukuchi teach each photonic integrated circuit of the first group is configured both to receive respective first optical signals and generate respective first electrical signals (from tile 220 [with PIC 315] to switch die 210, Col. 1, lines 50-60), and to receive respective second electrical signals and generate respective second optical signals (from switch die 210 to tile 220, Col. 1, lines 50-60).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Doerr / Pothukuchi as applied to claim 1 above and further in view of Mack et al. (US 2014/0306131 A1, herein “Mack”).
Doerr / Pothukuchi teach the invention of claim 1, but Doerr / Pothukuchi do not teach the photonic integrated circuits comprises an array of grating couplers, a plurality of optical waveguides coupled to the array of grating coupler, and a plurality of photodetectors coupled to the plurality of optical waveguides.
Mack teaches a light source assembly supporting direct coupling to an integrated circuit wherein grating couplers (Fig. 1B: grating couplers 117A-117D) are coupled to optical input waveguides and optical output waveguides (Fig. 1B) and a plurality of photodetectors (111A-111D and 113A-113H, Para [0079]-[0080]) are coupled to the plurality of the optical waveguides (Fig. 1B and 2D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize grating couplers allow optical signals to be coupled vertically to a various elements such as fibers, lasers, photodetectors, and planar lightwave chips (Para [0111]) while maintaining a small form factor. Photodiodes (111A-111D) are provided to perform optical to electrical signal conversions and vice versa, furthermore, photodiodes (113A-113H) are provided to monitor the optical signals (Para [0093]). One would be motivated to integrate grating couplers and photodiodes for coupling optical signals to CMOS chip for converting optical signals to electrical signals and process the signal electronically.
Claims 117-118 are rejected under 35 U.S.C. 103 as being unpatentable over Doerr / Pothukuchi as applied to claim 116 above and further in view of Kamdar et al. (US 2023/0325576 A1, herein “Kamdar”)
Regarding claim 117, Doerr / Pothukuchi teach the invention of claim 116, but Doerr / Pothukuchi do not teach the wafer-scale processing module comprising at least two rows and two columns, or four rows and four columns, of data processors,
wherein the wafer-scale processing module comprises: a first edge and a second edge,
Kamdar teaches interconnections for modular die designs wherein chiplets (102[1] – 102[4]) and not limited to four (Para [0019]) are coupled together within a multi-die package to form a package having desired computing capabilities (Para [0003]). These chiplets are capable of handling data, instructions, commands, information, signals, buts, symbols, and chips that may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof (Para [0046]); thus, the examiner considers Kamdar’s modular chiplets design is a wafer-scale processing module. Kamdar teaches each chiplet is provided with a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that the signals may be routed appropriately. By using a look-up table for each chiplet for routing communication between chiplets based on the unique identifiers, the routing method configures ports to route communication between chiplets (para [0004]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the switch system of Doerr / Pothukuchi disclosed invention wherein the switch system can be modified with the technology of Kamdar’s modular chiplet design. The data processor of Doerr / Pothukuchi disclosed invention can be considered individual chiplet (Doerr: 2 chiplets 210) and they can scale up the computing capacity by expanding the chiplet to an array of 2x2 chiplets. The expanded 2x2 chiplets can be modified according to Kamdar’s teaching on the routing and communicating assigned to each chip with a unique identifier and using identifiers with designated ports as data in a look-up table, each chiplet in the 2x2 array of Doerr / Pothukuchi can be configured to route communication to the exact chiplet and corresponding port within the 2x2 array.
The modified invention of Doerr / Pothukuchi in view of Kamdar would result in a wafer-scale processing module having a 2x2 array of data processors, wherein the module comprises a first edge and a second edge, as recited in the claim. Moreover, the expanded 2x2 wafer-scale processing module is also quadrilateral - having four edges. Therefore, the four optical input/output modules of Doerr / Pothukuchi would be coupled to four edges of the single data processor in the same manner as the expanded 2x2 wafer-scale processing module.
One motivation for scaling up the wafer-scale processing module is to increase the computational capacity in large data transmission application.
Regarding claim 118, Doerr / Pothukuchi in view of Kamdar (herein “Doer / Pothukuchi / Kamdar”) teach the invention of claim 117, but the combined teaching do not explicitly teach a wafer-scale processing module comprising at least four rows and four columns of data processors. The combined teaching also do not teach the first group, and second group, of photonic integrated circuits, each group comprises at least four rows and four columns of photonic integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention expand the number of data processors and expand the number of photonic integrated circuits within each group arranged on the four edges of the wafer-scale processing module, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (1977). One motivation for scaling up the wafer-scale processing module and number of photonic integrated circuits per group is to increase the computational capacity in large data transmission application.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3, 4, 7-18, 68, and 116-118 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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