DETAILED ACTION
This office action is in response to applicant’s amendment filed on December 16, 2025. Claims 1-4, 7-18, 68, and 116-118 are under consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8, 13-15, and 68 are rejected under 35 U.S.C. 102(a)(1) and (2) as being anticipated by Bchir (US 2021/0272944 A1, herein “Bchir”).
Claim 1. Bchir discloses a system (Fig. 2) comprising:
a first optical input/output module (200) comprising a first group of photonic integrated circuits (inputs 120, outputs 130) arranged in a two-dimensional pattern (column of 1x4 group) comprising at least three photonic integrated circuits (4 PIC 120 and 4 PIC 130), in which each of at least some of the photonic integrated circuits (120) is configured to receive first optical signals (from optical fibers 106a) and generate first electrical signals (carry by wirebonds 204a) based on the first optical signals (from optical fibers 106a), each of at least some of the photonic integrated circuits (130) is configured to receive second electrical signals (from wirebonds 204b) and generate second optical signals (output to fibers 106b) based on the second electrical signals (from wirebonds 204b); and
at least one data processor (114) that is configured to receive, directly or through an interface circuit, the first electrical signals (wirebonds 204a) generated by at least some of the photonic integrated circuits (120), and to transmit, directly or through the interface circuit, the second electrical signals (wirebonds 204b) to at least some of the photonic integrated circuits (PICs 130). See Para [0023]-[0024];
wherein the at least one data processor (114) has a first edge (see right edge);
wherein the first group of photonic integrated circuits (PICs 130) is disposed in a vicinity of the first edge of the at least one data processor (114). Fig. 1B shows a simplified and detailed view of an integrated circuit (130) is disposed in a vicinity of the first edge of the at least one data processor (114). As the number of photonic integrated circuits are scaled up, as shown in Fig. 2, the number of photonic integrated circuits (plurality of PIC chips 130) are disposed in a vicinity of the first edge of the data processor increases.
Claim 8. The system of claim 1, in which the first optical input/output module comprises:
a substrate (302), in which the plurality of photonic integrated circuits (320/330) are mounted on the substrate, and
a plurality of sets of second electronic integrated circuits (analog driver circuitry 116), each set of second electronic integrated circuits is associated with a photonic integrated circuit (330)a and electrically coupled to the photonic integrated circuit through one or more signal conductors and/or traces (wirebonds 304c).
Claim 13. Bchir discloses the semiconductor die 110 includes integrated circuitry 114 is used in several applications such as memory circuitry (Para [0021]).
Claim 14. Bchir discloses the invention of claim 1 comprising a wafer-scale processing module (Para [0018]) comprising a plurality of data processors, in which the first optical input/output module (Fig. 2) is configured to receive a plurality of first optical signals through at least some of a plurality of optical links (optical fibers 106a), generate a plurality of first electrical signals (from PICs 120 electrical signals are sent through wirebonds 204a) based on the plurality of first optical signals (from optical fibers 106a), and transmit the plurality of first electrical signals (wirebonds 204a) to the data processors (114 and 116) directly or through the interface circuit.
Claim 15. Bchir discloses the system of claim 14 in which plurality of data processors (114, 116) are configured to generate a plurality of second electrical signals that are transmitted (via wirebonds 204b) to the first optical output modules, the fist optical output module is configured to generate a plurality of second optical signals (via 2nd PICs 130) based on the second electrical signals (via wirebonds 204b), and output the plurality of optical signals through at least some of the plurality of optical links (optical fibers 106b).
Claim 68. Bchir discloses a system comprising:
a wafer-scale processing module (Para [0018]) comprising an array of data processors (Fig. 3 shows an array of two data processors 114, 116),
a first optical input/output module comprising a plurality of photonic integrated circuits (PICs 120, 130) arranged in a two-dimensional pattern (4x2) comprising at least three photonic integrated circuits (8 PICs), in which each of at least some of the photonic integrated circuits (120) are configured to receive first optical signals (from optical fibers 106a) and generate first electrical signals (sent via wirebonds 204a) based on the first optical signals, each of at least some of the photonic integrated circuits (130)is configured to receive second optical signals based on the second electrical signals (from wirebonds 204b); and
wherein at least some of the data processors (114, 116) are configured to receive, directly or through an interface circuit, the first electrical signals generated by at least some of the photonic integrated circuits (120), and at least some of the data processors are configured to transmit (114, 116), directly or through the interface circuit, the second electrical signals (via wirebonds 204b) to at least some of the photonic integrated circuits (PICs 130);
wherein the wafer-scale processing module has a first edge (see right edge);
wherein the plurality of photonic integrated circuits arranged in the two-dimensional pattern comprising at least three photonic integrated circuits (PICs 130) are disposed near the first edge of the wafer-scale processing module.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Bchir.
Bchir teaches the invention of claim 1, however, Bchir does not explicitly teach the two-dimensional array comprising at least two rows and at least two columns of photonic integrated circuits are disposed in the vicinity of the first edge of the at least one data processor.
Bchir teaches package (100) can include multiple ones of the PIC chips (120, 130). In some embodiments, the light source (136 in Fig. 2) can be a separate chip (Para (0022]-[0023]). In this embodiment it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to arrange the plurality of PIC chips (134, 136) in an array such as a 2x2 array to efficiently utilizing the small real estate in the package (100). One would be motivated to separate chip (134) from chip (136) to independently control integrated circuit of (134) and for example, the light source of chip (136) (Para [0022]).
Claims 3, 4, 7, 9-11, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Bchir in view of Doerr et al. (US 11,432,056 B1, herein “Doerr”).
Regarding claims 3, 9, and 11, Bchir discloses the invention of claims 1 and 8, but Bchir does not teach a plurality of optical connectors as recited in claim 3.
Doerr discloses an input/output optical module with co-packaged optics (CPO) tiles (Fig. 2). The module comprises a plurality of optical connectors (MPO connectors on four edges of the substrate), in which each optical connector is associated with a photonic integrated circuit (PIC 415 shown in Fig. 4), the optical connector is coupled to a first surface of the photonic integrated circuit, and
a plurality of sets of first electronic integrated circuits, in which each set of the first electronic integrated circuit (digital signal process DSP 470) is associated with one of the photonic integrated circuits, each set of the first electronic integrated circuits includes at least two electronic integrated circuits (serializers and deserializers – “SERDES”) that are coupled to the first surface of the associated photonic integrated circuit.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the electronic integrated circuits provided immediately next to the PIC is to provide supporting functions to the optical input/output data signals. One would be motivated to provide a SERDES immediately next to the PIC to convert parallel data into a serial stream for high speed transmission and then converts it back to parallel data at the receiving end for data processing.
Claims 4 and 7. Bchir in view of Doerr (herein “Bchir/Doerr”) further teach each set of first electronic integrated circuits comprises two electronic integrated circuits that are positioned on opposite sides (Doerr: Fig. 4 shows Transimpedance amplifier [TIA] 420/430) on opposite sides of the optical connector at 410) of the optical connector along a plane parallel to the first surface of the associated photonic integrated circuit.
Claim 10. Bchir/Doerr teach each set of first electronic integrated circuits comprises three electronic integrated circuits that surround four sides of the optical connector along a plane parallel to the first surface of the photonic integrated circuit, as recited in claim 3 and 8.
Bchir/Doerr do not teach four electronic integrated circuits that surrounds four sides of the optical connector.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to vertically couple the optical connector perpendicular to the plane of the first surface of the photonic integrated circuit to free up an additional side, fourth side, for additional electronic integrated circuits to provide supporting functions to the PIC in high speed processing application. It has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (1977).
Regarding claims 16-18, Bchir discloses the invention of claim 14, but Bchir does not disclose the module comprises a at least three rows and at least three columns of data processors.
In an different embodiment shown in Fig. 4 Bchir discloses a memory device wherein eight memory chiplets (400) are disposed on the package substrate, each memory chiplet comprises of the optical input/output module as shown in the embodiments of Figs. 1-3. The package substrate is provided with input (406b) and output (406a) optical links at connectors (458). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate an array of data processors, at least three rows and at least three columns of data processors, for processing densely integrated modules, since it has been held that mere duplication of essential working parts of a device involves only routine skill in the art St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (1977).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Bchir in view of Mack et al. (US 2014/0306131 A1, herein “Mack”).
Bchir discloses the invention of claim 1, but Bchir does not disclose the photonic integrated circuits comprises an array of grating couplers, a plurality of optical waveguides coupled to the array of grating coupler, and a plurality of photodetectors coupled to the plurality of optical waveguides.
Mack teaches a light source assembly supporting direct coupling to an integrated circuit wherein grating couplers (117A-117D) are coupled to optical input waveguides and optical output waveguides (Fig. 1B) and a plurality of photodetectors (111A-111D and 113A-113H) are coupled to the plurality of the optical waveguides (Fig. 1B and 2D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize grating couplers allow optical signals to be coupled vertically to a various elements such as fibers, lasers, photodetectors, and planar lightwave chips (Para [0111]) while maintaining a small form factor. Furthermore photodiodes (111A-111D) are provided to perform optical to electrical signal conversions and vice versa and photodiodes (113A-113H) are provided to monitor the optical signals (Para [0093]). One would be motivated to integrate grating couplers and photodiodes for processing optical signals and converting optical signals to electrical signals and vice versa.
Claims 116-118 are rejected under 35 U.S.C. 103 as being unpatentable over Bchir in view of Kamdar (US 2023/0325576 A1, herein “Kamdar”).
Claim 116. Bchir discloses the invention of claim 1, however Bchir does not teach:
a second optical input/output module comprising a second group of photonic integrated circuits arranged in a two dimensional pattern comprising at least three photonic integrated circuits, in which each of at least some of the photonic integrated circuits is configured to receive third optical signals and generate third electrical signals based on the third optical signals, each of at least some of the photonic integrated circuits is configured to receive fourth electrical signals and generate fourth optical signals based on the fourth electrical signals;
wherein the at least one data processor is configured to receive, directly or through a second interface circuit, the third electrical signals generated by at least some of the photonic integrated circuits in the second group, and to transmit, directly or through the interface circuit, the fourth electrical signals to at least some of the photonic integrated circuits in the second group;
wherein the at least one data processor has a second edge;
wherein the second group of photonic integrated circuits arranged in the two-dimensional pattern is disposed in a vicinity of the second edge of the at least one data processor, the second edge being different from the first edge.
Kamdar teaches interconnections for modular die designs wherein chiplets (102[1] – 102[4]) and not limited to four (Para [0019]) are coupled together within a multi-die package to form a package having desired computing capabilities (Para [0003]). These chiplets are capable of handling data, instructions, commands, information, signals, buts, symbols, and chips that may be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields or particles, or any combination thereof (Para [0046]); thus the examiner considers Kamdar’s modular chiplets design includes photonic integrated circuit (PIC). Kamdar teaches each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that the signals may be routed appropriately. By using a look-up table for each chiplet for routing communication between chiplets based on the unique identifiers, the routing method configures ports to route communication between chiplets (para [0004]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the system of Bchir’s invention wherein the optical input/output module can be modified with the technology of Kamdar’s invention. The input/output module of Bchir can be considered individual chiplet, as they are functional silicon dies designed to be combined. Bchir can scale up the input/output capacity by duplicating the input/output module as shown, for example in Fig. 2 and modify the routing and communicating methods as taught by Kamdar. Each module of Bchir can be designated with a unique identifier, and using identifiers with designated ports as data in a look-up table, each chiplet of Bchir can be configured to route communication to the exact chiplet and port. One motivation for scaling up the input/output capacity of Bchir’s modules is to increase the computational requirements and demand.
Claim 117-118. Bchir in view of Kamdar (herein “Bchir / Kamdar”) teach the invention of claim 116 and further teach the data processor comprises a wafer-scale processing module (Bchir: Para [0018]) comprises a first edge and a second edge (see Fig. 2).
Bchir / Kamdar do not explicitly teach the wafer-scale processing module comprising at least two rows and two columns, or four rows and four columns, of data processors, wherein the first group of photonic integrated circuits comprises at least two rows and two columns, or four rows and four columns, of photonic integrated circuits, the first group of photonic integrated circuits form a first edge interface module disposed near the first edge of the wafer-scale processing module; and wherein the second group of photonic integrated circuits comprises at least two rows and two columns of photonic integrated circuits, the second group of photonic integrated circuits form a second edge interface module disposed near the second edge of the wafer-scale processing module.
Bchir teaches package (100) can include multiple ones of the PIC chips (120, 130). In some embodiments, the light source (136 in Fig. 2) can be a separate chip (Para [0022]-[0023]). In this embodiment it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to arrange the plurality of PIC chips (134, 136) in an array such as a 2x2 or 4x4 array to efficiently utilizing the small real estate in the package (100). One would be motivated to separate chip (134) from chip (136) to independently control integrated circuit of (134) and for example, the light source of chip (136) (Para [0022]).
Furthermore, duplicating the first optical input/output module such that the system computational capacity can increase. It has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (1977).
Response to Arguments
Applicant's arguments filed December 16, 2025 have been fully considered but they are not persuasive.
Applicant argues Bchir does not teach the first group of photonic integrated circuits arranged in a two-dimensional patter in a vicinity of the first edge of the at least one data processor, as amended in claim 1 and claim 68.
The examiner respectfully disagrees. The first group of photonic integrated circuits disposed in a vicinity of the first edge of the data processor is an array of 1x4. For clarity, a 1x4 array has a first dimension of 1 chip unit width and 4 chip units long. Therefore, the argument is not persuasive.
The amendment to claim 2 and additional new claims 116-118 are address with new grounds of rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIN D CHIEM/
Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874