DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/29/2026 has been entered.
Status of the Claims
Claims 1-10, 21, 23-29, and 31-32 are pending in the application and are currently being examined. Claims 1, 3, 9, 21, 27, and 28 have been amended.
Response to Arguments
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. After reconsidering the references, Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections below.
Regarding the argument against the rejection of claim 1, Examiner agrees that Iayer does not teach the different concentrations of nitrogen in the silicon oxynitride layers, and Iayer is drawn specifically to silicon nitride layers, which are structurally different. However, after further search and consideration, a new reference (Yamazaki et al., see rejection to follow) discusses the first silicon oxynitride layer having a first nitrogen concentration and a second silicon oxynitride layer having a second higher nitrogen concentration.
Regarding the argument against claim 21, Examiner agrees Kwon is silent on the newly amended limitation ”a middle portion with a substantially linear surface profile along a horizontal plane; and an end portion extending from the middle portion to the first spacer and having a surface profile with a decreasing slope from the middle portion to the first spacer.” However, Examiner has brought in additional references to remedy the deficiencies of Kwon, as noted in the rejection to follow.
Regarding the argument against independent claim 27, Applicant argues that the cited prior art fails to teach “the second nitride layer extends laterally between the first and second spacers and sidewalls of the second nitride layer are in contact with the sidewalls of the first and second spacers”. Examiner respectfully disagrees. While Applicant is correct that Examiner erroneously did not describe the cited prior art as teaching the limitation, Examiner disagrees that the limitation is not taught by the prior art. Examiner would agree that the prior art as cited fails to disclose direct contact, Examiner notes that the claim as written does not necessitate direct physical contact. Under BRI, contact can include direct or indirect. The second nitride layer is in thermal contact with the sidewalls of the first and second spacers. As such, the prior art as cited teaches the limitation as written, and is properly clarified in the rejection to follow.
As the arguments against the rejections of all dependent claims rely upon the arguments against the rejections of the independent claims, they will not be repeated here. Please see rejection to follow.
Regarding the arguments directed to the rejection under 35 U.S.C. 112(a), the proposed amendments with respect to the specification and drawings are sufficient. As such, the rejection of claims under 35 U.S.C. 112(a) is hereby withdrawn.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3, 8-9, 21, 23-25, 27-28, and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2018/0301564 A1, hereafter Kwon) in view of Yamazaki et al. (US 2015/0102341 A1, hereafter Yamazaki).
Regarding claim 1, Fig. 15A of Kwon teaches a semiconductor device, comprising:
a substrate (100, [0029]);
a fin base (AP, [0029]) disposed on the substrate (100);
nanostructured channel regions (CS, [0031]) disposed on a first portion (R1, [0029]) of the fin base (AP);
a gate structure (GE and GD, [0033]) surrounding the nanostructured channel regions (CS);
a source/drain (S/D) region (SD, [0036]) disposed on a second portion (R2, [0029]) of the fin base (AP);
an air spacer (AG, [0038]) disposed between the S/D region (SD) and the fin base (AP); and
a dielectric layer (growth prevention regions, 148a, [0075]) disposed between the air spacer (AG) and the fin base (AP).
Kwon does not explicitly teach wherein the dielectric layer comprises a first nitride layer comprising a first nitrogen concentration and disposed in the fin base; and a second nitride layer comprising a second nitrogen concentration higher than the first nitrogen concentration and disposed between the air spacer and the first nitride layer.
However, Kwon teaches the dielectric layer 148a can be a multilayer structure, which would include a dual-layered structure comprising a first silicon nitride as the lower layer (in the fin base) and a second silicon nitride as the upper layer (located between the air spacer and the first nitride layer [0075]. This dielectric is a growth prevention region in Kwon. As it is made of a dielectric material, this growth prevention region has the added benefit of isolating the source/drain regions from the substrate.
Yamazaki teaches a silicon oxynitride stack for insulation in Fig. 4A in which a first silicon oxynitride layer (of a lower nitrogen concentration as an oxide layer is described as having higher oxygen than nitrogen [0116]) (25, [0230]) is covered by a second silicon nitride layer (of a lower nitrogen concentration as an nitride layer is described as having higher oxygen than nitrogen [0116]) (27, [0234]). The reason the higher nitrogen concentration is placed on top is to block oxygen, hydrogen, water, and prevent outward diffusion of oxygen [0233]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the growth prevention regions of Kwon to be two layered with silicon oxynitride layers of differing nitrogen concentrations for blocking diffusion of oxygen in the device as taught by Yamazaki [0233].
Regarding claim 3, Kwon in view of Yamazaki teach the semiconductor device of claim 1, wherein:
the first oxynitride layer (lower layer of 148a of claim 1 comprising silicon oxynitride, [0075], of lower nitrogen content taught by Yamazaki’s layer 25 [0230]) comprises a silicon oxynitride layer with the first nitrogen concentration; and
the second oxynitride layer (upper layer of 148a of claim 1 comprising silicon nitride, [0075], of higher nitrogen content taught by Yamazaki’s layer 27 [0234]) comprises a silicon oxynitride layer with the second nitrogen concentration.
Regarding claim 8, Kwon in view of Yamazaki teach the semiconductor device of claim 1. Fig. 15A of Kwon further teaches:
a first spacer (146, [0039], see annotated Fig. 15A) disposed between a first portion of the gate structure (GE and GD, [0033], see annotated Fig. 15A) and the S/D region (SD, [0036]); and
a second spacer (146, see annotated Fig. 15A) disposed directly on the fin base (AP, [0029]) and between a second portion of the gate structure (see annotated Fig. 15A) and the air spacer (AG, [0038]).
PNG
media_image1.png
465
462
media_image1.png
Greyscale
Regarding claim 9, Kwon in view of Yamazaki teach the semiconductor device of claim 1. Fig. 15A of Kwon further teaches a spacer (second spacer in annotated Fig. 15A) disposed directly on the fin base (AP, [0029]) and between the gate structure (GE and GD, [0033], second portion of gate structure in annotated Fig. 15A) and the dielectric layer (growth prevention regions, 148a, [0075]) (while not in the same vertical layer, the spacer is laterally between the second portion of the gate structure and the dielectric layer), wherein the spacer (146) and the dielectric layer (148a) comprise a same material (146 may include s silicon oxynitride [0041]).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Yamazaki, and further in view of Reznicek (US 10,170,638 B1).
Regarding claim 2, Kwon in view of Yamazaki teach the semiconductor of claim 1. Kwon in view of Yamazaki fail to teach a first portion of the dielectric layer extends into the fin base and a second portion of the dielectric layer extends above a top surface of the fin base.
However, Reznicek teaches in Fig. 8 a dual spacer structure (20L, 22, column 8, lines 39-20) in which a first portion of the dielectric layer extends into the fin base (see annotated Fig. 8) and a second portion of the dielectric layer extends above a top surface of the fin base (see annotated Fig. 8). The dielectric being above the fin base allows the dielectric to connect to the inner gate spacers (20S, column 8 line 24) to create better insulation between the source drain region and the substrate (column 11 lines 33-37). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric layer of Kwon in view of Yamazaki to have a portion extend above the fin base to provide better insulation as taught by Reznicek.
PNG
media_image2.png
495
665
media_image2.png
Greyscale
Claim(s) 4-6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Yamazaki as applied to claim 1 above, and further in view of Jung et al. (US 2020/0365692 A1, hereafter Jung).
Regarding claim 4, Kwon in view of Yamazaki teach the semiconductor device of claim 1. Kwon in view of Yamazaki fail to disclose the S/D region comprising S/D sub-regions disposed on sidewalls of the nanostructured channel regions and non-overlapping with each other.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions, with the subregions not overlapping with one another. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon in view of Yamazaki to include the layered S/D regions of Jung in order to minimize performance deterioration of the device [0052].
Regarding claim 5, Kwon in view of Yamazaki teach the semiconductor device of claim 1. Kwon in view of Yamazaki fail to disclose a doped S/D sub-region extending along a sidewall of the S/D region; and
undoped S/D sub-regions disposed on sidewalls of the nanostructured channel regions, wherein the undoped S/D sub-regions are separated from each other by the doped S/D sub-region.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions, with the subregions not overlapping with one another. Similarly, Jung indicates that element 230 may include n-type impurities, one of ordinary skill in the art would know that the impurities are not necessary, as that would still leave 240 with a higher concentration than 230. This means that the undoped subregions 230 are separated from one another by the doped subregion 240. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon in view of Yamazaki to include the layered S/D regions of Jung in order to minimize performance deterioration of the device [0052].
Regarding claim 6, Kwon in view of Yamazaki teach the semiconductor device of claim 1. Kwon in view of Yamazaki fail to disclose a first S/D sub-region disposed directly on the air spacer; and
second and third S/D sub-regions disposed directly on the air spacer and along opposite sidewalls of the first S/D sub-region.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (here the second and third sub-regions, 230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions, with the subregions not overlapping with one another. Jung also discloses another subregion (here the first sub-region, 240, [0038]). While Jung does not show the second and third subregions being disposed on the air spacer, they are being placed in a similar position in Kwon in view of Yamazaki, making them placed on the air gap of Kwon (AG, [0038] of Kwon, see annotated Fig. 15A of Kwon). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon in view of Yamazaki to include the layered S/D regions of Jung in order to minimize performance deterioration of the device [0052].
PNG
media_image3.png
456
365
media_image3.png
Greyscale
Regarding claim 10, Kwon in view of Yamazaki teach the semiconductor device of claim 1. Kwon also discloses in Fig. 2A spacers (146, [0039]) disposed between the gate structure (GE and GD, [0033]) and the S/D region (SD,[0036]), Kwon in view of Yamazaki fail to disclose the S/D region comprising:
first S/D sub-regions disposed on sidewalls of the nanostructured channel regions, and
a second S/D sub-region comprising first portions disposed on the first S/D sub-regions and second portions disposed on sidewalls of the spacers.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions, with the subregions not overlapping with one another. Jung also discloses another subregion (240, [0038]), which includes first portions (see annotated Fig. 3) disposed on the first S/D sub-regions (230) and second portions disposed on sidewalls of the spacers (see annotated Fig. 3). These epitaxial structures (230) structures and included to minimize performance deterioration of the device [0052]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon in view of Yamazaki to include the layered S/D regions of Jung.
PNG
media_image4.png
608
472
media_image4.png
Greyscale
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yamazaki as applied to claim 1 above, in view of Jung and further in view of Bomberger et al. (US 2020/0303502 A1, hereafter Bomberger).
Regarding claim 7, Kwon in view of Yamazaki teach the semiconductor device of claim 1. Kwon in view of Yamazaki fail to disclose the S/D region comprising:
first S/D sub-regions with triangular-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions;
a pair of second S/D sub-regions disposed on the first S/D sub-regions, wherein sidewalls of the pair of second S/D sub-regions facing each other comprise zig-zag-shaped cross-sectional profiles; and
a third S/D sub-region disposed between the pair of second S/D sub-regions.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions. These epitaxial structures (230) structures are less doped than the surrounding 240 to minimize performance deterioration [0052]. While Jung teaches these regions 230 to be candle shaped, one of ordinary skill in the art would know that altering the shape of these regions to be triangles is merely a matter of choice, as evidenced by MPEP 2144.05:
“In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).” (MPEP 2144.04).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon to include the layered S/D regions of Jung and further modified to be a triangular shape depending on design choice.
Bomberger teaches a device similar to Kwon in view of Yamazaki and in further view of Jung. In Fig. 3H, Bomberger depicts a pair of second S/D sub-regions (nubs, 332, [0049]), wherein sidewalls of the pair of second S/D sub-regions facing each other comprise zig-zag-shaped cross-sectional profiles (while not sharp, nubs 332 seem to make a general zig-zag shape); and
a third S/D sub-region (conductive contact structure, 344, [0053]) disposed between the pair of second S/D sub-regions (332). These subregions are created within the S/D region to decrease contact area of the source or drain while having a low resistance [0024-25]
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of invention of Kwon in view of Yamazaki with the subregions taught by Jung, as well as the subregions taught by Bomberger.
Claim(s) 21 and 23-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Iyer et al. (US 2007/0111538 A1, hereafter Iyer) and in further view of Lee (US 2016/0163788 A1).
Regarding claim 21, Fig. 15A of Kwon teaches a semiconductor device, comprising:
a substrate (100, [0029]);
a fin base (AP, [0029]) disposed on the substrate (100);
nanostructured channel regions (CS, [0031]) disposed on the fin base (AP);
a gate structure (GE and GD, [0033]) surrounding the nanostructured channel regions (CS);
a source/drain (S/D) region (SD, [0036]) disposed on the fin base (AP);
an air spacer (AG, [0038]) with a curved cross-sectional profile disposed between the S/D region (SD) and the fin base (AP); and
first and second spacers (146, [0039], see annotated Fig. 15A) disposed on opposite ends of the air spacer (AG).
Kwon does not explicitly teach a first dielectric layer comprising a first nitrogen concentration and disposed between the air spacer and the fin base; and a second dielectric layer, disposed between the air spacer and the first dielectric layer, comprising a second nitrogen concentration higher than the first nitrogen concentration and disposed between the air spacer and the first dielectric layer.
However, Kwon teaches the dielectric layer 148a can be a multilayer structure, which would include a dual-layered structure comprising a first silicon nitride as the lower layer (in the fin base) and a second silicon nitride as the upper layer (located between the air spacer and the first nitride layer [0075]. This dielectric is a growth prevention region in Kwon. As it is made of a dielectric material, this growth prevention region has the added benefit of isolating the source/drain regions from the substrate.
Iyer teaches a similar silicon nitride stack for isolation in Fig. 2F in which a first silicon nitride layer (of a lower nitrogen concentration due to processing parameters in [0034]) (206, [0026]) is covered by a second silicon nitride layer (of a higher nitrogen concentration due to processing parameters in [0038]) (208, [0026]). The reason the higher nitrogen concentration is placed on top is to prevent oxidation during other processing steps [0037] while also providing proper isolation to allow for higher transistor density [0004]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the growth prevention regions of Kwon to be two layered with silicon nitride layers of differing nitrogen concentrations for higher transistor density as taught by Iyer [0004].
Kwon in view of Iyer fails to teach the second dielectric layer having a middle portion with a substantially linear surface profile along a horizontal plane. While Kwon in view of Iyer teach the second dielectric layer to comprise a continuous curve, one of ordinary skill in the art would know that altering the shape of the second dielectric to have a middle portion with a substantially linear surface profile along a horizontal plane is merely a matter of choice, as evidenced by MPEP 2144.04:
“In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).” (MPEP 2144.04).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon in view of Iyer to include a middle portion with a substantially linear surface profile along a horizontal plane depending on design choice.
Kwon in view of Iyer of fail to teach the second dielectric layer with an end portion extending from the middle portion to the first spacer and having a surface profile with a decreasing slope from the middle portion to the first spacer. Kwon in view of Iyer teach the end portions having an increasing slope, or being concave. However, Lee teaches a similar spacer structure in which the shape of the dielectric (buffer layer, 45, [0035]) can either be concave or convex [0035]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer end portions of Kwon in view of Iyer to have a decreasing slope from the middle portion to the first spacer, as Lee teaches the slopes to be obvious variants of one another.
PNG
media_image5.png
683
533
media_image5.png
Greyscale
Regarding claim 23, Kwon in view of Iyer in view of Lee teach the semiconductor device of claim 21, wherein:
the first dielectric layer (lower layer of 148a of claim 1 comprising silicon nitride, [0075], of lower nitrogen content taught by Iyer’s layer 206 [0034]) comprises a silicon nitride layer with the first nitrogen concentration; and
the second dielectric layer (upper layer of 148a of claim 1 comprising silicon nitride, [0075], of higher nitrogen content taught by Iyer’s layer 208 [0038]) comprises a silicon nitride layer with the second nitrogen concentration.
Regarding claim 24, Fig. 15A of Kwon in view of Iyer in view of Lee teaches the semiconductor device of claim 21, further comprising a gate spacer (146, [0039])disposed along a sidewall of one of the nanostructured channel regions (CS, [0031]), wherein the gate spacer (146) is in contact with the air spacer (AG, [0038]).
Regarding claim 25, Fig. 15A of Kwon in view of Iyer in view of Lee teaches the semiconductor device of claim 21, further comprising:
a first spacer (146, [0039], see annotated Fig. 15A) disposed between a first portion of the gate structure (GE and GD, [0033], see annotated Fig. 15A) and the S/D region (SD, [0036]); and
a second spacer (146, [0039], see annotated Fig. 15A) disposed directly on the fin base (AP, [0029]) and between a second portion of the gate structure (GE and GD, see annotated Fig. 15A)and the air spacer (AG, [0038]).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Iyer in view of Lee, and further in view of Jung.
Regarding claim 26, Kwon in view of Iyer in view of Lee teach the semiconductor device of claim 21. Kwon in view of Iyer fail to disclose the S/D region comprising S/D sub-regions with triangular-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions. These epitaxial structures (230) structures are less doped than the surrounding 240 to minimize performance deterioration [0052]. While Jung teaches these regions 230 to be candle shaped, one of ordinary skill in the art would know that altering the shape of these regions to be triangles is merely a matter of choice, as evidenced by MPEP 2144.05:
“In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).” (MPEP 2144.04).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon to include the layered S/D regions of Jung and further modified to be a triangular shape depending on design choice.
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Iyer.
Regarding claim 27, Fig. 15A of Kwon teaches a semiconductor device, comprising:
a substrate (100, [0029]);
a fin base (AP, [0029]) disposed on the substrate (100);
first and second nanostructured channel regions (122, see annotated Fig. 15A, [0031]) disposed on the fin base (AP);
first and second spacers (146, [0039], see annotated Fig. 15A) disposed on and in contact with a top surface of the fin base (AP) and bottom surfaces of first and second gate structures (GE and GD, [0033], see annotated Fig. 15A), respectively;
an air spacer (AG, [0038]) extending laterally between the first and second spacers (146);
a source/drain (S/D) region (SD, [0036]) disposed on the air spacer (AG); and
the first and second gate structures (GE and GD) surround the first and second nanostructured channel regions (122), respectively.
Kwon fails to explicitly disclose a first nitride layer comprising a first nitrogen concentration and disposed between the air spacer and the fin base;
a second nitride layer comprising a second nitrogen concentration higher than the first nitrogen concentration and disposed between the air spacer and the first nitride layer, wherein the second nitride layer extends laterally between the first and second spacers and sidewalls of the second nitride layer are in contact with the sidewalls of the first and second spacers (while not in direct contact, the first and second spacers are in thermal contact with the with the sidewalls of the second nitride layer).
However, Kwon teaches the dielectric layer 148a can be a multilayer structure, which would include a dual-layered structure comprising a first silicon nitride as the lower layer (in the fin base) and a second silicon nitride as the upper layer (located between the air spacer and the first nitride layer [0075]. This dielectric is a growth prevention region in Kwon. As it is made of a dielectric material, this growth prevention region has the added benefit of isolating the source/drain regions from the substrate.
Iyer teaches a similar silicon nitride stack for isolation in Fig. 2F in which a first silicon nitride layer (of a lower nitrogen concentration due to processing parameters in [0034]) (206, [0026]) is covered by a second silicon nitride layer (of a higher nitrogen concentration due to processing parameters in [0038]) (208, [0026]). The reason the higher nitrogen concentration is placed on top is to prevent oxidation during other processing steps [0037] while also providing proper isolation to allow for higher transistor density [0004]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the growth prevention regions of Kwon to be two layered with silicon nitride layers of differing nitrogen concentrations for higher transistor density as taught by Iyer [0004].
Regarding claim 31, Kwon in view of Iyer teach the semiconductor device of claim 27, wherein the first nitride layer (lower layer of 148a of claim 1 comprising silicon nitride, [0075], of lower nitrogen content taught by Iyer’s layer 206 [0034]) comprises a first dielectric constant; and
the second nitride layer (upper layer of 148a of claim 1 comprising silicon nitride, [0075], of higher nitrogen content taught by Iyer’s layer 208 [0038]) comprises a second dielectric constant greater than the first dielectric constant. It is known in the art that silicon nitride has a higher dielectric constant when the nitrogen concentration is increased.
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Iyer in view of Lee, and further in view of Lee.
Regarding claim 28, Kwon in view of Iyer teach the semiconductor device of claim 27, wherein the air spacer (AG of Kwon, [0038]) comprises a curved cross-sectional profile.
Kwon in view of Iyer fail to teach the air spacer comprising a concave curvature facing towards the second nitride layer. However, the shape of the air gap is directly related to the second nitride layer, which has a concave shape. Lee teaches a similar spacer structure in which the shape of the dielectric (buffer layer, 45, [0035]) can either be concave or convex [0035], meaning the air gap of Kwon in view of Iyer would similarly be convex or concave facing the second dielectric layer respectively. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the air gap of Kwon in view of Iyer to the air spacer comprising a concave curvature facing towards the second nitride layer, as Lee teaches the shapes to be obvious variants of one another.
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Iyer in view of Lee, and further in view of Jung.
Regarding claim 29, Kwon in view of Iyer teach the semiconductor device of claim 27. Kwon in view of Iyer fail to disclose the S/D region comprises semiconductor layers with triangular-shaped cross-sectional profiles on sidewalls of the first and second nanostructured channel regions.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions. These epitaxial structures (230) structures are less doped than the surrounding 240 to minimize performance deterioration [0052]. While Jung teaches these regions 230 to be candle shaped, one of ordinary skill in the art would know that altering the shape of these regions to be triangles is merely a matter of choice, as evidenced by MPEP 2144.05:
“In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).” (MPEP 2144.04).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon to include the layered S/D regions of Jung and further modified to be a triangular shape depending on design choice.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iyer as applied to claim 27 above, and further in view of Jang et al. (US 2020/0220018 A1, hereafter Jang).
Regarding claim 32, Kim in view of Iyer teach the semiconductor device of claim 27. Kim in view of Iyer fail to teach a contact structure disposed on the S/D region, wherein the S/D region comprises:
first and second undoped S/D sub-regions disposed on the sidewalls of the first and second nanostructured channel regions, respectively;
a pair of doped S/D sub-regions extending vertically between the contact structure and the air spacer and disposed between the first and second undoped S/D sub-regions; and
a doped S/D sub-region extending vertically between the contact structure and the air spacer and disposed between the pair of doped S/D sub-regions.
However, Fig. 9 of Jang teaches a similar device with a contact structure (180, [0042]) disposed on the S/D region (150c, [0064]), wherein the S/D region (150c) comprises:
first and second undoped S/D sub-regions (151, [0058], see annotated Fig. 9) disposed on the sidewalls of the first and second nanostructured channel regions (CS of Kwon, [0031]), respectively; (epitaxial layer 151 of Jang is described as though it may include impurities, meaning the impurities are not necessary and may be excluded [0058])
a pair of doped S/D sub-regions (152c, [0064], see annotated Fig. 9) extending vertically between the contact structure (180) and the air spacer (AG of Kwon, [0038]) and disposed between the first and second undoped S/D sub-regions (151); (epitaxial layer 152 is described as having a higher impurity concentration compared to epitaxial layer 151, and as 151 is undoped, 152 would have to be doped [0058]) and
a doped S/D sub-region (154c, [0065]) extending vertically between the contact structure (180) and the air spacer (AG of Kwon) and disposed between the pair of doped S/D sub-regions (152) (epitaxial layer 154 is described as having a different type of impurity compared to epitaxial layer 152, implying 154 is doped as well).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the source/drain region of Kwon in view of Iyer to include the sub-regions taught by Jang in order to reduce short channel effects caused by diffusion of impurities ([0030] of Jang) and further include the source/drain contact of Jang to get the expected result of direct electrical contact to the device.
PNG
media_image6.png
416
387
media_image6.png
Greyscale
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
