CTNF 18/128,560 CTNF 90403 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Responsive to the communication dated 7/26/2024 Claims 1 – 20 are presented for examination. Priority ADS dated 3/30/2023 claims benefit of provisional 63/327021 dated 4/4/2022. No foreign priority claimed. Information Disclosure Statement IDS dated 7/26/2024 has been reviewed. See attached. Drawings The drawings dated 3/30/2023 have been reviewed. They are accepted. Specification The abstract dated 3/30/2023 has 103 words, 9 lines, and no legal phraseology. The abstract is accepted. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 3, 4, 5, 6, 7, 14, 15, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Arora_1996 (US 5,590,049) in view of Ray_1992 (US 5, 172,420) in view of Hagensen_2022 (Narrowband Microwave Bandpass Filter Design by Coupling Matrix Synthesis, Guided Wave Technology ApS, Hilleroed, Denmark, 4/1/2022) . Claim 1. Arora_1996 makes obvious “ A method of generating a multichip module design, the method comprising: receiving a multichip module design, the multichip module design ( abstract: “… verifying design constraint on printed circuit boards and multichip modules …; COL 1 lines 10 – 15: “… verifying constraints during the layout design of a printed circuit board or a multichip module …”; COL 1 lines 16 – 50: “an essential part of the design process for printed circuit boards and multichip modules is the definition of electrical, geometrical, and timing constraints that control the placement of circuit elements … the relative distance and positions of circuit elements with respect to one another… constraints define the electrical properties to be maintained by the circuit elements… during the design of the circuit … a number of design verification processes are implemented to test the accuracy and correctness of the design . One of the design verification processes is to test whether all of the specified constraints for all the circuit elements have been satisfied in the design… multichip module , so accurate verification of the constraints is critical to ensuring that the final circuit meets its specifications …”; COL 3 line 10: “… multichip module …”; COL 3 lines 45 – 47: “… the layout database 125 contains a coordinate representation of a printed circuit or multichip modul e layout that defines each of the circuits is elements in the circuit layout, and their relative placement and connections to one another…”; COL 6 lines 50 – 53: “… The process for verification 240 using the verification engine 123 is shown in FIG. 3. The design verification system 101 initializes 301 the verification engine 123 establishing appropriate memory structures in the addressable memory 115 for performing the verification…” FIGURE 1 illustrates layout database that is communicatively connected to the processor and the verification engine. EXAMINER NOTE: initializing the verification engine with a layout design in the addressable memory implies receiving the multichip module design as part of the layout database.) comprising a plurality of electrical components ( COL 1 lines 31 – 34: “… different types of circuit elements …”; COL 1 lines 43: “… all the circuit elements…”; COL 2 lines 28 – 38: “… hierarchical components for creating the electronic circuit, where each component has a component type, a design constraint, and is either a primitive circuit element or subhierarchical component … subhierarchical component… the hierarchical relations of the circuit components…”; COL 3 lines 47 – 48: “… each of the circuits is elements in the circuit layout …”; COL 4 lines 10 – 15: “… type or class of circuit elements in the circuit layout …”; COL 7 lines 54 – 56: “… design components in the electrical circuit, the electronic circuit including a selected plurality of interconnected components …”) and a plurality of signal paths defined between electrical components ( COL 1 lines 30 – 35: “… different constraints for the different types of circuit elements… such as requiring a minimum spacing between all signal paths …”; COL 3 lines 47 – 48: “… multichip module layout that defines each of the circuits is elements in the circuit layout, and their relative placement and connections to one another …”; COL 4 lines 10 – 15: “… constraint to a specific type or class of circuit element in the circuit layout . For example, specifying that a new constraint has a constraint attribute identity type “net” relates the new constraint to all net type circuit elements, that is, to all routing connections …” COL 5 Lines 47 -48: “… the designer is adding a connection net to a number or existing elements …”); simulating [verifying], for each electrical component and signal path, an isolation [constraint] between the electrical component or signal path and a plurality of other electrical components and signal paths ( FIGURE 3: block 305: “ for each circuit element ” block 307 “ for each constraint of circuit element ” block 313 “determine actual circuit element value” block 314: “constraint violation?” block 321 “another circuit element”; COL 1 lines 20 – 35: “… constraints that control the placement of circuit components … constraints specify the relative distance and positions of circuit elements with respect to one another… electrical constraints define the electrical properties to be maintained… constraints for the different types of circuit elements … such as requiring a minimum spacing between all signal paths …”); and updating the multichip module design based on the simulating [verification] (COL 7 lines 27 – 30: “… the designer is then able to retrieve the design rule violations that were marked 317 and correct them in the circuit layou t …; COL 3 lines 10 – 14: “… the display 105 provides a graphical user interface to the system 101, and allows the designer to graphically design a… multichip module … and to view and correct circuit elements during the design process …” EXAMINER NOTE: correcting a circuit layout or circuit elements based on identified rule violation is an updating of the circuit because the correction changes the circuit.). While Arora_1996 clearly teaches to verify a design to ensure the design meets requirements, including relative placement/position/distance and electrical properties, and to correct violations of requirements in the circuit design and that a user can implement their own constraints and add verification procedures to the verification engine ( COL 2 lines 1 – 3, lines 10 – 13 ), Arora_1996 does not recite that the constraint is, for example, an “isolation” constraint nor that the verification procedure is performed by “simulating.” Nevertheless, Ray_1992 makes obvious “isolation” constraints ( COL 1 lines 32 – 45: “… to reduce the overall size of such multi-chip modules … maintaining precise control of the dimensions of the features in each pattern is very important. If the dimensions of an individual feature in a pattern exceed the maximum allowable value under the operative design rule, the likelihood of leakage of a signal between such a feature and one adjacent to it becomes much higher , leading to possible “cross-talk .” EXAMINER NOTE: The above citation teaches that multi-chip module design is concerned with design rules that have prevent signal “leakage” between design elements and that when signals are not isolated this is called “cross-talk” and “cross-talk” is undesirable.) Arora_1996 and Ray_1992 are analogous art because they are from the same field of endeavor called multi-chip modules and/or circuits. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Arora_1996 and Ray_1992 . The rationale for doing so would have been that Arora_1996 teaches to have user defined (i.e., custom design rule that include electrical property design rules that are used to verify a multi-chip module design. Ray_1992 teaches to have design rules concerning signal leakage between adjacent electrical components for the purpose of presenting cross-talk. Therefore, it would have been obvious to combine the system and method for verifying multi-chip module design as taught by Arora_1996 with leakage and/or cross-talk design rules Ray_1992 for the benefit of ensuring that signals are isolated to their respective electrical components rather than leaking between components to obtain the invention as specified in the claims. While Arora_1996 teaches that the verification procedures can be provided to the verification engine, Ray_1992 teaches to use physical observations (e.g., physical experiments) to verify isolation of electrical elements so that there is no leakage or cross-talk. Accordingly, Arora_1996 and Ray_1992 does not teach a verification procedure that performs “simulating.” Hagensen_2022 , makes obvious “simulating” as a procedure to verify cross-coupling of electrical components ( Page 3/30 Introduction: “… the coupling matrix representation … the coupling matrix representation was introduced in the 1970s, but lately general methods have been introduced … the coupling matrix concept has been reformulated also to accommodate compiling directly from the source and the load to internal resonators… it is possible to transform between topologies whereby the best suited topology for a given problem may be found …”; page 9/30 section 3.1 “the N+2 Coupling Matrix… cross-coupling…”; Page 13/30: “… the right length may be found experimentally in a few trials or by use of a 3D EM simulator like HFSS …”; Page 16/30 section 4.3.1: “… may either be carried out by use of a 3D simulator or experimentally … it is clear that this is done most easily in a 3D simulator like HFSS [11] or CST [12]… if a 3D simulator is available, a more advanced technique may also be used, in which the coupling between more than just two neighboring resonators is taken into account. This technique is called co-simulation [13], and combines 3D modelling and circuit simulation t echniques…”; Page 24/30 section 4.5.1: “… improve the isolation between resonator 3 and 5 and between 2 and 4. One way of doing this could be to move the coupling apertures…”; page 28/30 section 6 conclusion: “ this article has dealt with the practical aspects of making physical… [device]… based on coupling matrix synthesis … this coupling matrix fully defines the… [device]… and, with this at hand, the corresponding… [device]… can be designed and manufactured … parameters can be determined either by use of 3D EM simulators or by measurement … to demonstrate the design process, two… [devices]… have been synthesized using the coupling matrix synthesis method and then manufactured… dimensions of… [components]… have been determined…” EXAMINER NOTE: The above citation teaches to use a 3D EM simulator to obtain a coupling matrix and then use the coupling information to modify and verify the design has the desired amount of coupling between components.) Ray_1992 and Hagensen_2022 are analogous art because they are from the same field of endeavor called circuits. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Ray_1992 and Hagensen_2022 . The rationale for doing so would have been Ray_1992 teaches make physical observations of cross-talk design rules and Hagensen_2022 teaches that a 3D simulator in conjunction with a cross coupling matrix can be used instead of physical experiment/measurements. Ray_1992 states: “by use of a 3D simulator or experimentally” and that it is done “most easily in a 3D simulator.” Therefore, it would have been obvious to combine design rules for leakage and cross-talk (i.e., electrical isolation between components) with 3D EM simulations for the benefit of having an easy way of designing an electrical component without needing to perform physical prototypes to obtain the invention as specified in the claims. Claim 3. Arora_1996 makes obvious “wherein the act of receiving a multichip module design includes generating a multichip module design” ( COL 1 lines 15 – 18: “… an essential part of the design process for printed circuit boards and multichip modules…”; COL 1 lines 39: “… during the design of the circuit…”; COL 3 lines 8 – 11: “… the system 101, and allows the designer to graphically design a printed circuit board or multichip module… and correct circuit elements during the design process …”) Claim 4. Hagensen_2022 makes obvious “wherein the act of simulating, for each electrical component and signal path, the isolation between the electrical component of signal path and the plurality of other electrical components and signal paths include: Generating a 3D model of the multichip module design; and Simulating, based on the 3D model and for each electrical component and signal path, the isolation between that component or signal path and the plurality of other electrical components and signal paths” (page 13/30: “… by use of a 3D EM simulator like HFSS…”; page 16/30: “… by use of a 3D simulator… most easily in a 3D simulator like HFSS… combines 3D modelling and circuit simulation…” EXAMINER NOTE: Ansys HFSS is a 3D electromagnetic field solver, and it fundamentally relies on 3D models to calculate how electromagnetic waves interact with physical structures and HFSS has a built-in 3D modeler that allows the building of detailed full-3D geometries.). Claim 5. Arora_1996 makes obvious “wherein the plurality of other electrical components and signal paths include every other electrical component and signal path of the multichip module design” ( COL 2 lines 28 – 38: “… hierarchical components for creating the electronic circuit, where each component has a component type, a design constraint, and is either a primitive circuit element or subhierarchical component… subhierarchical component… the hierarchical relations of the circuit components…”; FIGURE 3 block 305: “for each circuit element” block 307 “for each constraint of circuit element” EXAMINER NOTE: the above citation teaches to perform verification for all elements and all constraints. All elements include those in each sub-module and in different submodules.) Hagensen_2022 also makes obvious “wherein the plurality of other electrical components and signal paths include every other electrical component and signal path of the multichip module design” (page 8/30 section 3.1 illustrates the coupling matrix. EXAMINER NOTE: Notice that the coupling matrix is a matrix of the coupling between every node and accordingly the signal path includes every other electrical component and signal path of the circuit including those in the each sub-module and in different sub-modules.) Claim 6. Arora_1996 makes obvious “wherein the multichip module design includes a plurality of sub-modules, each sub-module including one or more of the plurality of electrical components and the plurality of signal paths, the plurality of other electrical components and signal paths include every other electrical component and signal path in each sub-module” ( COL 2 lines 28 – 38: “… hierarchical components for creating the electronic circuit, where each component has a component type, a design constraint, and is either a primitive circuit element or subhierarchical component… subhierarchical component… the hierarchical relations of the circuit components…”; FIGURE 3 block 305: “for each circuit element” block 307 “for each constraint of circuit element” EXAMINER NOTE: the above citation teaches to perform verification for all elements and all constraints. All elements include those in each sub-module and in different submodules.) Hagensen_2022 also makes obvious “wherein the multichip module design includes a plurality of sub-modules, each sub-module including one or more of the plurality of electrical components and the plurality of signal paths, the plurality of other electrical components and signal paths include every other electrical component and signal path in each sub-module” (page 8/30 section 3.1 illustrates the coupling matrix. EXAMINER NOTE: Notice that the coupling matrix is a matrix of the coupling between every node and accordingly the signal path includes every other electrical component and signal path of the circuit including those in the each sub-module and in different sub-modules.) Claim 7. Arora_1996 makes obvious “wherein the multichip module design include a plurality of sub-modules, each sub-module including one or more of the plurality of electrical components and the plurality of signal paths, the plurality of other electrical components and signal paths includes every other electrical component and signal path in a different sub-module” ( COL 2 lines 28 – 38: “… hierarchical components for creating the electronic circuit, where each component has a component type, a design constraint, and is either a primitive circuit element or subhierarchical component… subhierarchical component… the hierarchical relations of the circuit components…”; FIGURE 3 block 305: “for each circuit element” block 307 “for each constraint of circuit element” EXAMINER NOTE: the above citation teaches to perform verification for all elements and all constraints. All elements include those in each sub-module and in different submodules.) Hagensen_2022 also makes obvious “wherein the multichip module design include a plurality of sub-modules, each sub-module including one or more of the plurality of electrical components and the plurality of signal paths, the plurality of other electrical components and signal paths includes every other electrical component and signal path in a different sub-module” (page 8/30 section 3.1 illustrates the coupling matrix. EXAMINER NOTE: Notice that the coupling matrix is a matrix of the coupling between every node and accordingly the signal path includes every other electrical component and signal path of the circuit including those in the each sub-module and in different sub-modules.) Claim 14. Hagensen_2022 makes obvious “wherein each of the plurality of signal paths is represented by one or more nodes, and the isolation between a signal path and a plurality of the other electrical components and signal paths is simulated by comparing the isolation between each node of the signal path and the plurality of the other electrical components and signal paths” ( Figures 3, 4, 5, 9 ; page 8/9: “… source/load nodes”). Claim 15 . Arora_1996 makes obvious “wherein the method is performed iteratively, wherein the act of receiving a multichip design module includes receiving an updated multichip module design from a previous iteration of the method” ( COL 7 lines 27 – 30: “… once the circuit elements have been verified, the designer is then able to retrieve the design rule violations that were marked 317 and correct them in the circuit…”; COL 5 lines 40 – 45: “… in the preferred embodiment, the operation of the design verification system 101 is interactive, which each constraint being verified as the design instantiates new circuit elements and applies them to the circuit layout…” EXAMINER NOTE: The above teaches to “interactively” verify the design elements during the design process each time a new element is added and to correct the circuit. This indicates an iterative process by which the currently updated multichip module is received for future verifications as new circuit elements are added and/or changed.). Claim 16. Hagensen_2022 makes obvious “wherein simulating, for each electrical component and signal path, the isolation between the electrical component or signal path and the plurality of other electrical components and signal paths, outputs one or more of a table, a graph, and a spreadsheet” (Page 9/30 section 3.1 “coupling matrix”) 07-21-aia AIA Claim s 2, 17, 18, 8, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Arora_1996 in view of Ray_1992 in view of Hagensen_2022 in view of Zhu_2022 (US 2022/0344817 A1) . Claim 2. Arora_1996 makes obvious “further comprising, prior to updating the multichip module design: Comparing each simulation isolation to one or more predetermined isolation thresholds [constraints]; and Determining, based on the comparing of each simulated isolation to one or more predetermined isolation thresholds [constraints], whether the multichip module design meets one or more isolation design criteria; and updating the multichip module design is further based on whether the multichip module design meets the one or more isolation design criteria” (COL 3 lines 5 – 15: “… the design verification system 101… allows the designer to graphically design a printed circuit board or multichip module, and to create and input values for constraints, and to view and correct circuit elements during the design process…”; COL 7 lines 25 – 30: “… once all of the circuit elements have been verified, the designer is then able to retrieve the design rule violations that were marked 317 and correct them in the circuit layout …”) While Arora_1996 clearly teaches to compare design elements to design constraint values and if the design element does not conform to the constraint to subsequently update the design to correct the designs non-conformance. Arora_1996, however, does not explicitly recite that the constraint is evaluated, for example, as a threshold. Zhu_2022 makes obvious to have a constraint “ threshold” ( Par 24: “… circuitry 110 may have isolation thresholds that are desirable to reduce noise and optimize performance of the mmWave circuitry 110. As an example, elements of the mmWave circuitry 110 may have an isolation threshold of 40 decibels (dB) …”; Arora_1996 and Zhu_2022 are analogous art because they are from the same field of endeavor called circuits. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Arora_1996 and Zhu_2022. The rationale for doing so would have been that Arora_1996 teaches to perform constraint verification of circuit designs and that the verification may include electrical constraints for electrical properties. Zhu_2022 discussed electromagnetic coupling and teaches that it is “desirable to reduce noise and optimize performance” by having an electrical circuit that conforms to isolation threshold constraints measured in decibels. Therefore, it would have been obvious to combine the verification system which verifies that electrical circuit components meet electrical property constrains as taught by Arora_1996 with the electrical property constraint thresholds which provide a measurement of electrical isolation as taught by Zhu_2022 for the benefit of reducing circuit noise and optimizing circuit performance to obtain the invention as specified in the claims. Claim 8. Arora_1996 makes obvious “wherein updating the multichip module design includes, if it is determined that the multichip module design does not meet the one or more isolation design criteria, updating the multichip module design by adjusting at least one of the plurality of electrical components or plurality of signal paths that did not meet an isolation requirement with respect to another of the plurality of other electrical components or signal paths” ( COL 3 lines 5 – 15: “… the design verification system 101… allows the designer to graphically design a printed circuit board or multichip module, and to create and input values for constraints, and to view and correct circuit elements during the design process…”; COL 7 lines 25 – 30: “… once all of the circuit elements have been verified, the designer is then able to retrieve the design rule violations that were marked 317 and correct them in the circuit layout …”; COL 1 lines 16 – 35: “… constraints that control the placement of circuit component … constraints specify the relative distance and positions of circuit elements with respect to one anothe r, such as the position of ground lines with respect to power lines … the designer typically defines a variety of different constraints… such as requiring a minimum spacing between all signal paths … specific constraint value for a specific circuit element, overriding any generally defined constraint…”). Claim 9. Arora_1996 makes obvious “wherein adjusting at least one of the plurality of electrical components or plurality of signal paths includes moving at least one of the plurality of electrical components or plurality of signal paths that did not meet the isolation requirement with respect to another of the electrical components or signal paths with respect to that other electrical component or signal path” ( COL 3 lines 5 – 15: “… the design verification system 101… allows the designer to graphically design a printed circuit board or multichip module, and to create and input values for constraints, and to view and correct circuit elements during the design process…”; COL 7 lines 25 – 30: “… once all of the circuit elements have been verified, the designer is then able to retrieve the design rule violations that were marked 317 and correct them in the circuit layout …”; COL 1 lines 16 – 35: “… constraints that control the placement of circuit component … constraints specify the relative distance and positions of circuit elements with respect to one anothe r, such as the position of ground lines with respect to power lines … the designer typically defines a variety of different constraints… such as requiring a minimum spacing between all signal paths … specific constraint value for a specific circuit element, overriding any generally defined constraint…”). Claim 17. Arora_1996 makes obvious “further comprising manufacturing, if it is determined that the multichip module design does meet the one or more isolation design criteria, a multichip module in accordance with the multichip module design” ( COL 3 lines10 – 14: “… values for constraints and to view and correct circuit elements during the design process …”; COL 7 lines 25 – 30: “… once all of the circuit elements have been verified, the designer is then able to retrieve the design rule violations that were marked 317 and correct them in the circuit layout …” EXAMINER NOTE: if the circuit is corrected during design then it meets the design rules/constraints prior to manufacturing.) Hagensen_2022 also makes obvious “further comprising manufacturing, if it is determined that the multichip module design does meet the one or more isolation design criteria, a multichip module in accordance with the multichip module design” ( page 29/30: “… to demonstrate the design process, two 6 th order coaxial filters for WIMAX applications at 3.44 MHZ have been synthesized using the coupling matrix synthesis method a nd then manufactured … A single negative x-coupling has been applied to get the wanted characteristics . Dimensions of cavities, resonators, coupling apertures and I/O tap heights have been determined and the filter has been manufactured … the wanted characteristics has been obtained …” EXAMINER NOTE: this teaches to use a coupling matrix to identify cross coupling and to make modifications to the design to obtain desired circuit characteristics and then manufacture the circuit when it does meet the desired charcteristics.) Claim 18. Arora_1996 makes obvious “A multichip module manufactured according to the method of claim 17” ( COL 1 lines 14: “… multichip module…”) Ray_1992 also makes obvious “A multichip module manufactured according to the method of claim 17” ( COL 1 lines 19: “… development of multichip electronic modules…”) Hagensen_2022 also makes obvious “A multichip module manufactured according to the method of claim 17” ( page 29/30: “… to demonstrate the design process… using the coupling matrix synthesis method and then manufactured… applied to get the wanted characteristics. Dimensions… have been determined and the filter has been manufactured… the conclusion of this work… it is possible to design and manufacture…”). Accordingly, in combination Arora_1996 clearly teaches to verify a multi-chip module design and to correct any non-conformance to desired characteristics while Ray_1992 also teaches to design a multi-chip module where the desired characteristics include conformance to operative design rules that include reduced leakage of signals between circuit elements in order to prevent cross-talk and thereby isolating elements of the circuit from each other. Further, Hagensen_2022 teaches to perform manufacturing after a design process achieves a design with the “wanted characteristics”. Therefore, it would have been obvious to those of ordinary skill in the art to manufacture a multi-chip module design once the multi-chip module design has been verified to conform to the wanted characteristics, such as, reduced cross-talk between circuit elements. Further, Claim 18 is a product-by-process claim. In such a claim, it is not the product (i.e., a multichip module) that has patentable weight when the product is structurally identical to existing products. This holds true even if the process is unique. In this instance, however, the process of claim 17 provides no detail of the actual manufacturing process. Claim 17 simply indicates to perform a generic manufacturing after deciding that the multichip module design meets design requirement. In other words, the Applicant is claiming a multichip module that was, at some point, manufactured after someone decided the design met their design requirements. Such a multichip module is, on its face, obvious to those of ordinary skill in the art . 07-21-aia AIA Claim s 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Arora_1996 in view of Ray_1992 in view of Hagensen_2022 in view of Zhu_2022 in view of Okabe_2005 (US 2005/0176380 A1) . Claim 19 . Okabe_2005 makes obvious “ A radio-frequency module comprising the multichip module of claim 18” (par 2: “… a radio frequency (RF) circuit module that is employed in wireless communication equipment…”; par 3: “one technique for downsizing portable equipment is circuit integration of electronic circuits and another is module implementation, that is, assembling multiple electronic circuit units in one module. The module implementation method is widely used for RF circuit blocks of wireless communication equipment to achieve high performance of the circuit blocks at low cost…”) Arora_1996 and Okabe_2005 are analogous art because they are from the same field of endeavor called multichip modules. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Arora_1996 and Okabe_2005. The rationale for doing so would have been that Arora_1996 teaches to have a verification system for multi-chip modules that verifies design rules and constraints and to correct the design to conform to the design rules and constraints. Okabe_2005 teaches to have a multi-chip module for radio frequency circuits used in wireless devices because (1) doing so is widely used for RF circuits (2) it lowers cost and (3) downsizes circuits for portable equipment. Therefore, it would have been obvious to combine the verification system of Arora_1996 with a radio-frequency multi-chip module for the benefit of having a radio-frequency multi-chip module that conforms to design rules and constraints to obtain the invention as specified in the claims. Further, this claim is also a product-by-process claim and such claims are not patentably distinct if there are no claimed structural differences between the resulting product and the prior art product. Claim 20. Okabe_2005 makes obvious “A wireless device comprising the radio-frequency module of claim 19” (par 2: “… a radio frequency (RF) circuit module that is employed in wireless communication equipment…”; par 3: “one technique for downsizing portable equipment is circuit integration of electronic circuits and another is module implementation, that is, assembling multiple electronic circuit units in one module. The module implementation method is widely used for RF circuit blocks of wireless communication equipment to achieve high performance of the circuit blocks at low cost…”) Further, this claim is also a product-by-process claim and such claims are not patentably distinct if there are no claimed structural differences between the resulting product and the prior art product . 07-21-aia AIA Claim s 10, 11, 12, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Arora_1996 in view of Ray_1992 in view of Hagensen_2022 in view of Zhu_2022 in view of Sierra_Circuits_2020 (How to Avoid Crosstalk in HDI Substrates October 5, 2020, downloaded from https://www.protoexpress.com/blog/how-to-avoid-crosstalk-hdi-substrates) . Claim 10. Sierra_Circuits_2020 makes obvious “wherein the multichip module design includes a plurality of layers, and wherein moving at least one of the plurality of electrical components of plurality of signal paths includes moving at least one of the plurality of electrical components or plurality of signal paths to a different layer” ( page 7/17: “… the following measures can be adopted to avoid crosstalk… do not route two parallel wires over a long distance in the same layer…” EXAMINER NOTE: this teaches that if there is crosstalk between two components in the same layer to move one of the components to another layer. This is an application of increasing the relative distance between two components in the vertical/Z direction). Arora_1996 and Sierra_Circuits_2020 are analogous art because they are from the same field of endeavor called electrical circuits. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Arora_1996 and Sierra_Circuits_2020. The rationale for doing so would have been that Arora_1996 teaches to verify circuit design and to make corrections to the circuit design if there are failures of electrical property rules/constraints. Sierra_circuits_2020 teaches ways to correct circuits to avoid an undesirable electrical property known as crosstalk. Therefore, it would have been obvious to combine Arora_1996 and Sierra_Circuits_2020 for the benefit of correcting unintentional or unwanted electromagnetic coupling in circuit that have multiple layers to obtain the invention as specified in the claims. Claim 11. Sierra_Circuits_2020 makes obvious “wherein the multichip module design includes a plurality of layers, and wherein adjusting at least one of the plurality of electrical components or plurality of signal paths includes introducing a ground layer into the multichip module design between two different layers” ( page 7/17: “… crosstalk between the signal layers in different layers can be reduced by designing a ground layer between the signal layers…”; page 10/17: “… the designer should care about the signal layer; no two signal layers should be adjacent. Place the ground layer between all signal layers…”) Arora_1996 and Sierra_Circuits_2020 are analogous art because they are from the same field of endeavor called electrical circuits. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Arora_1996 and Sierra_Circuits_2020. The rationale for doing so would have been that Arora_1996 teaches to verify circuit design and to make corrections to the circuit design if there are failures of electrical property rules/constraints. Sierra_circuits_2020 teaches ways to correct circuits to avoid an undesirable electrical property known as crosstalk. Therefore, it would have been obvious to combine Arora_1996 and Sierra_Circuits_2020 for the benefit of correcting unintentional or unwanted electromagnetic coupling in circuit that have multiple layers to obtain the invention as specified in the claims. Claim 12. Sierra_Circuits_2020 makes obvious “ wherein adjusting at least one of the plurality of electrical components or plurality of signal paths includes rotating at least one of the plurality of electrical components or plurality of signal paths” ( page 7/17: “… do not route two parallel wires over a long distance in the same layer. Also, the layers adjacent to the traces should be perpendicular …” EXAMINER NOTE: this is teaching that rather than having wires run parallel that wires should be rotated 90 degrees so that they run perpendicular.). Arora_1996 and Sierra_Circuits_2020 are analogous art because they are from the same field of endeavor called electrical circuits. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Arora_1996 and Sierra_Circuits_2020. The rationale for doing so would have been that Arora_1996 teaches to verify circuit design and to make corrections to the circuit design if there are failures of electrical property rules/constraints. Sierra_circuits_2020 teaches ways to correct circuits to avoid an undesirable electrical property known as crosstalk. Therefore, it would have been obvious to combine Arora_1996 and Sierra_Circuits_2020 for the benefit of correcting unintentional or unwanted electromagnetic coupling in circuit that have multiple layers to obtain the invention as specified in the claims. Claim 13. Sierra_Circuits_2020 makes obvious “wherein adjusting at least one of the plurality of electrical components or plurality of signal paths includes moving one or more pins of the plurality of electrical components” ( page 9/17: “… provide the return path as close as possible to the signal path… moving the ground pin close to the signal pin can minimize the loop area…” See below: PNG media_image1.png 456 784 media_image1.png Greyscale ; page 10/17: “… using the same pin for the ground path from several signals creates nested loops with high mutual inductance. The PCB designers must consider separate ground return pins, which should be at a minimum distance from the signal pins to reduce the inductive coupling…” See below: PNG media_image2.png 632 785 media_image2.png Greyscale Arora_1996 and Sierra_Circuits_2020 are analogous art because they are from the same field of endeavor called electrical circuits. Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to combine Arora_1996 and Sierra_Circuits_2020. The rationale for doing so would have been that Arora_1996 teaches to verify circuit design and to make corrections to the circuit design if there are failures of electrical property rules/constraints. Sierra_circuits_2020 teaches ways to correct circuits to avoid an undesirable electrical property known as crosstalk. Therefore, it would have been obvious to combine Arora_1996 and Sierra_Circuits_2020 for the benefit of correcting unintentional or unwanted electromagnetic coupling in circuit that have multiple layers to obtain the invention as specified in the claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN S COOK whose telephone number is (571)272-4276. The examiner can normally be reached 8:00 AM - 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Emerson Puente can be reached at 571-272-3652. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRIAN S COOK/Primary Examiner, Art Unit 2187 Application/Control Number: 18/128,560 Page 2 Art Unit: 2187 Application/Control Number: 18/128,560 Page 3 Art Unit: 2187 Application/Control Number: 18/128,560 Page 4 Art Unit: 2187 Application/Control Number: 18/128,560 Page 5 Art Unit: 2187 Application/Control Number: 18/128,560 Page 6 Art Unit: 2187 Application/Control Number: 18/128,560 Page 7 Art Unit: 2187 Application/Control Number: 18/128,560 Page 8 Art Unit: 2187 Application/Control Number: 18/128,560 Page 9 Art Unit: 2187 Application/Control Number: 18/128,560 Page 10 Art Unit: 2187 Application/Control Number: 18/128,560 Page 11 Art Unit: 2187 Application/Control Number: 18/128,560 Page 12 Art Unit: 2187 Application/Control Number: 18/128,560 Page 13 Art Unit: 2187 Application/Control Number: 18/128,560 Page 14 Art Unit: 2187 Application/Control Number: 18/128,560 Page 15 Art Unit: 2187 Application/Control Number: 18/128,560 Page 16 Art Unit: 2187 Application/Control Number: 18/128,560 Page 17 Art Unit: 2187 Application/Control Number: 18/128,560 Page 18 Art Unit: 2187 Application/Control Number: 18/128,560 Page 19 Art Unit: 2187 Application/Control Number: 18/128,560 Page 20 Art Unit: 2187 Application/Control Number: 18/128,560 Page 21 Art Unit: 2187 Application/Control Number: 18/128,560 Page 22 Art Unit: 2187
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