Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially evenly” in claims 1, 10, and 19 is a relative term which renders the claim indefinite. The term “substantially evenly” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The remaining claims mentioned in the header depend from the above independent claims and do not further clarify what is meant by “substantially evenly” and are therefore also rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 10-15, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanno, US PGPub 2019/0004724, in view of Lercari et al., US PGPub 11,675,708, hereafter “Lercari,” and further in view of Kotte et al., US PGPub 2018/0260331, hereafter “Kotte.”
With respect to claim 10, Kanno teaches a system, comprising:
a plurality of non-volatile random access memory (NVRAM) blocks configured to store data (par. 52, the memory cell array of the NAND flash memory includes a plurality of blocks for writing and reading data); and
a processor and logic integrated with and/or executable by the processor (par. 50, controller 4), the logic being configured to:
receive specification of an amount of drive space in a solid state drive (SSD) to emulate, the specified amount being less than all of the drive space of the SSD (par. 154, the specified capacity of the user region, which is less than the total capacity); and
format the SSD such that only a number of blocks that provides the specified amount of drive space are made available (par. 155, the specified capacity of the user region is allocated for the user region),
wherein a presented amount of drive space of the SSD corresponds to the specified amount of drive space (par. 151, the visible capacity corresponds to the specified capacity of the user region);
Kanno doesn’t specifically use the word “skipped” when mentioning the overprovisioned blocks and doesn’t disclose wherein the available blocks are distributed substantially evenly across planes of the SSD, wherein a presented amount of drive space of the SSD corresponds to the specified amount of drive space. Lercari teaches:
wherein the other blocks are skipped (col. 6, line 67, through col. 7, line 6, reserved and defective erase units (blocks) are skipped)
wherein the available blocks are distributed substantially evenly across planes of the SSD (col. 21, lines 59-66, the erase units (blocks) are distributed evenly between even and odd erase-unit planes).
Kanno and Lercari fail to disclose wherein parameters of the SSD that are dependent upon capacity are scaled based on the specified amount of drive space relative to an actual amount of drive space of the SSD. Kotte teaches:
wherein parameters of the SSD that are dependent upon capacity are scaled based on the specified amount of drive space relative to an actual amount of drive space of the SSD (pars. 47 and table 1 and table 2, which shows the parameters such as pSLC read cache size and pSLC write cache size are scaled based on the OP ratio, table 1 showing one OP ratio, and table 2 showing another).
It would have been obvious to one of ordinary skill in the art, having the teachings of Kanno and Lercari before him before the earliest effective filing date, to modify the SSD system of Kanno with the SSD system of Lercari, as skipping over reserved and defective erase units facilitates virtualizing the pool of erase units, which facilitates configurable and predictable I/O latency, and greatly shortens address translation time and associated complexity, as taught by Lercari in col. 6, line 67, through col. 7, line 36. Further, it would have been obvious to one of ordinary skill in the art, having the teachings of Kanno, Lercari and Kotte before him before the earliest effective filing date, to modify the SSD system of Kanno and Lercari with the SSD system of Kotte, in order for NAND media to have better endurance and longevity, as taught by Kotte in par. 78.
With respect to claim 11, Kanno, Lercari and Kotte teach the limitations of the parent claim. Kotte further teaches the system of claim 10, wherein the specified amount of drive space to emulate is less than 81% (par. 34, the amount of overprovisioning for enterprise applications is 28%, meaning the emulated drive space (non OP area) is 72%).
With respect to claim 12, Kanno, Lercari and Kotte teach the limitations of the parent claim. Kotte further teaches the system of claim 11, wherein the specified amount of drive space to emulate is at least 50% (par. 34, the amount of overprovisioning for enterprise applications is 28%, meaning the emulated drive space (non OP area) is 72%).
With respect to claim 13, Kanno, Lercari and Kotte teach the limitations of the parent claim. Kotte further teaches the system of claim 10, comprising enforcing an unmodified card single level cell (SLC)/quad level cell (QLC) ratio among the blocks (pars. 36-40, the SLC/QLC ratio is determined based on the write flush threshold).
With respect to claim 14, Kanno, Lercari and Kotte teach the limitations of the parent claim. Kotte further teaches the system of claim 13, wherein the skipped blocks are marked so that a SLC and QLC Pools (SQP) engine ignores the skipped blocks (pars. 33-34, the area designated for overprovisioning corresponds to the skipped blocks, and are outside of the SLC and QLC areas).
With respect to claim 15, Kanno, Lercari and Kotte teach the limitations of the parent claim. Kotte further teaches the system of claim 10, wherein the specification is received as a percentage, wherein the presented amount of drive space is determined by scaling an actual amount of drive space in the SSD according to the percentage (par. 34, the overprovisioning (OP) ratio is received as a percentage, which is used to allocate the area for user data).
Claims 1-6 are a method that correspond to claims 10-15, and are rejected using similar logic.
Claim 19 is a computer program product that corresponds to claim 10, and is rejected using similar logic.
With respect to claim 20, Kanno, Lercari and Kotte teach the limitations of the parent claim, but fail to specify the percentage of drive space to emulate. Kotte further teaches the computer program product of claim 19, wherein the specified amount of drive space to emulate is at least 50% and less than 81% (par. 34, the amount of overprovisioning for enterprise applications is 28%, meaning the emulated drive space (non OP area) is 72%).
Claim(s) 7-9 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanno, Lercari and Kotte as applied to claims 1 and 10 above, and further in view of Ben-Yehuda et al., US Patent 11,442,658, hereafter, “Ben-Yehuda.”
With respect to claim 16, Kanno, Lercari and Kotte teach the limitations of the parent claim, but fail to teach wherein the logic is configured to fill the available blocks. Ben-Yehuda further teaches the system of claim 10, wherein the logic is configured to fill the available blocks (col. 11, lines 29-38, filling the storage device above a predetermined level).
It would have been obvious to one of ordinary skill in the art, having the teachings of Kanno, Lercari, Kotte, and Ben-Yehuda before him before the earliest effective filing date, to modify the SSD system of Kanno, Lercari, and Kotte, with the SSD system of Ben-Yehuda, in order to improve the endurance of the block storage device as well as the overall performance of read operations, as taught by Ben-Yehuda in col. 3, lines 54-59.
With respect to claim 17, Kanno, Lercari, Kotte and Ben-Yehuda teach the limitations of the parent claim. Ben-Yehuda further teaches the system of claim 16, wherein the logic is configured to precondition the filled blocks (col. 11, lines 29-38, preconditioning the block storage device).
With respect to claim 18, Kanno, Lercari, Kotte and Ben-Yehuda teach the limitations of the parent claim. Ben-Yehuda further teaches the system of claim 18, wherein the logic is configured to perform testing of the preconditioned blocks (col. 11, line 52, through col. 12, line 8, performing I/O operations and testing the storage device by collecting performance metrics).
Claims 7-9 are a method that corresponds to claims 16-18, and are rejected using similar logic.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bennett et al., US PGPub 2024/0377960 teaches a flexible SSD with overprovisioning techniques. Lee et al., US PGPub 20240201865 teaches overprovisioning at the plane level of flash. Rajwade et al., US PGPub 2023/0154539 teaches skipping pages in an SSD. Shim et al., US PGPub 2023/0153001 teaches distributing blocks evenly across planes. Jang et al., US PGPub 2022/0253239 teaches overprovisioning and QLC/SLC ratio. Huang et al., US PGPub 2022/0043588 teaches evenly distributing data across planes of a memory. Papandreou et al., US PGPub 2021/014592 teaches SLC to QLC ratio on an SSD. Tomlin et al., US Patent 9,286,176 teaches selective skipping of blocks on an SSD. Meir et al., US PGPub 2012/0246391 teaches overprovisioning and MLC and SLC areas on an SSD.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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