Prosecution Insights
Last updated: August 17, 2026
Application No. 18/128,805

DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI

Non-Final OA §103
Filed
Mar 30, 2023
Examiner
PHUNG, LUAT
Art Unit
2468
Tech Center
2400 — Computer Networks
Assignee
Amd
OA Round
3 (Non-Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
3m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
464 granted / 608 resolved
+18.3% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
31 currently pending
Career history
654
Total Applications
across all art units

Statute-Specific Performance

§101
4.8%
-35.2% vs TC avg
§103
57.1%
+17.1% vs TC avg
§102
22.9%
-17.1% vs TC avg
§112
8.0%
-32.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 608 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicants’ arguments filed on 5 June 2026 have been fully considered but they are moot in view of the new ground of rejection. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dorsey et al (US Pub. 2009/0138745) in view of Ma (US Pub. 2024//0212562). Regarding claim 1: "An apparatus comprising:" Dorsey discloses an apparatus including one or more radio-frequency transceivers and one or more clocked electronic components configured to reduce radio-frequency interference by dynamically selecting operating clock frequencies (¶¶3-5, 42-50, 61-68). "a clocked component of a computing system distinct from a radio module of the computing system, wherein the clocked component is configured to perform processing operations using a first clock frequency, and wherein the clocked component comprises circuitry configured to:" Dorsey discloses a clocked component distinct from the radio module, including processors, memory devices, display circuitry, application-specific integrated circuits (ASICs), input/output circuitry, and other electronic components operating using adjustable clock sources (¶¶47-50). Dorsey further teaches that these clocked components perform processing operations using operating clock frequencies that may be adjusted to reduce interference with radio operation (¶¶47-50, 61-68). "receive an indication, based on operation of the radio module, identifying one or more frequency ranges to be avoided;" Dorsey discloses receiving information identifying operating frequencies of the radio module, determining victim frequencies associated with operation of the radio module, identifying one or more frequency ranges to be avoided based on operation of the radio module, determining safe operating clock frequencies, determining unsafe operating clock frequencies, and controlling operating clock frequencies based upon the identified frequency ranges (¶¶11, 61-68, 73-80, 92-100). "and in response to the first clock frequency overlapping at least one of the one or more frequency ranges, cause the clocked component to operate using a second clock frequency that is selected by the circuitry and is outside the one or more frequency ranges." Dorsey further discloses determining whether an operating clock frequency overlaps the identified frequency ranges, identifying corresponding safe operating clock frequencies outside the identified frequency ranges, selecting an alternate operating clock frequency from the identified safe operating clock frequencies, and adjusting the adjustable clock source so that the clocked component operates using the selected clock frequency outside the identified frequency ranges to avoid interference with operation of the radio module (¶¶11, 61-68, 95-100). However, Dorsey does not expressly disclose that the circuitry of the clocked component itself (i) receives the indication identifying the one or more frequency ranges to be avoided, and (ii) selects the second clock frequency and causes the clocked component to operate using the selected second clock frequency. Ma discloses independently operating clock domains in which local circuitry associated with an individual clock domain performs control operations using a local clock. Specifically, Ma discloses a receiving sub-circuit, a writing control component, a reading control component, a selecting component, and associated local control circuitry operating within the local clock domain (¶¶44-49). Ma further teaches that the local control circuitry performs control operations within the associated clock domain using the local clock (¶¶50-58), thereby implementing clock-management functionality within circuitry associated with the individual clock domain rather than exclusively through centralized control circuitry. It would have been obvious to one of ordinary skill in the art at the time of the invention to implement Dorsey's known RF coexistence clock-management functionality using the local circuitry associated with the individual clocked component as taught by Ma. Dorsey already teaches receiving RF operating information, identifying frequency ranges to be avoided, determining whether an operating clock frequency overlaps the identified frequency ranges, selecting a safe operating clock frequency outside the identified frequency ranges, and causing the clocked component to operate using the selected safe clock frequency. Ma teaches that such clock-management functionality may be implemented by local circuitry associated with individual clock domains. Implementing Dorsey's known clock-selection functionality within Ma's distributed clock-domain architecture would have been a predictable design choice that improves modularity, facilitates independent management of multiple clock domains, reduces centralized clock-management overhead, and achieves the same known objective of operating the clocked component at a clock frequency outside the identified frequency ranges with a reasonable expectation of success. Regarding claim 2: "The apparatus of claim 1, wherein the clocked component is a memory device configured to store video frame data accessed by a graphics processing unit." Dorsey further discloses that the clocked component may be a memory device. Specifically, Dorsey teaches processors, memory devices, display circuitry, ASICs, and other electronic components whose operating clocks are adjusted to mitigate interference with radio operation (¶¶47-50). Accordingly, Dorsey teaches the additional limitation of claim 2. Regarding claim 3: "The apparatus of claim 2, wherein the first clock frequency is used for communication between the memory device and the graphics processing unit." Dorsey further discloses clock signals used by memory devices and associated processing circuitry, including processors and graphics circuitry operating using adjustable clock sources (¶¶47-50, 61-68). It would have been obvious that the operating clock adjusted by Dorsey is the clock used for communication between the memory device and the graphics processing unit because those components communicate using the disclosed system clocks. Regarding claim 4: "The apparatus of claim 3, wherein the circuitry is further configured to cause the clocked component to operate using the second clock frequency such that an absolute value of a difference between the second clock frequency and a lower frequency limit or an upper frequency limit of at least one of the one or more frequency ranges is greater than a threshold." Dorsey further discloses determining unsafe frequency ranges, identifying safe operating clock frequencies outside those ranges, and selecting replacement clock frequencies sufficiently separated from the prohibited frequency ranges to avoid interference (¶¶95-100). Selecting a replacement clock frequency having a separation greater than a threshold from the identified frequency ranges would have been an obvious matter of routine optimization to ensure an adequate interference margin while maintaining desired system performance. Regarding claim 5: "The apparatus of claim 1, wherein the indication is received via system firmware or a network interface, and further specifies at least one harmonic range of the one or more frequency ranges." Dorsey further discloses receiving operating constraints and desired radio operating frequencies from system software or firmware for use in determining safe operating clock frequencies (¶¶73-74). Dorsey further discloses determining harmonic frequencies and harmonic interference ranges associated with radio operation (¶¶95-100). Accordingly, Dorsey teaches the additional limitation of claim 5. Regarding claim 6: "The apparatus of claim 1, wherein the component is an access point." Dorsey further discloses wireless communication devices, including wireless access points operating according to IEEE 802.11 wireless networking standards (¶¶6, 45). Accordingly, Dorsey teaches the additional limitation of claim 6. Regarding claim 7: "The apparatus of claim 1, wherein the circuitry is further configured to: determine one or more harmonic frequencies of operating frequency ranges used by a plurality of radio modules, in response to an indication from a power manager specifying a third clock frequency; and use the third clock frequency, in response to the third clock frequency not overlapping any of the one or more harmonic frequencies of operating frequency ranges used by the plurality of radio modules." Dorsey further discloses determining one or more harmonic frequencies associated with operating frequencies of radio modules, identifying unsafe harmonic frequencies, determining safe clock frequencies, and using the selected safe clock frequency when it does not overlap the identified harmonic frequencies (¶¶95-100; Fig. 11, elements 158 and 172). Accordingly, Dorsey teaches the additional limitations of claim 7. Claim 8 recites a method corresponding to the apparatus of claim 1, and is thus similarly rejected. Claims 9-14 recite substantially identical subject matter as recited in claims 2-7, respectively, and are thus similarly rejected. Regarding claim 15, Dorsey discloses a computing system (fig. 2) comprising: network interface circuitry comprising radio frequency circuitry (fig. 2, para. 42); and a processing node comprising a plurality of components (fig. 2, para. 39); wherein circuitry of a given component of the plurality of components is substantially identical to the apparatus of claim 1, and is thus similarly rejected. Claims 16, 18, 19 recite substantially identical subject matter as recited in claims 2-4, respectively, and are thus similarly rejected. Regarding claim 17, Dorsey further discloses wherein the first clock frequency is a clock frequency of a clock signal conveyed to the memory device (para. 38, 79). Claims 20 recites substantially identical subject matter as recited in claim 6 and is thus similarly rejected. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUAT T PHUNG whose telephone number is (571)270-3126. The examiner can normally be reached on M-F 9 AM - 6 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marcus Smith can be reached on (571) 272-3988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Luat Phung/ Primary Examiner, Art Unit 2468
Read full office action

Prosecution Timeline

Show 1 earlier event
Jul 16, 2025
Non-Final Rejection mailed — §103
Nov 11, 2025
Response Filed
Mar 11, 2026
Final Rejection mailed — §103
May 19, 2026
Applicant Interview (Telephonic)
May 21, 2026
Examiner Interview Summary
Jun 05, 2026
Request for Continued Examination
Jun 14, 2026
Response after Non-Final Action
Jul 01, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
89%
With Interview (+12.5%)
3y 8m (~3m remaining)
Median Time to Grant
High
PTA Risk
Based on 608 resolved cases by this examiner. Grant probability derived from career allowance rate.

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