CTNF 18/128,867 CTNF 74911 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are now pending in the application under prosecution and have been examined. The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented. The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art. In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application. Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. 37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features. Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c). Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 20200202971 A1 (GIACCIO et al) in view of US 20160034206 (RYAN et al) . With respect to claim 7, US 20200202971 A1 (GIACCIO et al) teaches computer program product for testing a solid state drive, the computer program product comprising: one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media (computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods carrying instructions for execution by the machine to robustly test performance of memory devices in the event of unexpected failures such as power loss, the system including power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test) [Par. 0029-0031; Par. 0044-0048] , the program instructions comprising: program instructions to store a list of states for testing the effects of power loss by a solid state drive (one or more test conditions recorded to make a record of a chain of events associated with triggering power loss in the memory device under test) [Par. 0042; Par. 0036-0038) ; program instructions to receive selection of one or more of the states; program instructions to instruct the solid state drive to generate an interrupt upon detecting the one or more of the selected states, wherein the interrupt triggers a power loss to the solid state drive (receiving or providing input test conditions of memory under test to a power loss logic, where one or more test conditions have been met in an exchange between host device and the memory device under test, the power loss logic to trigger a power loss in the memory device under test by sending an enable signal to the power management device) [Par. 0027-0028] . GIACCIO fails to specifically teach program instructions to initiate performance of a workload by the solid state drive. However, RYAN teaches system and method monitoring historical health metrics of memory device, measuring the performance effects of flash memory block and attempting to recover (read) test patterns with different sets of operating parameters, one or more control registers storing the operating parameters associated with wherein, in response application of varying levels of electrical stimuli to the flash memory blocks in accordance with current values of the operating parameters, i.e., power loss condition triggered, adaptively tuning the operating parameters of flash memory chips during their operational lifetime [Abstract; Par. 0037-0039; Par. 0186-0190] . Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing of the instant application, to use the input test conditions of memory of GIACCIO and feature instructing the solid state drive to generate an interrupt upon detecting the one or more of the selected states to initiate performance, as taught by RYAN, in order to identify data that was in the process of being written (e.g., aborted data) and/or data that had already been written to an aborted memory cell, such that the data can be programmed in a more time-efficient and/or power-efficient manner, as taught by RYAN . Independent claims 1 and 13 , repeat the features of rejected claim 7, in other claim format, are rejected under the same arguments. With respect to claims 2, 8, and 14, GIACCIO and RYAN , combined, teach computer program product wherein the program instructions to instruct include program instructions to send instructions to program a controller of the solid state drive to detect the one or more of the selected states and generate the interrupt (test conditions protocol, device management entity, external trigger, counter, and timer checked and used to trigger a test power loss event) [GIACCIO ‘s Par. 0035-0037] . With respect to claims 3, 9, and 15, GIACCIO and RYAN , combined, teach computer program product, comprising removing the programming to detect the one or more of the selected states from the controller after processing the workload (after a protocol command has been used a selected number of times, a counter triggered to program check condition logic block that triggers power loss event) [GIACCIO ‘s Par. 0036-0037] . With respect to claims 4,10, and 16, GIACCIO and RYAN , combined, teach computer program product, wherein the controller is not in charge of a flash translation layer of the solid state drive (memory controller to include circuitry or firmware, such as a number of components or integrated circuits, one or more memory control units, circuits, or components configured to control access across the memory array and to provide a translation layer between the host device and the storage system) [GIACCIO’s Par. 0021] . With respect to claims 5, 11, and 17, GIACCIO and RYAN , combined, teach computer program product, wherein the controller is programmed to send the interrupt to a separate processor on the solid state drive, the separate processor causing the power loss (communication to and from a memory device passes through the Unipro layer and the parameters of the communication protocol are interpreted by the write/read datapath host controller blocks) [GIACCIO ‘s Par. 0032-0034; Par. 0029-0030] . With respect to claims 6, 12, and 18, GIACCIO and RYAN , combined, teach computer program product, wherein the controller is programmed to send the interrupt to an independent system that causes the power loss (device management entity, external trigger, counter, and timer checked and used to trigger a test power loss event) [GIACCIO ‘s Par. 0035-0037] . With respect to claim 19, GIACCIO and RYAN, combined, teach computer program product wherein the power loss is caused by severing the power provided to the solid state drive from an external source (memory event may be specifically tested with a targeted power loss includes a protocol event in transmission of a packet from the memory device under test to the host device with a targeted power loss includes an externally triggered event that may be triggered at a specified time) [GIACCIO ‘s Par. 0028-0030] . 07-21-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US 20200202971 A1 (GIACCIO et al) in view of US 20160034206 (RYAN et al) and further in view of US 20170228154 (KIM et al) . With respect to claim 20, GIACCIO and RYAN , combined, teach the invention as claimed, but fails to specifically teach computer program product detecting the power loss; and backing up a cache and metadata structures in response to detecting the power loss. However, LIU teaches buffered data directly written to a blank power loss block of the power loss region to form a power loss backup, and an auxiliary mark is created for confirming the most updated power loss backup, the power loss backup is directly read from the power loss region according to the most updated power loss auxiliary mark of the power loss backup to restore the original state of the SSD before the power is interrupted [Abstract; Par. 0014; Par. 0030-0032]. Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing of the instant application, to combine the features of GIACCIO and RYAN and backing up the buffered data and metadata, as taught by LIU, in order to resolve in the technology field of SSD power loss protection, as taught by LIU [Par. 10] . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. N. R. Mielke, R. E. Frickey, I. Kalastirsky, M. Quan, D. Ustinov and V. J. Vasudevan, "Reliability of Solid-State Drives Based on NAND Flash Memory," in Proceedings of the IEEE, vol. 105, no. 9, pp. 1725-1750, Sept. 2017. H. -W. Tseng, L. Grupp and S. Swanson, "Understanding the impact of power loss on flash memory," 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), San Diego, CA, USA, 2011, pp. 35-40. L. Zuolo, C. Zambelli, R. Micheloni and P. Olivo, "Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance," in Proceedings of the IEEE, vol. 105, no. 9, pp. 1589-1608, Sept. 2017. US 10847244 B2 (KIM et al) teaching storage device including a non-volatile memory storing user data, a volatile memory buffering the user data and performing a test for detecting a defective cell on a volatile cell array at an idle time of the storage device, and a controller controlling the volatile memory to perform the test at an idle time and storing test information including a test result or a test history in the non-volatile memory. US 20240095139 A1 (GANGADHAR et al) mechanism for saving one or more SSD drive parameters (drive states) of an SSD to volatile memory of the SSD using an SSD controller, the one or more SSD drive parameters (drive states) include one or more of: a drive health parameter, a drive internal statistic, drive thermal information, drive debug information, a number of host and non-volatile memory read and writes, media error handling data, temperature and throttle information, and firmware download information. US 9570159 (WAKCHAURE et al) teaching tangible machine readable storage medium comprising instructions that, when executed, cause one or more processors to at least: send, upon detection of a power loss event, from a processor of the solid state drive, a command to abort an ongoing write operation of an aborted memory cell; in response to an indication that the ongoing write operation was aborted, recover the data to be written to the aborted memory cells. US 20180158535 KIM teaching processor to execute machine-readable instructions to control all operations of the controller, the instructions being firmware or software including test code for driving the controller. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIM VO can be reached at (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138 Application/Control Number: 18/128,867 Page 2 Art Unit: 2138 Application/Control Number: 18/128,867 Page 3 Art Unit: 2138 Application/Control Number: 18/128,867 Page 4 Art Unit: 2138 Application/Control Number: 18/128,867 Page 5 Art Unit: 2138 Application/Control Number: 18/128,867 Page 6 Art Unit: 2138 Application/Control Number: 18/128,867 Page 8 Art Unit: 2138 Application/Control Number: 18/128,867 Page 9 Art Unit: 2138 Application/Control Number: 18/128,867 Page 10 Art Unit: 2138
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