Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the Applicant’s response filed August 19, 2026.
This application has been examined. Claims 1, 6, 9, 14, 17-20, 22-25, 27, 30 have been amended. Claims 2-4, 7-8, 10-12, 15-16, 26, 28, 31-32 have not been amended and stand as previously presented. Claims 5, 13, 21, 29 have been canceled. Claims 1-4, 6-12, 14-20, 22-28, 30-32 are pending in the application, and Claims 1-4, 6-12, 14-20, 22-28, 30-32 stand rejected.
Specification
The objection to the title of the invention set forth in the prior Office Action is acknowledged as addressed by Applicant's amendment of the title in the Amendment filed August 19, 2026. Subject to confirmation that the substitute title is descriptive of the claimed invention (see header table above), the objection to the specification is withdrawn.
Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-12, 14-20, 22-28, 30-32 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Man et al. (“Man”) (US No. 9,063,727) in view of Blaine et al. (“Blaine” (US Pub No. 2018/0088985)
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Blaine and Man references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
The rejection below incorporates and updates the claim mapping set forth in the prior Office Action (mailed 05/20/2026) to reflect the current claim amendments and cancellations. No new reference, and no rejection of any claim on a new ground not necessitated by amendment, is set forth herein.
In regard to claim 1, 9, 17, 25, Man discloses a method, a machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations by processor comprising: a plurality of cores to execute instructions (as shown in Fig. 5, which is reproduced below for ease of reference and convenience, Man discloses multi-core processor with core domain 125 containing one or more processor cores. See col. 7:58 through col. 8:33: a processor includes a first domain with at least one core to execute instructions. The processor 400 may be a multicore processor including a plurality of cores 410.sub.a-410.sub.n. In one embodiment, each such core may be of an independent power domain and can be configured to operate at an independent voltage and/or frequency, and to enter a turbo frequency mode when available headroom exists);
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and a power management unit to control power consumption of each core of the plurality of cores (in Man, power Control Unit (PCU) 140 that performs power management operations, including thermal control logic 145. See col. 3:26-37: a power control unit (PCU) 140 which in the embodiment shown may include a thermal control logic 145. In general, PCU 140 may be configured with various circuitry, logic and so forth to perform power management operations for the processor);
a frequency limiter to determine a maximum frequency of the core based, at least in part, on a measured temperature (in Man, thermal control logic monitors temperature and limits/reduces frequency to prevent exceeding thermal throttle point or maximum junction temperature Tj. See col. 3:38-58: a processor having multiple independent domains can be controlled to prevent a temperature of any of the domains from exceeding a maximum junction temperature. These sensors can communicate information to a comparison logic 166 that further receives one or more thermal throttling thresholds. Note that the thermal thresholds, which may be stored in a threshold storage 165);
and limit resolution circuitry to determine a first frequency of the core in accordance with the frequency ramp rate limit and the maximum frequency (in Man, PCU / thermal control logic resolves thermal constraints with performance states to select final operating frequency. See col. 3:47-64:thermal logic of a PCU, in one embodiment, and can be performed on an iterative basis, namely once per predetermined interval (which may be approximately 1 millisecond (ms) in one embodiment). In general, the method may be performed based on a temperature of multiple domains of a processor. Such temperature information can be obtained directly from the domains, e.g., from a thermal sensor associated with each domain that is coupled to the PCU, e.g., via a push bus or other link. Or, temperature information can be determined within the PCU, e.g., based on thermal sensor data obtained from these thermal sensors);
further based on one or more of power budget constraints, thermal limits, and one or more power/performance request (in Man, thermal control logic further discloses that the resolved operating frequency of a domain is constrained so as not to exceed a maximum junction temperature (i.e., a thermal limit), based on temperature information obtained from a thermal sensor associated with each domain and compared, within the PCU, against one or more thermal throttling thresholds (col. 3:38-58). Accordingly, Man alone discloses determining the first frequency further based on a thermal limit, satisfying that alternative of the limitation reciting that the first frequency is determined “in accordance with the frequency ramp rate limit and the maximum frequency and further based on one or more of power budget constraints, thermal limits, and one or more power/performance requests”).
But Man does not expressly disclose a frequency ramp governor to determine a frequency ramp rate limit for at least one core of the plurality of cores based, at least in part, on a present frequency of the core. In the same field of endeavor, Blaine discloses a frequency ramp governor to determine a frequency ramp rate limit for at least one core of the plurality of cores based, at least in part, on a present frequency of the core (as shown in Fig. 5, which is reproduced below for ease of reference and convenience, Man discloses performance controller / governor that dynamically determines ramp behavior and control effort based on current frequency/state of the core. See ¶ 22-24: the performance controller can enable or disable processor cores based on the thread scheduler dispatch latency, so that if the scheduler is reporting that the latency between receiving a thread dispatch request and dispatching the thread to a processor core is particularly high (e.g., exceeds a target latency), the performance controller will increase the number of recommended processor cores. The scheduler can then begin to schedule threads to the additional processors that are made available by the performance controller).
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Additionally, and independently, Blaine discloses, at ¶ 51, that an indication that a thread is performance-core eligible operates as a hint to scheduler 412, which may be conditionally executed based on several factors including the degree of contention for an active performance microprocessor core (e.g., microprocessor core 432A); performance controller 416 synchronizes performance-core-eligibility recommendations with recommended-cores bit field 308, such that when a thread is hinted as performance-core eligible, at least one performance microprocessor core is recommended. This discloses determining the first frequency further based on a power/performance request - an additional, independently sufficient basis for satisfying the disjunctive limitation now recited in claims 1, 9, 17, and 25.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Man to include a sophisticated dynamic ramp governor that intelligently adjusts how quickly frequency can change (ramp rate) depending on the current operating frequency, as taught by Blaine, in order to prevents sudden jumps that could cause voltage droop, instability and/or unnecessary power spikes.
In regard to claims 2, 10,18, 26, Blaine discloses wherein the frequency ramp rate limit comprises a first (lower) ramp rate if present frequency is above a threshold and a second (higher) ramp rate if below the threshold (in Blaine, different control effort/ramp aggressiveness based on current frequency/load level more conservative at high frequency. See ¶ 22-24).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Man to include a sophisticated dynamic ramp governor that intelligently adjusts how quickly frequency can change (ramp rate) depending on the current operating frequency, as taught by Blaine, in order to prevent overshoot and instability at high frequencies.
In regard to claims 3, 11, 19, 27, Blaine discloses wherein the frequency ramp rate governor ... uses frequency ramp rate limit data comprising a plurality of frequency ranges mapped to corresponding ramp rate limits (in Blaine, range-based or state-based mapping for different control/ramp rates. See ¶ 55).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Man to include a sophisticated dynamic ramp governor that intelligently adjusts how quickly frequency can change (ramp rate) depending on the current operating frequency, as taught by Blaine, in order to provide the efficient lookup implementation of dynamic behavior.
In regard to claims 4, 12, 20, Man discloses wherein the frequency limiter… uses temperature-frequency data comprising a plurality of temperature ranges mapped to frequency downstep values, ... subtracting the downstep value from a maximum supported frequency (in Man, thermal throttle points and thresholds; temperature compared to configurable thresholds, frequency reduction/derating from max frequency. See col. 3:38-52, col. 7:19-35).
In regard to claims 6, 14, 22, 30 (amended solely to update the claim dependency from canceled claims 5, 13, 21, and 29, respectively, to claims 1, 9, 17, and 25, respectively; no new limitation is introduced by this amendment), Blaine discloses work point determination circuitry to determine voltage ... based on frequency-voltage data ... further in accordance with a maximum current constraint (scheduler hints and performance requests. See ¶ 51: the indication that a thread is performance core eligible is a hint to the scheduler 412, which may be conditionally executed based on several factors including the degree of contention for an active performance microprocessor core (e.g., microprocessor core 432A). In one embodiment, the performance controller 416 synchronizes performance core eligibility recommendations with the recommended cores bit field 308, such that when a thread is hinted as performance core eligible, at least one performance microprocessor core is recommended. For example and in one embodiment, at least one performance microprocessor core (e.g., performance microprocessor core 432A) is recommended if any one thread is hinted as performance core eligible in the performance controller thread information 408 provided to the scheduler 412).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Man to include a sophisticated dynamic ramp governor that intelligently adjusts how quickly frequency can change (ramp rate) depending on the current operating frequency, as taught by Blaine, in order to provide comprehensive constraint resolution.
In regard to claims 7, 15, 23, 31, Blaine discloses wherein the work point determination circuitry is to determine the voltage further in accordance with a maximum current constraint (¶ 51). Same obviousness as claim 1, 9, 17, 25.
In regard to claims 8, 16, 24, 32, Blaine discloses thermal spike detection and control circuitry to detect a thermal spike event based on a temperature slope and to responsively trigger a hardware-based throttling response (in Blaine, rapid response to changing conditions. See ¶ 22-24).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Man to include a sophisticated dynamic ramp governor that intelligently adjusts how quickly frequency can change (ramp rate) depending on the current operating frequency, as taught by Blaine, in order to provide fast hardware reaction to sudden temperature increases (slope/rate of change).
In regard to claim 28, Man discloses that each core may be configured to operate at an independent voltage and/or frequency (col. 7:58-8:33), consistent with a known frequency-voltage relationship (see also claims 6, 14, 22, and 30, below) whereby a temperature-based limit placed on frequency corresponds to an analogous temperature-based limit on the voltage at which the core may be operated.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply Man's temperature-based frequency-downstep scheme (col. 3:38-52) in an analogous manner to determine a maximum voltage of the core based on temperature-voltage data comprising a plurality of temperature ranges mapped to a corresponding plurality of maximum voltage values, in order to prevent a core operated according to a determined voltage/frequency work point from exceeding its thermal limits, applying a known technique (temperature-indexed derating) to a known device (a voltage limiter) to yield the predictable result of a temperature-limited maximum voltage.
Examiner's note:
Applicant is reminded that the Examiner has cited particular columns, line numbers, and paragraphs in the applied references for the convenience of the Applicant; other passages and figures of Man and Blaine may apply as well, and Applicant is encouraged to consider the references in their entirety.
Response to Arguments
Applicant's arguments filed 08/19/2026 have been fully considered but are not persuasive.
Claim 1: Applicant argues that Blaine paragraphs 22-24 do not use the terms “ramp,” “ramp rate,” “slew rate,” or “current operating frequency,” and that the Office Action's characterization of Blaine as teaching “a sophisticated dynamic ramp governor that intelligently adjusts how quickly frequency can change (ramp rate) depending on the current operating frequency” is unsupported by the cited disclosure. This argument is not persuasive. It is well settled that a prior art reference need not use the same terminology as the claims, nor expressly articulate the reason a proposed modification would have been obvious, in order to support a rejection; the relevant inquiry is what the reference would have suggested to one of ordinary skill in the art. See In re Bode, 550 F.2d 656 (CCPA 1977); KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). Blaine's performance controller 416 conditions its control effort (e.g., the number of processor cores recommended or enabled) dynamically on a present, real-time operating condition of the system - namely, thread scheduler dispatch latency and the degree of contention for an active core (¶ 22-24) - rather than applying a static control policy. This disclosure evidences that state-dependent (i.e., present-condition-dependent) control of a core performance parameter, of which frequency ramp-rate control is one well-known species, was known in the art. The articulated motivation to combine (preventing sudden frequency jumps that could otherwise cause voltage droop, instability, or unnecessary power spikes) reflects a well-recognized concern in multi-core processor power management and does not depend on Blaine using the specific words “ramp” or “slew rate.”
Applicant next argues that amended claim 1 requires “a highly specific relationship” among the frequency ramp governor, the frequency limiter, and the limit resolution circuitry, and that Blaine does not disclose “a frequency-selection engine that receives competing constraints and resolves those constraints into a selected operating frequency,” nor “power-budget constraints used in determining a core operating frequency” or “thermal limits being provided to limit-resolution circuitry.” This argument is not persuasive because it is not commensurate in scope with what is actually recited in claim 1. Claim 1 does not recite a “frequency-selection engine,” nor does it require that the limit resolution circuitry “receive” multiple “competing constraints” and “resolve” them as a single unified operation; claim 1 recites only that the first frequency is determined “in accordance with the frequency ramp rate limit and the maximum frequency and further based on one or more of power budget constraints, thermal limits, and one or more power/performance requests.” Arguments premised on limitations that are not actually recited in the claims are not persuasive to overcome a rejection based on the claim as written. See In re Self, 671 F.2d 1344, 1348 (CCPA 1982).
Further, because the added limitation is expressly disjunctive (“one or more of” A, B, and C), it is satisfied upon a showing that the prior art teaches any single one of the three recited alternatives; Applicant is not required to show, and the rejection does not require, that the prior art disclose all three of power budget constraints, thermal limits, and power/performance requests. Applicant's arguments addressing only the “power budget constraints” and “thermal limits” alternatives, without addressing the “power/performance requests” alternative on which the Office Action also relies, do not rebut the rejection. In any event, both alternatives relied upon in the rejection remain fully supported by disclosure already of record:
(i) Thermal limits - Man's thermal control logic 145, already applied under the base “frequency limiter ... based, at least in part, on a measured temperature” limitation of claim 1, discloses that the resolved operating frequency of a domain is constrained so that the domain's temperature does not exceed a maximum junction temperature Tj, using comparison logic 166 that receives one or more thermal throttling thresholds from a threshold storage 165 (Man, col. 3:38-58). This is itself a disclosure of determining the first frequency “further based on” a thermal limit, and requires no reliance on any reference or passage not already of record.
(ii) Power/performance requests - Blaine ¶ 51, already cited in the prior Office Action, discloses that an indication that a thread is “performance core eligible” functions as a hint/request communicated to scheduler 412, and that performance controller 416 synchronizes performance-core-eligibility recommendations with a recommended-cores bit field 308 so that at least one performance-eligible core (e.g., core 432A) is recommended whenever such a request is present. This request-driven allocation of processing/performance resources reasonably discloses a “power/performance request” that is factored into the system's resource-affecting decision-making, satisfying that alternative of the disjunctive limitation.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine Man's thermal-limit-constrained frequency resolution with Blaine's request-responsive resource allocation, for the reasons already of record (see prior Office Action at pp. 4-8) and as reinforced above, in order to provide comprehensive constraint resolution that is responsive to real-time thermal conditions and performance demands. For at least these reasons, Applicant's arguments do not overcome the rejection of independent claim 1.
Claims 9, 17, and 25: Applicant relies on the arguments presented for claim 1 as applicable to claims 9, 17, and 25, which recite commensurate limitations. These arguments are not persuasive for the same reasons discussed above with respect to claim 1.
Dependent Claims: Applicant does not present separate arguments for patentability of claims 2-4, 6-8, 10-12, 14-16, 18-20, 22-24, and 26-32 apart from their dependency, directly or indirectly, from claims 1, 9, 17, and 25. Because claims 1, 9, 17, and 25 remain properly rejected for the reasons discussed above, the dependent claims fall with the claims from which they depend. See In re Fine, 837 F.2d 1071, 1076 (Fed. Cir. 1988).
Conclusion
Claims 1-4, 6-12, 14-20, 22-28, 30-32 are rejected. Claims 5, 13, 21, 29 are cancelled.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 C.F.R. § 1.136(a).
A SHORTENED STATUTORY PERIOD FOR RESPONSE TO THIS FINAL ACTION IS SET TO EXPIRE THREE MONTHS FROM THE DATE OF THIS ACTION. IN THE EVENT A FIRST RESPONSE IS FILED WITHIN TWO MONTHS OF THE MAILING DATE OF THIS FINAL ACTION AND THE ADVISORY ACTION IS NOT MAILED UNTIL AFTER THE END OF THE THREE-MONTH SHORTENED STATUTORY PERIOD, THEN THE SHORTENED STATUTORY PERIOD WILL EXPIRE ON THE DATE THE ADVISORY ACTION IS MAILED, AND ANY EXTENSION FEE PURSUANT TO 37 C.F.R. § 1.136(a) WILL BE CALCULATED FROM THE MAILING DATE OF THE ADVISORY ACTION. IN NO EVENT WILL THE STATUTORY PERIOD FOR RESPONSE EXPIRE LATER THAN SIX MONTHS FROM THE DATE OF THIS FINAL ACTION.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
