CTNF 18/128,977 CTNF 79409 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are presented for the examination. 07-04 AIA 07-04-01 § 101 2. 35 U.S.C. 101 reads as follows Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 2, 3, 9, 10, 16, 17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. As to Claims 2, 3, 9, 10, 16, 17, have been rejected under 35 USC 101 for abstract idea without significantly more. Under Step 2A, Prong 1, the “selected from the group”, “ indicate a priority mailbox to receive a thread-specific parking hint from a software or firmware component”, “ the thread-specific parking hint to identify” recite a mental process since “select”, “ indicate”, “ identify” are functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion. Under Prong 2, the additional element “ power management circuitry to associate a plurality of performance values and a plurality of efficiency values with the plurality of cores, wherein each core is to be associated with at least one performance value and at least one efficiency value, the plurality of performance values and the plurality of efficiency values to be used by a scheduler for scheduling threads on the plurality of cores; and core configuration circuitry coupled to or integral to the power management circuitry to resolve a plurality of configuration hints into a consolidated hint for updating one or more performance values of the plurality of performance values and/or one or more efficiency values of the plurality of efficiency values.” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f). Under Step 2B, the additional elements “power management circuitry to associate a plurality of performance values and a plurality of efficiency values with the plurality of cores, wherein each core is to be associated with at least one performance value and at least one efficiency value, the plurality of performance values and the plurality of efficiency values to be used by a scheduler for scheduling threads on the plurality of cores”, - this generally have been a mental process although the power management circuitry could be a generic computer component if the spec describes it as actual computer hardware in computer hardware. “ core configuration circuitry coupled to or integral to the power management circuitry to resolve a plurality of configuration hints into a consolidated hint for updating one or more performance values of the plurality of performance values and/or one or more efficiency values of the plurality of efficiency values” - this is mere instructions to apply the mental process under mpep 2106.05(f), amounts to merely generally, amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application. See MPEP 2106.05(d). Thus, the claim is not patent eligible. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. 6. Claims 15-20 are rejected under 35 U.S.C. 101 because as non-statutory because it is not tangibly embodied. 7. Claim 15 recites “ machine-readable medium” in the preamble. However, the specification does not define this medium to be hardware or memory. Therefore, claim 15 is non-statutory. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 8. Claim (s) 1, 9, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow ( US 20100153954 A1) in view of Kursun (US 20110271161 A1) . As to claim 1 , Morrow teaches A processor, comprising: a plurality of cores; power management circuitry to associate a plurality of performance values and a plurality of efficiency values with the plurality of cores, wherein each core is to be associated with at least one performance value and at least one efficiency value ( The second sensor circuit 430 includes a ring oscillator 434 , a frequency counter 436, an interface port 438, and an output 440. The ring oscillator 434 may be constructed with transistors used in the controllable power domain it is associated with to determine the leakage current for the associated controllable power domain , para[0033], ln 1-8/ core-A may be manufactured primarily with a low voltage threshold (lo-Vt) transistor process to achieve high performance, but at a cost of increased leakage current. Core-B may be manufactured primarily with a high threshold (hi-Vt) transistor process to achieve good performance with low leakage curren t. Also, either of the two cores may be manufactured with a mix of hi-Vt and lo-Vt transistors, using the lo-Vt transistors in timing critical path circuits , para[0030], ln 2-12/ in a core constructed with a combination of low threshold voltage transistors and high threshold voltage transistors, two ring oscillators may be utilized. One ring oscillator is constructed with low threshold voltage transistors and another ring oscillator is constructed with high threshold voltage transistors. Both ring oscillators would be measured and read providing leakage current information for the associated core. In another embodiment, the design of the second sensor circuit 430 may generally be duplicated, but constructed with a different set of transistors than was utilized for determining leakage current information , and used to gauge process variations, para[0034]) the plurality of performance values and the plurality of efficiency values to be used by a scheduler for scheduling threads on the plurality of cores( A thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage, para[0008], ln 5-10/ thread scheduling in an asymmetric multiprocessor system based on leakage current and dynamic power to achieve required performance at a low power expenditure , para[0001]/ Power points 212 and 214 are the static leakage power for core-A and core-B, respectively, at the PVT.sub.L environment. In particular, core-A has a higher leakage power than core-B as indicated by power point 212 but uses less dynamic power per operation at high frequencies above frequency F.sub.1 than core-B. Core-B has a lower leakage power as indicated by power point 214 and is more efficient at lower frequencies below F.sub.1 as compared to core-A. The crossover point (P.sub.1, F.sub.1) 220 represents a crossover decision point to be considered for allocating tasks to core-A or to core-B depending upon operating frequency and PVT environment for the dual cores. , para[0028], ln 7-21/ Power points 212 and 214 are the static leakage power for core-A and core-B, respectively, at the PVT.sub.L environment. In particular, core-A has a higher leakage power than core-B as indicated by power point 212 but uses less dynamic power per operation at high frequencies above frequency F.sub.1 than core-B. Core-B has a lower leakage power as indicated by power point 214 and is more efficient at lower frequencies below F.sub.1 as compared to core-A, para[0028], ln 8-17/ For this particular task, the core-A power comprises the leakage power (P.sub.L,A,L) plus the dynamic power (P.sub.D,A,L) which equals, for this example, 25 mW+35 mW=60 mW. The core-B power equals P.sub.L,B,L+P.sub.D,B,L=10 mW+40 mW=50 mW. Based on this analysis, this particular task should be allocated to core-B, even though it is above the crossover point 720 and has a dynamic power component (40 mW) that is higher than core-A's dynamic power (35 mW). The leakage power for core-A at point 712 makes a significant power contribution in the determination of where this particular task is to be assigned, para[0045],ln 10-21). Kursun teaches core configuration circuitry coupled to or integral to the power management circuitry to resolve a plurality of configuration hints into a consolidated hint for updating one or more performance values of the plurality of performance values and/or one or more efficiency values of the plurality of efficiency values( As shown in FIG. 2A, the multi-core processor chip 200 includes a plurality of computational cores, or processors , 210-224 (hereafter referred to as the cores), on-chip sensors/hardware counters 230, storage structures 232-239, 242-248 (both within and outside of the core for which the illustrative embodiments are also applicable), one or more on-chip management units 240 , para[0033], ln 3-12/ on- chip management units that control the operation of the cores and other chip resources so as to achieve a desired operation within an acceptable operational range. Alternatively, this operation may be performed, at least partially, on an external data processing device, for example, that takes the baseline chip characteristic map information and updated chip characteristic map information from the chip and performs the other operations to determine how to adjust the operation of the chip, if at all. The operation may be performed such that chip level optimization may be achieved so as to maximize performance, minimize temperature, minimize power consumption, and the lik e, para[0061], ln 7-23 / FIG. 5 is a flowchart outlining an operation for performing dynamic performance and energy efficiency adjustments based on the chip characterization information in the on-chip characterization map device. This operation may again be performed by the on -chip characterization map device in conjunction with on-chip management units that control the operation of the cores and other chip resources so as to achieve a desired operation within an acceptable operational range. A lternatively, this operation may be performed, at least partially, on an external data processing device, for example, that takes the baseline chip characteristic map information and updated chip characteristic map information from the chip and performs the other operations to determine how to adjust the operation of the chip, if at all. The operation may be performed such that chip level optimization may be achieved so as to maximize performance, minimize temperature, minimize power consumption, and the like. Alternatively, the operation may be performed to optimize the operation of individual devices on the chip , Based on the selected performance and energy mode of operation, various corresponding optimization criteria are determined for the operational characteristics of the chip/cores (step 530). These criteria may be power, performance, temperature, and/or reliability criteria for achieving the goals of the selected performance and energy mode of operation. Based on these criteria and the operational characteristics of the cores and/or chip as a whole, determinations are made as to the modifications that need to be made to the operation of the cores and/or chip (step 540). Based on these determined modifications, control signals are sent to the management units of the chip to achieve the modifications (step 550). The operation then terminates , para[0061] to para[0063]/ In another example if the inherent static power dissipation of one of the cores (e.g., core 2) is determined to be lower than the rest of the cores, a high-power task can be assigned to this core. As a result, the power efficiency of the chip will be improved because of this assignment., para[0046], ln 22-27). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Morrow with Kursun because this provides profile for use in efficiency and performance control of the chip resources. As to claims 8, 15 , they are rejected for the same reason as to claim1 above. In additional, Morrow teaches machine-readable medium(computer readable storage medium, para[0054], ln 8-12) . 07-21-aia AIA 9. Claim (s) 2, 9, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow ( US 20100153954 A1 ) in view of Kursun (US 20110271161 A1 ) and further in view of Russell( US 20090187909 A1) . As to claim 2, Russell teaches the plurality of configuration hints comprise one or more different types of hints selected from the group comprising: core-specific parking hints, thread-specific parking hints, core consolidation hints, workload type (WLT) hints, SoC die biasing hints, and processor or system survivability hints( the affinity value increases as the percentage of information required by the thread and stored in the core's cache increases. In one embodiment, a thread's affinity value may be proportional to a number of cache lines used by that thread that still reside or are stored in the core's associated cache (e.g. L2 cache 40 for core 50). Note that a thread's affinity value is usually dynamic in nature since a thread's affinity for a core will decrease in time as the thread's cache lines are replaced or overwritten in the core's associated cache when the thread is not active, and other threads are utilizing the core's associated cache, para[0012], ln 6-17). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Morrow and Kursun with Russell to incorporate the above because this minimizes the number of active devices at the expense of performance and minimize power could be consumed than desired. As to claims 9, 16 , they are rejected for the same reason as to claim 2 above . 07-21-aia AIA 10. Claim (s) 3, 10, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow ( US 20100153954 A1 ) in view of Kursun (US 20110271161 A1 ) in view of Russell( US 20090187909 A1) and further in view of Zhang(US 20110099402 A1) . As to claim 3 , Russell teaches the thread-specific parking hint to identify one or more cores or logical processors associated with the one or more cores to be reserved for executing a particular thread or group of threads( uses "minimize power", "maximize performance", and "thread affinity" as three possible criteria to be used to select a core to execute a thread, para[0022], ln 2-6) for the same reason as to claim 2 above. Zhang teaches the power management circuitry is to indicate or configure a priority mailbox to receive a thread-specific parking hint from a software or firmware component( A global control 28 is bidirectionally coupled to both the system core 14 and the system interconnect 12. Relevant portions of the global control 28 illustrated in FIG. 1 include a thread priority register 38, a thread scheduler 40, an arbiter 42 and interconnect low power control circuitry 44. An output of the thread priority register 38 is coupled to an input of the thread scheduler 40 via a multiple bit conductor. An output of the thread scheduler 40 is connected to a first input of arbiter 42. An output of the interconnect low power control circuitry 44 is connected to a second input of arbiter 42. An input/output of arbiter 42 is connected to the system interconnect 12. An input/output of the interconnect low power control circuitry 44 is connected to the system interconnect 12, para[0011], ln 22-41). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Morrow and Kursun and Russell with Zhang to incorporate the above feature because this ensures that the amount of energy saved by entering low power mode exceeds the overhead energy expended in transitioning into and out of a low power mode. As to claims 10, 17, they are rejected for the same reason as to claim 3 above . 07-21-aia AIA 11. Claim (s) 4, 5, 11, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow ( US 20100153954 A1 ) in view of Kursun (US 20110271161 A1 ) and further in view of Yi( US 20230418664 A1) . As to claim 4, Yi teaches the plurality of cores include a plurality of relatively larger, relatively higher performance cores (P-cores) and a plurality of relatively smaller, relatively more efficient cores (E-cores)( The ranking or weight for the mapping of the assignment between core “c0” and thread class type 0 is shown as “eff_0.” This ranking “eff_0” indicates that the thread class type 0 is not preferably assigned to a low-power core, but rather, a high-performance core. Here, the low-power cores are indicated as “e” and “eff” for efficient cores, and the high-performance cores are indicated as “p” and “perf” for performance cores. The ranking or weight for the mapping of the assignment between core “c0” and thread class type 0 is also shown as “perf_3.” Here, the higher the numerical value, the stronger the preference for the assignment. Therefore, this ranking “perf_3” indicates that the thread class type 0 is strongly preferred to be assigned to a high-performance core such as core “c0.” Here, a ranking or weight of “0” indicates a strong avoidance to making the corresponding assignment between core and thread class type. Other value types, ranges, and indications for the rankings in table 230 are possible and contemplated, para[0036]). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Morrow and Kursun with Yi to incorporate the above feature because this provides hardware design of the first core emphasizes high performance (high throughput), which also increases power consumption. As to claims 11, 18 , they are rejected for the same reason as to claim 4 above. As to claim 5 , Yi teaches a first die comprising: a memory controller to couple the processor to a system memory; a plurality of fabric interconnects to couple to other dies; and at least one E-core of the plurality of E-cores; a second die comprising: a shared cache; the plurality of P-cores coupled to the shared cache; multiple E-cores of the plurality of E-cores coupled to the shared cache; and a plurality of fabric interconnects to couple the second die to the first die( para[0036]/para[0019] to para[0020]/ Fig.1) for the same reason as to claim 4 above . 07-21-aia AIA 12. Claim (s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Morrow ( US 20100153954 A1 ) in view of Kursun (US 20110271161 A1 ) in view of Yi( US 20230418664 A1) and further in view of Williamson(US 20160147290 A1) . As to claim 6 , Yi teaches the power management circuitry comprises a first power unit integral to the first die and a second power unit integral to the second die, wherein the second power unit is to send power management data related to the second die to the first power management unit( para[0019] to para[0020]) for the same reason as to claim 4 above. Williamson teaches the first power management unit is to send requests to the second power management unit related to power and performance states of the plurality of P-cores and the multiple E-cores( As the code being executed by a processor 32 A- 32 n changes and/or other system considerations warrant a change in the PState, the PState register 38 may be updated (e.g. by the OS). If the PState is changed from a current PState that is mapped to one of the cores 40 and 42 (the “active core”) to a new PState that is mapped to another one of the cores 40 and 42 (the “target core”), the cluster 30 may automatically, in hardware, transfer the processor context of the processor 32 A from the active core to the target core. The target core may be powered off at the time the PState is changed. The process of transferring the context may include powering on the target core, resetting and initializing the target core, transferring the processor context, and powering off the active core (making the target core the active core), para[0030], ln 1-17/ The context buffer 92 may be a first in, first out buffer (FIFO) to capture context state from one core to another. The context buffer 92 may provide elasticity, handle clock domain crossings, etc. In an embodiment, the context buffer 92 may be part of the processor power manager 36 and thus is shown in dotted lines in FIG. 8. The state machines 90 may also be implemented in the processor power manager 36 in another embodiment. In such embodiments, the processor power manager 36 may have access to the register state in the cores 40 and 42 , or may cause instructions to be executed to perform the register reads/writes to perform the transmission of the register states, para[0057]/ Each processor 32 A- 32 n may have its own independent PState, groups of processors 32 A- 32 n may share a PState, or the cluster 30 may have a shared PState for the processors 32 A- 32 n , in various embodiments. Processor 32 A is shown in more detail in FIG. 1 to include at least two processor cores, a performance core (PCore) 40 and an efficient core (ECore) 42 . Other embodiments may include additional cores. Each core 40 and 42 is coupled to a power supply rail (V.sub.P) through respective power switches 44 and 46 . Thus, each core 40 and 42 may be independently powered up or down. Other processors, such as the processor 32 n , may be similar to the processor 32 A, para[0023], ln 9-21). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Morrow and Kursun and Yi with Williamson because this limits certain features to one core or, at least, to less than all the cores may provide an area efficient implementation by eliminating duplicative circuitry in the cores to process the same instruction types . 07-21-aia AIA 13. Claim (s) 7, 12, 13, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow ( US 20100153954 A1 ) in view of Kursun (US 20110271161 A1 ) in view of Yi( US 20230418664 A1) in view of Williamson(US 20160147290 A1) in view of Matveev( US 20180232540 A1) . As to claim 7, Matveev teaches the WLT hints include a first WLT hint indicating a high power or high performance workload, wherein responsive to the first WLT hint, the dynamic core configuration hardware logic is to generate the consolidated hint to configure the one or more performance values and the one or more efficiency values to restrict scheduling of the high power or high performance workload to one or more P-cores of the plurality of P- cores( Such mapping can be implemented by setting an affinity property of the communication thread. For example, ‘weak affinity’ can be set for a communication thread and indicate that the communication thread is allowed to execute on any CPU core unless the CPU core for executing the thread is separately assigned. For example, the electronic device includes two different CPU core clusters, a big cluster includes high-performance CPU cores, and a little cluster includes power-efficient low-performance CPU cores which are not highly productive. In this case, when the affinity property of the communication thread is set to assign the communication thread to the big-cluster CPU core, the corresponding communication thread executes on the high-performance CPU core. When a communication thread is assigned to the little-cluster CPU core, the corresponding communication thread executes on the low-performance CPU core. Thus, balance between the performance and the power consumption can be achieved using the affinity property., para[0074], ln 1-21/ an affinity property of a corresponding thread can be used. The affinity property can be set to, for example, map threads to different CPU cores. For example, ‘weak affinity’ can be set for a particular thread and indicate that the corresponding thread is allowed to execute on any CPU core unless the CPU core for executing the thread is separately assigned. Also, the thread can execute only on a CPU core assigned according to the set affinity property. For example, when the electronic device includes two or more CPU cores having different performances, thread affinity information can be set to assign any one of a high-performance CPU core and a low-performance CPU core, para[0059], ln 5-18). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Morro, Kursun, Yi and Williamson with Matveev because this limits certain features to one core or, at least, to less than all the cores may supports the multi-threading and thus supports smooth execution of the computationally intensive applications as various action games and multimedia apps and enables an idle CPU core nor request the rich OS to enable the idle CPU core, in order to optimize the secure OS operation. As to claim 12 , it is rejected for the same reason as to claim 7 above. As to claim 13 , Matveev teaches the WLT hints include a second WLT hint indicating an idle or low power workload, the method further comprising: generating the consolidated hint responsive to the second WLT hint to configure the one or more performance values and the one or more efficiency values to restrict scheduling of the idle or low power workload to the at least one E-core of the plurality of E-cores of the first die( para[0074], ln 1-21/ para[0059], ln 5-18) for the same reason as to claim 7 above. As to claims 19, 20 , they are rejected for the same reasons as to claims 7, 13 above . 07-21-aia AIA 14. Claim (s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Morrow ( US 20100153954 A1 ) in view of Kursun (US 20110271161 A1 ) in view of Yi( US 20230418664 A1) in view of Williamson(US 20160147290 A1) in view of Matveev( US 20180232540 A1) and further in view of Wang( WO 2015089780 A1) . As to claim 14 , Wang teaches sorting the plurality of cores responsive to the first WLT hint, and based on corresponding performance values to identify cores with the highest performance values for scheduling; or sorting the plurality of cores responsive to the second WLT hint, and based on corresponding efficiency values to identify cores of the plurality of cores with the highest efficiency values for scheduling( configured to determine a kernel sorting order corresponding to the target parameter category according to a correspondence between a preset parameter category and a kernel sorting order, where the kernel sorting order is higher according to the target performance average Sorting the plurality of cores in a low order; the second kernel determining subunits are configured to determine a target core having the highest target performance average according to the kernel sorting order, sec: a kernel performance determining unit, ln 1-10). It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Morrow, Kursun, Yi, Williamson and Matveev with Wang because this increases the speed of the target application process and improves the running speed of the target application process Conclusion US 20100153954 A1 teaches multiple ring oscillators may be utilized based on the type of transistors used in a core. For example, in a core constructed with a combination of low threshold voltage transistors and high threshold voltage transistors, two ring oscillators may be utilized. One ring oscillator is constructed with low threshold voltage transistors and another ring oscillator is constructed with high threshold voltage transistors. Adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described. US 20090055826 A1 teaches A high-speed control circuit controls high-speed operations of at least one of the processor core and the peripheral device in response to the selection signal, and a low-speed and low-power control circuit controls low-speed and low-power operations of at least one of the processor core and the peripheral device in response to the selection signal. frequency for each of the plurality of processor cores. US 20140282565 A1 teaches shows a process for scheduling threads on a processor having both "out-of-order" core(s) and "non-out-of-order" core(s). A first thread is executing on an out-of-order core 401 and a second thread is executing on a non out-of-order core 402. US 20210064426 A1 teaches of a scheduling method in accordance with an embodiment. More specifically, scheduling method 1600 may be performed by an OS to schedule workloads on a heterogeneous SoC that includes cores having different capabilities. US 20160239065 A1 teaches threads to be executed in the next operation interval may be scheduled/rescheduled to the reduced number of cores. For example, threads currently executing on a core to be powered down may be rescheduled to cores that are to remain powered on. This is the case as in various embodiments, the cores may be multithreaded such that multiple threads can concurrently execute on a single core/In addition to internal power management circuitry and functionality within SoC 1310 , a PMIC 1380 is coupled to SoC 1310 to provide platform-based power management, e.g., based on whether the system is powered by a battery 1390 or AC power via an AC adapter 1395 . In addition to this power source-based power management, PMIC 1380 may further perform platform power management activities based on environmental and usage conditions. Still further, PMIC 1380 may communicate control and status information to SoC 1310 to cause various power management actions within SoC 1310 . CN 115617470 A teaches PCU provides signal to the operating system (or other suitable software process executed by the processor) prompting the core included in the thread scheduling, or omitted from the thread scheduling. Based on the prompt, the operating system (or other such execution process) conditionally adapts the thread scheduling (e.g., to facilitate the transition of the processor to the higher- efficiency mode of operation). US 20090187909 teaches A1for monitoring performance of the apparatus and for monitoring power usage of the apparatus; select circuitry for example: (62) for selecting one or more of the plurality of processors to execute the thread based on a selection criteria, said selection criteria comprising the affinity for the thread , a performance of the apparatus, and a power usage of the apparatus US 20230168898 teaches A1By breaking up a thread into two or more partitions, the partitions can be scheduled across the cores according to the complexity of the partitions and the configurations of the cores to reduce the amount of time needed to complete the threads and increase the efficiency of the execution by ensuring that cores are not idle while other cores are working. US 10437313 B2 teaches FIG. 2 is a block diagram of an efficiency and performance control system 200 , according to an embodiment. The efficiency and performance control system 200 includes processing subsystem hardware 210 to execute tasks and a scheduler 212 to schedule tasks to execute on the processing subsystem hardware 210 . 214 . Any inquiry concerning this communication or earlier communications from the examiner should be directed to LECHI TRUONG whose telephone number is (571)272-3767. The examiner can normally be reached 10-8 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Young Kevin can be reached on (571)270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LECHI TRUONG/ Primary Examiner, Art Unit 2194 Application/Control Number: 18/128,977 Page 2 Art Unit: 2194 Application/Control Number: 18/128,977 Page 3 Art Unit: 2194 Application/Control Number: 18/128,977 Page 4 Art Unit: 2194 Application/Control Number: 18/128,977 Page 5 Art Unit: 2194 Application/Control Number: 18/128,977 Page 6 Art Unit: 2194 Application/Control Number: 18/128,977 Page 7 Art Unit: 2194 Application/Control Number: 18/128,977 Page 8 Art Unit: 2194 Application/Control Number: 18/128,977 Page 9 Art Unit: 2194 Application/Control Number: 18/128,977 Page 10 Art Unit: 2194 Application/Control Number: 18/128,977 Page 11 Art Unit: 2194 Application/Control Number: 18/128,977 Page 12 Art Unit: 2194 Application/Control Number: 18/128,977 Page 13 Art Unit: 2194 Application/Control Number: 18/128,977 Page 14 Art Unit: 2194 Application/Control Number: 18/128,977 Page 15 Art Unit: 2194 Application/Control Number: 18/128,977 Page 16 Art Unit: 2194 Application/Control Number: 18/128,977 Page 17 Art Unit: 2194 Application/Control Number: 18/128,977 Page 18 Art Unit: 2194 Application/Control Number: 18/128,977 Page 19 Art Unit: 2194 Application/Control Number: 18/128,977 Page 20 Art Unit: 2194
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