DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention group I, species 1, drawn to a device shown in Fig. 1 in the reply filed on 06/17/2026 is acknowledged.
Response to Amendment
Applicant’s amendment dated 06/17/2026, in which claims 3-4, 7, 10-18 were withdrawn, has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. As known in the art, when the semiconductor die is coupled to the substrate using solder balls (flip chip bonding), an active surface facing toward the substrate. When semiconductor die is coupled to the substrate using wire connection, the semiconductor die is coupled to the substrate with an active surface facing away from the substrate. All the drawings show the semiconductor die is coupled to the substrate using solder balls, thus all the drawings show an active surface facing toward the substrate. Therefore, the “the semiconductor die is coupled to the substrate with an active surface facing away from the substrate” of claim 8 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chakravorty et al. (US Pub. 20040238942) in view of Lee et al. (US Pub. 20130193948).
Regarding claim 1, Chakravorty et al. discloses in Fig. 3 an electronic device, comprising:
a semiconductor die [60] coupled to a substrate [200];
a plurality of metal-insulator-metal capacitor units [141, 151, 94, 93, 92]; and
a selected amount of the metal-insulator-metal capacitor units that are electrically coupled between a power connection on the substrate [200], and a power input on the semiconductor die [60].
Chakravorty et al. fails to disclose
a control circuit, when in operation, configured to dynamically control the selected amount of the metal-insulator-metal capacitor units.
Lee et al. discloses in Fig. 3, paragraph [0025], [0047], [0053]
a control circuit [321 and/or 322], when in operation, configured to dynamically control a selected amount of capacitor units [323].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lee et al. into the method of Chakravorty et al. to include a control circuit, when in operation, configured to dynamically control the selected amount of the metal-insulator-metal capacitor units. The ordinary artisan would have been motivated to modify Chakravorty et al. in the above manner for the purpose of dynamically controlling the capacitance of the selected amount of the metal-insulator-metal capacitor units based on an user selection and/or the environments and the requirements of the electronic device [paragraph [0025], [0047], [0053] of Lee et al.].
Regarding claim 2, Chakravorty et al. discloses in Fig. 3, paragraph [0036]-[0037] wherein the plurality of metal-insulator-metal capacitor units are located in an interposer [50] between the semiconductor die [60] and the substrate [200].
Regarding claim 9, Chakravorty et al. discloses in Fig. 3
wherein the semiconductor die [60] is coupled to the substrate [200] with an active surface facing towards the substrate [200][surface having solder ball formed thereon must be an active surface].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chakravorty et al. (US Pub. 20040238942) in view of Lee et al. (US Pub. 20130193948) as applied to claim 1 above and further in view of Li (US Pub. 20040027813).
Regarding claim 5, Chakravorty et al. and Lee et al. fails to disclose
a package capacitor coupled to the control circuit.
Li discloses in Fig. 1, Fig. 5, Fig. 10
the device further including a package capacitor [106 or 506] coupled to a plurality of metal-insulator-metal capacitor units.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Li into the method of Chakravorty et al. and Lee et al. to include a package capacitor coupled to the control circuit. The ordinary artisan would have been motivated to modify Chakravorty et al. and Lee et al. in the above manner for the purpose of providing an integrated circuit package having multiple surface mounted capacitors to increase the capacitors' effectiveness and provide the desired capacitance [paragraph [0004]-[0006] of Li].
The combination of Chakravorty et al. and Lee et al. suggests the control circuit coupled to the plurality of metal-insulator-metal capacitor units. Li suggests a package capacitor [106 or 506] coupled to a plurality of metal-insulator-metal capacitor units. Thus, the combination of Chakravorty et al. and Lee et al. and Li suggests “a package capacitor coupled to the control circuit.”
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chakravorty et al. (US Pub. 20040238942) in view of Lee et al. (US Pub. 20130193948) as applied to claim 1 above and further in view of Davis (US Pat. 8860508).
Regarding claim 6, Chakravorty et al. and Lee et al. fails to disclose
wherein the control circuit is located in the interposer.
Davis discloses in Fig. 7
the control circuit [200] is located in a same substrate [701] as the MIM capacitor [723]. Chakravorty et al. discloses the MIM capacitors are located in the interposer. Thus, the combination of Chakravorty et al. and Davis discloses the control circuit is located in the interposer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Davis into the method of Chakravorty et al. and Lee et al. to include wherein the control circuit is located in the interposer. The ordinary artisan would have been motivated to modify Chakravorty et al. and Lee et al. in the above manner for the purpose of providing suitable location of the control circuit.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chakravorty et al. (US Pub. 20040238942) in view of Lee et al. (US Pub. 20130193948) as applied to claim 1 above and further in view of Zhang et al. (US Pub. 20020171144).
Regarding claim 8, Chakravorty et al. and Lee et al. fails to disclose
wherein the semiconductor die is coupled to the substrate with an active surface facing away from the substrate.
Zhang et al. discloses in Fig. 7
wherein the semiconductor die [102] is coupled to the substrate [104] with an active surface facing away from the substrate [104].
Zhang further discloses in Fig. 9 and paragraph [0049] that alternatively, the semiconductor die [102] is coupled to the substrate [104] with an active surface facing toward the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Zhang et al. into the method of Chakravorty et al. and Lee et al. to include wherein the semiconductor die is coupled to the substrate with an active surface facing away from the substrate. The ordinary artisan would have been motivated to modify Chakravorty et al. and Lee et al. in the above manner for the purpose of providing suitable alternative method for coupling the semiconductor die to the substrate. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
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/SOPHIA T NGUYEN/ Primary Examiner, Art Unit 2893