DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-13, in the reply filed on 7/28/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US 2023/0066387.
Regarding claim 1, Chen discloses one or more apparatuses, comprising:
a first transistor comprising a first stack of nanosheets or nanowires through a first gate structure (PD-1, fig. 6A and paragraph 0050),
wherein a first sidewall of the first gate structure has a first slope (sidewall next to 350A, fig. 6A and paragraph 0051); and
a second transistor comprising a second stack of nanosheets or nanowires through a second gate structure (PG-1, fig. 6B and paragraph 0050), wherein a second sidewall of the second gate structure has a second slope that differs from the first slope (sidewall next to 350B, fig. 6B and paragraph 0051). Chen does not disclose wherein the difference is by at least five degrees, instead, Chen discloses different widths of the trenches to be etched which results in different sidewall taper profiles (paragraphs 0048-0051). Therefore, given Chen’s disclosure it would be deemed obvious to one of ordinary skill in the art at the time of filing to have a difference of at least five degrees given reasonable experimentation of Chen’s teachings.
Regarding claim 2, Chen’s disclosure is that of a die comprising an SRAM. For which more than one die is commonly used in an apparatus and since each die contains both transistor sidewall configurations the use of a first and second die would have been obvious to one of ordinary skill in the art at the time of filing.
Regarding claim 3, Chen discloses transistors of an SRAM configuration. Chend does not disclose wherein the first IC die has a first oscillator frequency greater than a second oscillator frequency of the second IC die. However, Chen does disclose a method of tuning threshold voltages of nanostructure based transistors by modifying the slopes of the gate sidewalls (paragraphs 0044-0052). As such, it would be deemed obvious to one of ordinary skill in the art at the time of filing to incorporate Chen’s teachings into a first and second die with different oscillator frequencies since such frequencies can be altered by altering the threshold voltages as taught by Chen.
Regarding claim 4, Chen further discloses wherein the first transistor has a first
threshold voltage less than a second threshold voltage of the second transistor (paragraphs 0044-0052).
Regarding claim 5, Chen disclose different slopes as mentioned above. Chen does not explicitly disclose wherein the first slope is within two degrees of vertical. However, two degrees of vertical would be deemed obvious to one of ordinary skill in the art at the time of filing given Chen’s disclosure for the reasons mentioned above.
Regarding claim 6, Chen further discloses wherein the first slope has a
depression angle from vertical of less than 0 degrees (Figs. 6A-B).
Regarding claim 7, Chen further discloses wherein a first nearest sidewall is a
first distance to the first sidewall, a second nearest sidewall is a second distance to the second sidewall, and the second distance is greater than the first distance (figs. 4, 6A-B, 7 and paragraphs 0044-0052).
Regarding claim 8, Chen discloses one or more apparatuses, comprising:
a first pair of adjacent transistors, comprising first and second stacks of nanosheets or nanowires through first and second gate structures and a first taper, wherein the first taper is a first difference between a first upper distance and a first lower distance between the first and second gate structures (PD-1, 350A, PD-1, fig. 6A and paragraphs 0044-0052); and
a second pair of adjacent transistors, comprising third and fourth stacks of nanosheets or nanowires through third and fourth gate structures and a second taper, wherein the second taper is a second difference between a second upper distance and a second lower distance between the second gate structures (PG-1, 350B, PU-2, fig. 6B and paragraphs 0044-0052). Chen does not disclose wherein the second taper is at least five times the first taper, instead, Chen discloses different widths of the trenches to be etched which results in different sidewall taper profiles (paragraphs 0048-0051). Therefore, given Chen’s disclosure it would be deemed obvious to one of ordinary skill in the art at the time of filing to have the second taper is at least five times the first taper given reasonable experimentation of Chen’s teachings.
Regarding claim 9, Chen’s disclosure is that of a die comprising an SRAM. For which more than one die is commonly used in an apparatus and since each die contains both transistor pairs, the use of a first and second die would have been obvious to one of ordinary skill in the art at the time of filing.
Regarding claim 10, Chen discloses transistors of an SRAM configuration. Chend does not disclose wherein the first IC die has a first oscillator frequency greater than a second oscillator frequency of the second IC die. However, Chen does disclose a method of tuning threshold voltages of nanostructure based transistors by modifying the slopes of the gate sidewalls (paragraphs 0044-0052). As such, it would be deemed obvious to one of ordinary skill in the art at the time of filing to incorporate Chen’s teachings into a first and second die with different oscillator frequencies since such frequencies can be altered by altering the threshold voltages as taught by Chen.
Regarding claim 11, Chen does not disclose wherein a first capacitance between
the first pair of adjacent transistors is less than a second capacitance between the second pair of adjacent transistors. However, the different widths of the gate cut trenches taught by Chen (paragraphs 0044-0052 and figs. 6A-B would inherently alter the capacitance of the transistor pair accordingly.
Regarding claim 12, Chen further discloses wherein a first pitch between the first
and second stacks is approximately equal to a second pitch between the third and fourth stacks (figs. 4, 6A-B).
Regarding claim 13, Chen discloses different tapers (paragraph 0051). Chen does not explicitly disclose wherein the first taper is less than 5nm. However, a taper of less than 5nm would be deemed obvious to one of ordinary skill in the art at the time of filing given Chen’s disclosure for the reasons mentioned above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2020/0006148 discloses a relevant transistor with a sloped gate sidewall.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 9/26/26
