Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 07/21/2026 amending claims has been acknowledged.
Currently, claims 1-20 are pending.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
It should be noted that applicant has not provided any substantiative arguments besides a general statement of “In view of the amendments to claims, the undersigned is of the position that the claims should be allowable over Pietambaram.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram et al., (hereinafter D1) (previously cited) in view of US Li et al., US 2023/0089494 A1 (hereinafter D2), DE ANGELS et al., US 2023/0142315 A1 (hereinafter D3) and further in view of Liff et al., US 11.756,943 B2 (hereinafetre D4).
As to claim 1, D1 discloses and shows in Figures, an integrated circuit (IC) device, comprising: a routing structure on a first side of a substrate (102), the routing structure comprising metallization features (Fig. 1A; ¶¶ 72–79, 92–95; substrate 102 having a glass core 104 and dielectric 124 with conductive traces 126 disposed on either side of the core. Those conductive traces are metallization features that form a routing structure on a side of the substrate);
a plurality of electronic IC (EIC) die over the first side of the substrate and over the routing structure, the plurality of EIC die electrically interconnected to each other by the routing structure ( ¶¶ 80–84, 87–95; EIC 138 coupled to substrate 102 and conductive traces/vias used to electrically couple package components. It teaches EIC placement over the substrate and routing structure);
a glass preform over the first side of the substrate and over the routing structure, wherein the glass preform comprises an optical waveguide herein (¶ 72–76, 92–95; a glass core/substrate and a waveguide 106 in the glass. This teaches glass plus embedded optical routing);
a photonic IC (PIC) die over the first side of the substrate and attached to a side of a first of the plurality of EIC die opposite of the routing structure, the PIC die optically coupled to a first end of the optical waveguide (¶¶ 80–84, 87–95; PIC 134 and EIC 138 on the same substrate with electrical coupling. It teaches PIC/EIC integration); and
a plurality of through vias extending through the substrate from the routing structure to a second side of the substrate (¶¶ 79–84, 90–95; TGVs 120 through the glass core and routing traces that electrically couple components on opposite sides of the substrate.).
D1 doesn’t explicitly disclose plurality/arrayed EIC-die arrangement, glass preform over the first side of the substrate and over the routing structure, wherein the glass preform, and the corresponding PIC optically coupled to a first end of the waveguide.
D2 and D4 related from the same field of endeavor teach multi-die photonic/electronic package architectures with multiple dies integrated in a common package. These disclosures support arranging multiple EIC dies over a routing structure and electrically interconnecting them in the package (D2: ¶¶ 54–56, 85–90, 110–116; D3: ¶¶ 54–68, 80–84, 87–91, 110–115)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the known D1 package to multiple EIC dies to increase I/O density and integrate more functions, as taught by the multi-die packaging of D2 and D4.
Still lacking the limitation such as glass preform over the first side of the substrate and over the routing structure, wherein the glass preform, and the corresponding PIC optically coupled to a first end of the waveguide.
D2 discloses optical packaging structures including glass blocks, fiber-array blocks, pass-through structures, and optical alignment components used adjacent to PICs, which reasonably corresponds to a discrete glass optical component or preform carrying an optical path. ( See ¶¶ 54-56, 85-90, 102-106, 110-116; teaches optical packaging components such as glass blocks, fiber-array blocks, and pass-through structures used adjacent to PICs; optical components aligned to PICs). D3 teaches edge coupling of a waveguide to a photonic chip and alignment at the waveguide end. D3 discloses a photonic chip having a cladding material and an edge coupler comprising a composite guiding structure of substantially parallel planar layers of optical guiding material, with a waveguide arranged to overlap the guiding structure and to couple at an edge of the chip, thereby teaching a glass-based optical structure carrying an optical waveguide and suitable for edge coupling to a PIC. (See ¶¶ 57-68, 74-88, 93-103; teaches a glass-based photonic chip having a waveguide/composite guiding structure and an edge-coupling architecture in glass).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to separate the optical routing function into a distinct glass optical component or preform because D2 and D3 both show that optical coupling can be implemented with glass-based optical bodies carrying waveguides. Combining that known optical body with D1’s glass substrate/routing architecture would predictably provide modular optical interconnect capability.
Further, D2 and D3 together supply the optical coupling relationship between a PIC and a waveguide end. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optically couple the PIC to the waveguide end to achieve low-loss optical input/output, which is the established purpose of optical package structures in D2 and edge-coupled photonic structures in D3.
As to claim 2, D1 discloses the IC device of claim 1 (¶¶ 80–84, 87–95; teaches PIC/EIC placement on the substrate ) but doesn’t explicitly disclose wherein the PIC die is in alignment with an end coupler of the optical waveguide that intersects an edge of the glass preform.
D3 expressly teaches edge-coupling of a waveguide to a photonic chip and the alignment of the waveguide end at the edge of the glass-based structure (¶¶ 62–68, 77–86, 98–103). D2 teaches optical alignment between PICs and optical components (¶¶ 54–56, 85–90, 102–106). This supports positioning the PIC in alignment with the waveguide end coupler. A skilled artisan would recognize that aligning the PIC to an edge coupler is a conventional, expected way to couple light into or out of the PIC.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to align the PIC with the waveguide end coupler at the edge of the glass preform, as taught by D2 and D3 to maximize optical coupling efficiency and minimize insertion loss.
As to claim 3, D1 discloses the package-level PIC/EIC integration on a glass substrate with routing metallization and interconnects (See ¶¶ 72-95), but does not explicitly disclose the recited plurality of PIC dies arrayed along a first dimension, each optically coupled to a corresponding optical waveguide embedded within a singular glass preform, nor the corresponding plurality of EIC dies arrayed along a second dimension.
D2 teaches the missing multi-component optical packaging teaching by disclosing photonic packaging architectures with multiple optical components, glass blocks, fiber-array blocks, and optical alignment structures arranged in package contexts that support multiple channels. (See ¶¶ 54-56, 85-90, 110-116). D3 teaches the missing waveguide architecture by teaching a glass-based photonic chip with an edge-coupled waveguide structure that can be aligned to provide optical coupling at a package edge. (See ¶¶ 57-68, 74-88, 93-103). D4 further teaches multi-die heterogeneous integration and adjacent packaging of multiple dies. (See ¶¶ 54-68, 80-84, 87-91, 110-115). These teachings collectively show that repeating the PIC-to-waveguide coupling architecture across multiple channels and arranging multiple EIC dies adjacently would have been a predictable scaling choice to increase bandwidth, I/O density, and packaging flexibility.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the known single-channel optical/electrical arrangement because such replication is ordinary design choices and predictable means of increasing I/O density and bandwidth in a hybrid photonic package.
As to claim 4, D1 discloses die-to-die and package interconnects in the photonic/electronic package context, including first-level interconnect structures 136 (See ¶¶ 87-95), but does not explicitly disclose first solder features between the PIC die and the first of the plurality of EIC dies.
D4 explicitly teaches solder-based coupling between dies in photonic/electronic packaging architectures and describes solder interconnect implementation as a routine package assembly choice. (See ¶¶ 44-48, 75-77, 110-116). The cited passages show that solder is used as a standard mechanical and electrical coupling mechanism in heterogeneous packages.
27. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use first solder features between the PIC die and the first EIC die because solder interconnects are a conventional and predictable means of achieving both electrical connection and mechanical attachment in the package environment taught by the references.
28. As to claim 5, D1 discloses conductive traces 126 and other metallization features in the routing structure on the glass substrate and teaches interconnect coupling between dies and substrate routing structures. (See ¶¶ 77-84, 87-95).
D1 does not explicitly disclose second solder features between metallization features of the routing structure and each of the plurality of EIC dies but the cited passages clearly show substrate metallization used for package interconnection and die coupling.
29. In light of D1’s teaching of routing metallization, first-level package interconnects, and hybrid package assembly, it would have been an obvious and routine implementation choice to one of ordinary skill in the art before the effective filing date of the claimed invention to employ solder features between the routing metallization and the EIC dies, because solder is a well-known package interconnect material used to connect die contacts to routing pads in a predictable manner. The modification would not require undue experimentation and would have been expected to yield the same basic electrical coupling function already taught by D1.
30. As to claim 6, D1 explicitly discloses that the substrate comprises glass, that the through vias extend through the glass core, and that the routing metallization is embedded within dielectric 124, which may comprise ABF and other organic dielectric materials. (See ¶¶ 72-79, 79-84, 92-95, 78). These disclosures map directly to the limitations that the substrate comprises glass, the through vias extend through a thickness of the glass, and the metallization features are embedded within an organic dielectric material. D1 also teaches package interconnect coupling between package dies and the routing structure, while D4 teaches that dies may be coupled using solder features or direct-bond-type interconnects depending on the package implementation. (See ¶¶ 87-95; D4 ¶¶ 44-48, 75-77, 110-116). The combined teachings show that the recited coupling alternatives are standard packaging choices.
31. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use either direct bond or solder features to couple the EIC dies to the routing structure because the cited art teaches those options as known, routine coupling mechanisms selected according to conventional packaging tradeoffs such as pitch, manufacturability, and thermal-mechanical reliability.
32. As to claim 7, D1 teaches the glass-based substrate 102 having a glass core 104, dielectric 124, conductive traces 126, and TGVs 120 extending through the glass core, thereby teaching the basic routing structure, through-via interconnect architecture, and glass substrate context. (See ¶¶ 72-79, 79-84, 92-95). D1 further teaches package-level integration of dies with the substrate routing structure, including PIC 134 and EIC 138 coupled by first-level interconnects (See ¶¶ 80-84, 87-95).
33. D1 doesn’t explicitly disclose the limitation such as, first side of the substrate comprising a recess, with a passive device within the recess between the routing structure and the second side of the substrate and electrically coupled to the routing structure.
34. D4 discloses heterogeneous photonic/electronic package architectures having cavity- or recess-based placement of dies and components, including package structures in which components are positioned in recessed portions of a substrate and electrically coupled to routing features. (See ¶¶ 54-68, 80-84, 87-91, 110-116). The cited passages show that placing a passive device in a recess between routing levels is a known packaging arrangement used to enable compact integration and close electrical coupling to routing structures.
35. A person of ordinary skill in the art would have recognized that placing a passive device in a recess between the routing structure and the opposite side of the substrate is a predictable package integration option used to reduce package height and to place passive circuitry close to the routing features.
36. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the glass package of D1 to include a recess and a passive device therein, as suggested by D4 because the combination preserves the known electrical routing framework while enabling compact integration of passive components.
37. As to claim 8, D1 discloses the glass substrate 102 with conductive traces 126 and TGVs 120 extending through the glass core 104, as well as the package-level integration of dies with the routing structure. (See ¶¶ 72-84, 87-95).
38. D1 does not explicitly disclose that the passive device comprises a coupling capacitor having terminals coupled to the routing structure and to the second side of the substrate through through-vias.
39. However, D4 teaches the use of package-level passive elements, including capacitive structures and other passive circuitry, integrated into heterogeneous package architectures and coupled to routing and via structures. (See ¶¶ 54-68, 80-84, 87-91, 110-116). Thus, D4 supplies the missing teaching of a passive capacitor-like structure integrated into a package-level interconnect network.
40. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the passive device of claim 7 as a coupling capacitor because capacitors are a well-known, routine passive component used for decoupling, coupling, and filtering in high-density package routing. A skilled artisan would have had a predictable reason to place such a capacitor in the recess and couple it to the routing and via network to improve signal conditioning and package-level power integrity.
41. As to claim 9, D1 discloses a glass substrate 102 having a glass core 104 and embedded waveguide 106, as well as conductive traces 126 and TGVs 120 extending through the substrate, thereby teaching the electrical and optical foundation recited in the claim. (See ¶¶ 72-84, 87-95).
42. D1 does not expressly teach the claimed second substrate coupled to the first routing structure having its own second plurality of conductive through vias and second routing structure, together with a PIC die attached to a side of the EIC die and an adjacent glass preform over the second routing structure that carries a second optical waveguide and a vertical optical coupler embedded within a recess in the first substrate.
43. D2 teaches package-level optical components such as glass blocks, fiber-array blocks, and pass-through structures used adjacent to PICs. (See ¶¶ 54-56, 85-116). D3 teaches a glass-based photonic waveguide structure with edge coupling at a chip boundary. (See ¶¶ 57-68, 74-103). D4 teaches multi-layer and heterogeneous package integration, including recessed component placement and stacked interconnect structures. (See ¶¶ 54-68, 80-116).
44. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine these teachings to provide an additional glass optical routing layer coupled to a stacked routing substrate because doing so would permit optical signal transfer between package levels while maintaining the electrical routing advantages already provided by D1. The combination would merely apply known optical packaging techniques to the known glass-routing substrate architecture to obtain a predictable hybrid electrical/optical package.
45. As to claim 10, D1 teaches the first substrate with glass core 104, routing traces 126, TGVs 120, and PIC/EIC package integration (See 454 ¶¶ 72-95), but does not expressly teach the recited plurality of first substrates coupled to the second routing structure; a plurality of vertical optical couplers embedded within corresponding recesses in the second substrate; each first substrate comprising a PIC die and an EIC die; and each PIC die coupled to a corresponding vertical optical coupler.
46. The missing teachings are taught by D2 and D3, which disclose optical package architectures using optical components and alignment structures, and by D4 which discloses multi-die and heterogeneous package integration. (See D2: ¶¶ 54-56, 85-90, 102-106, 110-116; D3: ¶¶ 57-68, 74-88, 93-103; D4: ¶¶ 54-68, 80-84, 87-91, 110-116). The cited passages demonstrate that optical coupling structures can be repeated across multiple package units and that multiple dies can be arranged in a package to mate with corresponding optical elements.
47. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replicate the first-substrate/PIC/EIC assemblies and corresponding vertical optical couplers because channel replication is a routine and predictable scaling strategy to increase throughput, optical I/O count, and package modularity.
48. As to claim 11, D1 teaches the glass substrate/core, routing structure, and through-via architecture (See ¶¶ 72-95), but does not expressly teach that the second end of the second optical waveguide is coupled to an optical connector affixed to the second substrate.
49. D2 discloses optical package structures using optical components, glass blocks, fiber-array structures, and optical connectors that interface with PIC-related optical paths. (See ¶¶ 54-56, 85-90, 102-106, 110-116). D3 likewise teaches that a waveguide in a glass-based photonic chip can be aligned and coupled at an edge interface for optical communication, which supports coupling a waveguide end to an external optical connector. (See ¶¶ 57-68, 74-88, 93-103). The cited passages show that optical connectors are a known way to terminate or interface with a waveguide end in a photonic package.
50. Therefore, it would have been obvious to couple the second end of the second optical waveguide to an optical connector affixed to the second substrate because such a connector would provide a known, predictable interface for routing optical signals into or out of the package while preserving the modular glass-based optical routing taught by the references.
51. As to claim 12, D1 teaches the glass substrate/core, routing metallization, and through-via architecture, but does not expressly teach the recited memory IC die attached to at least one of the routing structure or the second routing structure. (See ¶¶ 72-95).
52. D4 discloses heterogeneous photonic/electronic package architectures including additional IC die, memory-related dies, and other supporting package components coupled to routing structures and package interconnects. (See ¶¶ 54-68, 80-84, 87-91, 110-116). The cited passages show that a memory IC die may be placed on a routing structure in the package to support compute, control, buffering, or data handling functions.
53. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a memory IC die on the routing structure because memory is a routine companion die in heterogeneous packages and because routing structures are conventional mounting and electrical coupling locations for auxiliary dies. The combination would have been a predictable package-level integration choice to add memory capacity or buffering without altering the basic glass-routing architecture taught by D1.
54. As to claim 13, D1 discloses an integrated circuit (IC) device, comprising: a first substrate comprising glass and an optical waveguide embedded within the glass (D1 expressly teaches a substrate 102 having a glass core 104. See ¶¶ 72–76. D1 further teaches that the core includes waveguide 106, which is formed within the glass and routes optical signals through the substrate. See ¶¶ 74–76. D1 also explains that the waveguide can bend optical signals and that optical via 128 aligns with waveguide 106. See ¶¶ 74–80, 82–84. The cited portions of D1 read directly on a first substrate comprising glass and an optical waveguide embedded within the glass, because the glass core is the structural glass body of the substrate and waveguide 106 is explicitly formed in that glass core. The waveguide is not merely adjacent to the substrate; it is embedded in the glass core and used to route optical signals);
a first routing structure on a first side of the first substrate, the first routing structure comprising metallization features electrically interconnected to a first plurality of conductive through vias extending through the first substrate to a second side of the first substrate (D1 teaches conductive traces 126 on either side of the glass core 104, with dielectric 124 disposed around them. See ¶¶ 77–79. D1 also teaches TGVs 120 extending through the glass core 104. See ¶¶ 79–84. It further states that conductive traces 126, vias, planes, and pads may be provided on either side of the core and that the traces and vias provide electrical coupling. See ¶¶ 77–84, 92–95; conductive traces 126 are the claimed metallization features, and the TGVs 120 are the claimed conductive through vias. The disclosure that these traces and vias are on either side of the glass core, and that TGVs extend through the core, supports the claimed first routing structure on a first side of the first substrate with metallization features electrically interconnected to the through vias.);
a second substrate coupled to the first routing structure, the second substrate comprising (D1 teaches a package assembly in which substrate 102 is coupled to dies and other package components and further coupled to package substrate 402 through MLI 142 or similar interconnect structures. See ¶¶ 80–84, 87–95 and ¶¶ 99–101; While D1 does not use the exact words “second substrate” in the same way as claim 13, it teaches stacked/package-level substrate coupling and a substrate-to-substrate interconnect framework. The cited disclosure supports the general concept of a second substrate coupled to the routing structure):
a second plurality of conductive through vias extending through the second substrate; and a second routing structure on a side of the second substrate opposite the first routing structure, the second routing structure coupled to the first routing structure through the second plurality of through vias (D1 discloses conductive traces 126 and TGVs 120 in a glass substrate. See ¶¶ 77-84. D1 also teaches that the conductive pathways and vias provide package interconnection. See ¶¶ 92-95. Thus D1 clearly teaches routing metallization and through-vias in a glass substrate).
an electronic IC (EIC) die electrically coupled to a side of the second routing structure opposite the second substrate ( D1 discloses EIC 138 coupled to the substrate through first-level interconnects and package routing structures. See ¶¶ 80-84, 87-95; Thus D1 teaches an EIC die electrically coupled to routing in the package context); and
a photonic IC (PIC) die attached to a side of the EIC die opposite the second routing structure (D1 discloses PIC 134 and EIC 138 integrated in the same package. See ¶¶ 80-84, 87-95; Thus D1 teaches the coexistence of PIC and EIC dies in a package, but it does not expressly teach the exact physical arrangement of the PIC die being attached to a side of the EIC die opposite the second routing structure.)
the PIC die coupled to the optical waveguide through an adjacent glass preform affixed to the second substrate, over the second routing structure (D1 teaches a glass core 104 with embedded waveguide 106 and optical via 128 (See ¶¶ 72-80, 82-84, 92-95). Thus it reads on a glass-based optical routing body in general, but not on the exact claimed glass preform affixed to a second substrate and positioned over the second routing structure),
and comprising a second optical waveguide coupling the PIC die to a vertical optical coupler embedded within a recess in the first side of the first substrate (D1 teaches waveguide 106 embedded in glass core 104 and optical via 128 aligned with the waveguide. See ¶¶ 72-80, 82-84; Thus D1 teaches an embedded optical waveguide and an optical via).
55. D1 does not explicitly disclose adjacent glass preform affixed to the second substrate, over the second routing structure, and comprising a second optical waveguide coupling the PIC die to a vertical optical coupler embedded within a recess in the first side of the first substrate.
56. D2 discloses photonic package architectures using optical components such as glass blocks, fiber-array blocks, pass-through structures, and optical alignment structures adjacent to PICs, which reasonably corresponds to a glass preform or optical coupling body carrying an optical waveguide. (See ¶¶ 54-56, 85-90, 102-106, 110-116). D3 discloses a glass photonic chip with a composite guiding structure and waveguide arranged for edge coupling at the edge of the photonic chip, thereby teaching a glass-based optical waveguide structure and an optical end-coupling interface. (See ¶¶ 57-68, 74-88, 93-103). D4 further teaches heterogeneous multi-die and multi-layer packaging with optical and electrical interconnect structures, including recessed and package-level component placement. (See ¶¶ 54-68, 80-84, 87-91, 110-116).
57. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the glass-based package of D1 to include the optical coupling architecture of D2 and D3, because D1 already supplies the glass substrate, routing metallization, and through-via electrical interconnect framework, while D4 and D2 supply the known glass optical component / waveguide / edge-coupler concepts needed to route optical signals between dies and substrates in a modular package. Further, combining them would have been a predictable and routine way to obtain a package capable of dense electrical routing and low-loss optical coupling across multiple substrate levels.
58. As to claim 14, D1 discloses the IC device of claim 1 (See ¶¶ 80–84, 87–95; teaches PIC/EIC placement on the substrate ) but doesn’t explicitly disclose wherein the PIC die is alignment with an end coupler of the optical waveguide that intersects an edge of the glass preform.
59. D3 expressly teaches edge-coupling of a waveguide to a photonic chip and the alignment of the waveguide end at the edge of the glass-based structure (See ¶¶ 62–68, 77–86, 98–103). D2 teaches optical alignment between PICs and optical components (See ¶¶ 54–56, 85–90, 102–106). This supports positioning the PIC in alignment with the waveguide end coupler. A skilled artisan would recognize that aligning the PIC to an edge coupler is a conventional, expected way to couple light into or out of the PIC.
60.. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to align the PIC with the waveguide end coupler at the edge of the glass preform, as taught by D2 and D3 because edge coupling is a known technique for efficiently transferring optical signals with reduced loss, maximize optical coupling efficiency and improved alignment tolerance in hybrid photonic packages.
61. As to claim 15, D1 discloses the IC device of claim 14, wherein: the second substrate comprises glass (See ¶[0073]–¶[0076]; ¶[0126]); the first and second routing structures comprise metallization features embedded within an organic dielectric material (conductive traces embedded in organic dielectric layers (second dielectric 124, ABF/polyimide/BCB examples) (See ¶[0078]–¶[0083]; ¶[0035]); and the EIC die are coupled to the second routing structure either through a direct bond or through solder features (direct/hybrid bonds or solder coupling described (EIC 138 coupled to the package substrate through first-level interconnects 136. See ¶¶ 87–95.).
62. D1 teaches package-level electrical coupling of EIC dies to routing structures, but does not expressly state the direct-bond or solder-feature alternatives in the exact form recited.
63. D4 expressly teaches solder-based interconnects and direct-bond-type interconnect implementations in heterogeneous package architectures. Those teachings support using either direct bond or solder features for EIC-to-routing coupling ( See ¶¶ 44–48, 75–77, 110–116).
64. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply direct bond or solder features because these are routine, predictable package interconnect options selected according to manufacturability, pitch, and thermal-mechanical constraints.
65. As to claim 16, D1 discloses the IC device of claim 14, wherein: the PIC die is one of a plurality of PIC die arrayed along a first dimension of the second routing structure and coupled to an optical waveguide embedded within the glass preform (D1 teaches a PIC 134 and waveguide 106 in a glass core, but not a plurality of PIC dies arrayed along a routing structure with corresponding waveguides in a singular glass preform. See ¶¶ 72–80, 87–95;.). Thus D1 reads on the general PIC/waveguide concept, but not the specific multi-PIC arrayed architecture.
66. D2 teaches multi-component optical package structures and repeatable optical interfaces ( See ¶¶ 54–56, 85–116). D3 teaches the waveguide-in-glass and edge-coupling arrangement (See ¶¶ 57–68, 74–103). D4 teaches multi-die heterogeneous package integration. Together, these teach or suggest repeating the PIC/waveguide arrangement across multiple dies (See ¶¶ 54–68, 80–116). Together, these teach or suggest repeating the PIC/waveguide arrangement across multiple dies.
67. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replicate the PIC-to-waveguide interface across multiple channels to increase bandwidth and I/O density, which is a predictable scaling strategy in photonic package design.
As to the limitation of each of the plurality of PIC die is adjacent to one of a plurality EIC die arrayed along a second dimension of the second routing structure, D1 discloses PIC and EIC dies in the same package context. (See 454 ¶¶ 80–84, 87–95.). Thus, D1 teaches PIC/EIC coexistence and electrical coupling, but not the exact arrayed adjacency arrangement.
68. D4 teaches multi-die heterogeneous package layouts in which multiple dies are arranged in package-level arrays (See ¶¶ 54–68, 80–116). D2 supports multi-component optical package integration (See¶¶ 54–56, 85–116). These disclosures support arranging EICs adjacent to PICs in a repeated array.
69. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange EIC dies adjacent to the PIC dies in an array because multi-die array layouts are a conventional way to organize routing, reduce interconnect distance, and scale package channel count.
70. As to claim 17, D1 teaches substrate-level routing metallization and through-via interconnect structures, but does not expressly disclose the recited first solder features between the first routing structure and the second through vias; second solder features between the second routing structure and EIC die; and third solder features between the PIC die and the second EIC die. (See ¶¶ 72-95). D1 nonetheless teaches first-level interconnect coupling between package dies and substrate routing structures, while D4 expressly teaches solder-based interconnect implementations for die-to-die and die-to-substrate coupling in heterogeneous photonic/electronic package architectures. (See D1: ¶¶ 87-95; D4 ¶¶ 44-48, 75-77, 110-116). The cited passages show that solder interconnects are a conventional and predictable choice for both die-to-routing and die-to-die coupling in advanced packaging.
71. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use solder features in the claimed locations because solder is a routine package interconnect material selected to establish electrical connection and mechanical attachment between routed metallization, vias, EIC dies, and PIC dies.
72. Claim(s) 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram et al., (hereinafter D1) (previously cited) in view of US Li et al., US 2023/0089494 A1 (hereinafter D2) and DE ANGELS et al., US 2023/0142315 A1 (hereinafter D3).
73. As to claim 18, D1 discloses forming through holes in a glass substrate and forming conductive through vias by metallizing the through holes (D1 discloses: “vias for Ts 120 may be formed in glass panel 502”, “the vias may be filled with copper (or other conductive metal) to generate TGVs 120; [0105] further discloses: “optical via 128 may be formed …” in the glass-based structure, and the glass panel becomes embedded within material layers forming the core; A person of ordinary skill in the art would understand “forming through holes in a glass substrate and forming conductive through vias by metallizing the through holes” to correspond to the process in D1 where holes/vias are created in the glass panel and metallized/fill-plated to form TGVs. The claim’s “through vias” are therefore reasonably met by D1’s TGVs.);
building up a routing structure coupled to the through vias (D1: [0105] discloses: “Second dielectric 124 along with conductive traces 126 (e.g., traces and vias), may be formed on either side of glass panel 502. During this process, glass panel 502 becomes embedded within material layers thereby forming core 104.” [0078] discloses: “Conductive traces 126, including vias, planes and pads, may be provided on either side of core 104 in second dielectric 124 using any suitable conductive material, such as copper.” [0083] discloses MLI as conductive pathways enabling electrical/mechanical coupling; the glass substrate can function as a redistribution layer. “Building up a routing structure coupled to the through vias” is reasonably interpreted to cover D1’s build-up of dielectric and conductive trace layers around the glass panel, with conductive traces/vias/pads on either side and TGV interconnection through the glass. The routing structure is the conductive trace/plane/pad stack formed in the dielectric layers on the substrate);
attaching a glass preform to a first region of a first side of the routing structure opposite the glass substrate, the glass preform comprising an optical waveguide (D1: [0072]–[0075] disclose a substrate with a glass core and a waveguide 106 fabricated in the glass using DLW; [0073] characterizes the substrate as a “patch substrate” with a smaller footprint and routing functionality; [0075 in bulk] discloses the waveguide as a 3D shape formed glass; [0103] discloses that the glass panel becomes embedded within material layers to form the core; [0105] discloses the panel embedded in the dielectric/routing structure;
74. D1 doesn’t explicitly disclose “glass reform” per se. It teaches a glass body/panel/core carrying an optical waveguide. D1 also teaches that glass optical bodies/components such as glass blocks and waveguide-containing optical components are used as package optical subassemblies.
75. D2 discloses disclose optical components such as glass locks, fiber array blocks, ** optical components waveguides**, laser written waveguides, and composite in PIC packages (See [0085]–[0086] and [0101]–[0102]); D2 also expressly states that the optical surface component and optical component with defined pathways can be glass blocks or waveguides ([0086]) ; Further, D2 show a package manufacturing process where optical components are attached to/with PIC structures [0102]–[0103].
76. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize that a “glass preform” is simply a pre-shaped glass optical body or glass optical component carrying the waveguide, attachable to a routing structure as a modular optical carrier. The claim term “preform” is reasonably broad enough to encompass a pre-shaped glass optical body or glass optical piece used before final integration. The phrase “attaching a glass preform to a first region of a first side of the routing structure” would have been an obvious packaging implementation in view of the known use of glass optical blocks/components in D2 and the glass-waveguide body in D1.
attaching a PIC die over a second region of the first side of the routing structure, adjacent to the glass preform and in alignment with an end coupler of the optical waveguide intersecting an edge of the glass preform, D1 discloses a waveguide in bulk glass, formed by DLW, with one end on an exposed side and another end on the orthogonal side ([0075]), optical via and optical lens aligned with waveguide end points ([0079]), optical coupling from the waveguide through the optical coupling structure to the PIC ([0107]–[0108] and [0103]), PIC 134 and EIC 138 attached to substrate 102 with FLI 136 ([0104]–[0106]), the PICs coupled on the side of the substrate and receiving optical signals from the waveguide/lens/OCS arrangement ([0080] and [0082]).
77. D3 discloses a photonic chip with a composite guiding structure and a waveguide arranged to overlap with the layer closest to the waveguide ([0057]–[0063] and [0067]–[0068]), the waveguide arranged to partially overlap the uppermost layer or closest layer ([0067]–[0068]), coupling optical fiber to the chip via the edge and evanescently coupling to the waveguide ([0093]–[0103]), aligning the waveguide based on a marker and fabricating it on the chip after the composite guiding structure is formed ([0122]–[0124] ).
78. D2 discloses optical components including glass blocks and waveguides coupled to PICs. ([0086]), show optical components aligned with PICs and integrated into layered packages, ([0102]–[0103] and [0105]–[0107]), multi-layer packagers where optical components are coupled to PICs and optical surfaces. ([0124]–[0126]).
79. The claim recites a PIC die “in alignment with an end coupler of the optical waveguide intersecting an edge of the glass preform.” In D1, the optical waveguide is coupled to the PIC through the optical coupling structure and lens; in D3, the waveguide is explicitly arranged for edge coupling and overlap with a closest layer, with the optical coupling occurring at the chip edge; in D1, the glass optical component / waveguide is used in optical packaging with optical components coupled to PICs.
80. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that it to be an obvious design choice to place the PIC adjacent to the glass waveguide component and align the PIC with the waveguide end-coupler region at the edge of the glass body to maximize optical coupling efficiency and minimize insertion loss. The “end coupler intersecting an edge of the glass preform” maps to the known edge-coupling arrangements in D3 where the waveguide is terminated at an edge and coupled to another optical structure, and to the optical coupling interface in D1 between waveguide and lens/OCS.
attaching an electronic integrated circuit (EIC) die over a third region of the first side of the routing structure, adjacent to the PIC die, DI discloses “PIC 134 and EIC 138 with FLI 136 to substrate 102” ([0104] ), explains attachment of PIC and EIC to the substrate using flip-chip or hybrid bonding ([0106]), explains that EIC 138 may be an ASIC or other IC electrically integrated with the PIC, ([0081] ), and further discusses PIC and EIC receiving power and signals through the substrate ([0090]). D2 discloses PIC packaging with EICs and PICs in the same package ([0037]–[0043]), show EICs placed adjacent to PICs with optical components in the package ([0066]–[0068] and [0102]–[0107]), multi-chip/package-level integration and adjacency of PIC and EIC dies ([0114]–[0116] ).
81. D1 expressly teaches PIC and EIC dies coupled to the substrate. The claim’s requirement that the EIC die be adjacent to the PIC die and over the same routing structure region is a routine packaging placement reflected in D1 and D2. The routing structure serves as the electrical interconnect layer, while the PIC and EIC are placed adjacently to support dense electrical signaling and optical access.
82. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of D1, D2 and D3 because: D1 provides the glass substrate with through-vias, routing traces, and integrated PIC/EIC packaging. D2 teaches using glass optical components / glass blocks / waveguide-bearing optical elements in PIC packaging and shows that optical access can be integrated into layered packages and D3 teaches edge-coupled waveguide structures and the desirability of arranging the waveguide near an edge and coupling it to a waveguide-containing optical element for efficient optical coupling. The combination would improve optical coupling efficiency, reduce insertion loss, allow modular assembly of optical and electronic package elements, preserve dense electrical interconnect routing through the glass substrate, and enable a packaging architecture where the optical waveguide can be separately formed in a glass preform and then positioned relative to PIC/EIC dies. This is a predictable use of prior art elements according to their established functions. The routing structure of D1 provides electrical interconnectivity; the glass optical preform provides optical routing; and D2/D3 provide the optical coupling configuration needed for the PIC.
83. Claim(s) 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of D2 and D3 and further in view of D4.
84. As to claim 19, D1 teaches a glass substrate 102 having an embedded waveguide 106 in the glass core 104, together with routing metallization 126 and through-glass vias 120 extending through the substrate. See ¶¶ 72-84, 87-95. D1 therefore provides the basic glass-waveguide and through-via routing framework recited in claim 19.
85. D1 does not expressly disclose the further limitation of “attaching a vertical optical coupler to a second glass substrate, the second glass substrate comprising a second optical waveguide and a second routing structure; and attaching the through vias to the second routing structure with the optical waveguide optically coupled to the vertical optical coupler.”
86. However, D2 teaches package-level optical coupling components such as glass blocks, fiber-array blocks, pass-through structures, and other optical interface bodies used adjacent to PICs and optical routing structures. See ¶¶ 54-56, 85-116. D3 teaches a glass-based photonic chip having an embedded optical guiding structure and an edge-coupler arrangement for optical transfer at a chip boundary. See ¶¶ 57-68, 74-103. D4 teaches heterogeneous and stacked package structures with multiple routing layers, multiple dies, and recessed or nested component placement, as well as package-level interconnect integration. See ¶¶ 54-68, 80-116.
87. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a second glass substrate carrying a second optical waveguide and a vertical optical coupler to the glass-routing architecture of D1, because such an arrangement is a predictable way to route optical signals between package levels while preserving the electrical interconnect framework already taught by D1. The use of a vertical optical coupler and second glass substrate is a routine optical packaging implementation choice, and the through vias of D1 would naturally attach to the second routing structure to provide the required electrical connection in a stacked package.
88. As to claim 20, D1 teaches the foundational glass substrate with an embedded waveguide and routing metallization coupled by through vias, as well as a PIC/EIC package architecture. See ¶¶ 72-95. Claim 20 adds a more specific multi-channel and multi-substrate optical/electrical packaging arrangement, namely: “attaching a second glass preform to a fourth region of the routing structure, the second glass preform also comprising an optical waveguide; attaching a second photonic IC (PIC) die over a fifth region of the routing structure, adjacent to the second glass preform; attaching a second electronic integrated circuit (EIC) die over a sixth region of the routing structure, adjacent to the second PIC die; and attaching a second vertical optical coupler to the second glass substrate, the second glass substrate comprising another optical waveguide optically coupled to the second PIC die through the second vertical optical coupler.”
89. D1 does not expressly disclose that repeated stacked arrangement. However, D2 teaches modular optical package components, including glass blocks, fiber-array blocks, pass-through structures, and optical alignment structures used in package-level PIC integration. See ¶¶ 54-56, 85-116. D3 teaches that a glass-based optical waveguide structure can be arranged for edge coupling and optical transfer at a chip boundary, thereby providing the optical interface principle for the claimed second glass preform and vertical optical coupler arrangement. See ¶¶ 57-68, 74-103. D4 teaches stacked heterogeneous package architectures with multiple dies and multiple routing levels, including repeated die placement and package-level interconnect integration. See ¶¶ 54-68, 80-116.
90. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replicate the optical-coupler / glass-preform / PIC / EIC arrangement across multiple regions of the routing structure because multi-channel optical packaging is a known scaling strategy for increasing bandwidth and packaging density. The second glass preform, second PIC die, and second EIC die are simply repeated instances of known optical/electrical package building blocks applied to additional routing regions, and the second vertical optical coupler provides the known optical interface for coupling the second PIC die to the glass-based optical routing path. The resulting structure would have been a predictable extension of the glass-waveguide and heterogeneous package teachings already present in D1, D2, D3 and D4.
Examiner’s Note
91. The examiner has pointed out particular references contained in the prior art of record within the body of the action for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Applicant, in preparing response should consider fully the entire reference as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or discussed by the examiner.
Conclusion
92. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TARIFUR RASHID CHOWDHURY whose telephone number is (571)272-2287. The examiner can normally be reached M-F: 8 am-5 pm.
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/TARIFUR R CHOWDHURY/Supervisory Patent Examiner, Art Unit 2877
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