CTNF 18/129,702 CTNF 77987 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (2015/0318332) in view of Miyake et al. (2018/0113547) . Regarding claims 1, 4 and 19, Lu (Figs. 1 and 18) discloses an integrated circuit device comprising: a resistor (1R) formed on a substrate 102/1802 ([0046] and [0085]), the resistor (1R) comprising: a gate electrode 1804 (Fig. 18, [0085]); a gate dielectric 1806 in contact with the gate electrode 1804; a source electrode 1808 and a drain electrode 1810; and a thin film transistor TFT channel material 1812 coupled between the source electrode 1808 and the drain electrode 1810 (Figs. 1 and 18, [0046] and [0085]). Lu discloses all the claimed limitations as discussed above, except for a non-crystalline substrate. Miyake (Fig. 16A) discloses the non-crystalline substrate 570 comprises silicon oxide, silicon nitride, or silicon oxynitride (see [0324]) for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416. Accordingly, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the device of Lu by forming the non-crystalline substrate comprises silicon oxide, silicon nitride, a metal oxide, or silicon oxynitride for the intended use as a matter of design choice, as taught by Miyake (see [0324]). Regarding claim 3, Lu (Figs. 1 and 20-21) discloses wherein the integrated circuit device comprises an integrated circuit die with a front side comprising a plurality of transistors 2005/2112 and interconnect layers (2030, 2032, 2034, 2036) and a back side comprising the resistor 1R (2104, 2106, 2108) (Fig. 20-21, [0008]). Regarding claims 5 and 20, Lu (Figs. 1 and 18) discloses further comprising a diode (1D) comprising a first conductive contact 112, a second conductive contact 108, and the TFT channel material 110/1812 coupled between the first conductive contact 112 and the second conductive contact 108. Regarding claim 6, as discussed, the combination above, Miyake (Fig. 16A) discloses further comprising a circuit implementing electrostatic discharge protection, wherein the circuit comprises the resistor and the diode ([0075] and [0236]). Regarding claim 7, Lu (Figs. 1 and 18) discloses wherein the first conductive contact 112 is substantially parallel to the second conductive contact 108, and wherein the TFT channel material 110/1812 is substantially orthogonal to the first conductive contact 112 and the second conductive contact 108. Regarding claim 8, Lu (Figs. 1 and 18) discloses wherein the TFT channel material 110 is substantially parallel to the first conductive contact 112 and second conductive contact 108 in a horizontal grating configuration. Regarding claim 9, Lu (Figs. 1 and 18) discloses wherein the TFT channel material 110 is between the first conductive contact 112 and second conductive contact 108 in a vertical stack. Regarding claims 10-11, Lu (Figs. 1 and 18) discloses wherein the integrated circuit device comprises an integrated circuit die with a front side comprising a plurality of transistors 2005/2112 and interconnect layers (2030, 2032, 2034, 2036) and a back side comprising the resistor 1R (2104, 2106, 2108) (Fig. 20-21, [0008]), wherein the back side of the integrated circuit die further comprises the diode 110 (Fig. 1, [0056]). Regarding claim 12, as discussed, the combination above, Miyake (Figs. 15A-15C) discloses further comprising a circuit board FPC1 coupled to the integrated circuit die. Regarding claim 13, Lu (Figs. 1 and 18) discloses further comprising at least one of a network interface, battery, or memory coupled to the integrated circuit die ([0043]). Regarding claim 14, Lu (Figs. 1 and 18) discloses an apparatus comprising: a diode (1D) formed on a substrate 102 (Fig. 1, [0046]), the diode comprising: a first conductive contact 112; a second conductive contact 108; and a thin film transistor (TFT) channel material 110/1812 coupled between the first conductive contact 108 and the second conductive contact 112 (Figs. 1 and 18, [0046] and [0085]). Lu discloses all the claimed limitations as discussed above, except for the non-crystalline substrate. Miyake (Fig. 16A) discloses the non-crystalline substrate 570 comprises silicon oxide, silicon nitride, or silicon oxynitride (see [0324]) for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416. Accordingly, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the device of Lu by forming the non-crystalline substrate for the intended use as a matter of design choice, as taught by Miyake (see [0324]). Regarding claim 15, Lu (Figs. 1 and 4-5) discloses wherein the TFT channel material 110/406 and the first conductive contact 408/112 form a Schottky barrier ([0054]). Regarding claim 16, Lu (Figs. 1 and 18) discloses wherein the TFT channel material 110/1812 and the second conductive contact 108 form an ohmic contact ([0071]). Regarding claims 2 and 17, Lu discloses all the claimed limitations as discussed above, except for wherein the TFT channel material has a charge carrier mobility within a range of 5 cm 2 /(V-s) to 700 cm 2 /(V-s) and a bandgap voltage within a range of 1.15 eV to 6.5 eV at 300 degrees Kelvin. However, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of the ranges of charge carrier mobility or the bandgap voltage of the claimed device and a device having the claimed relative of the ranges of charge carrier mobility or the bandgap voltage would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardner v. TEC Systems, Inc ., 725 F. 2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to form the range of charge carrier mobility or the bandgap voltage as claimed, because they can be varied for other implementations. Regarding claim 18, Lu (Figs. 1 and 18) discloses further comprising: a resistor (1R) comprising: a gate electrode 1804 (Fig. 18, [0085]); a gate dielectric 1806 in contact with the gate electrode 1804; a source electrode 1808 and a drain electrode 1810; and the TFT channel material 1812 coupled between the source electrode 1808 and the drain electrode 1810. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THERESA T DOAN whose telephone number is (571)272-1704. The examiner can normally be reached on Monday, Tuesday, Wednesday and Thursday from 7:00AM - 3:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THERESA T DOAN/ Primary Examiner, Art Unit 2814 Application/Control Number: 18/129,702 Page 2 Art Unit: 2814 Application/Control Number: 18/129,702 Page 3 Art Unit: 2814 Application/Control Number: 18/129,702 Page 4 Art Unit: 2814 Application/Control Number: 18/129,702 Page 5 Art Unit: 2814 Application/Control Number: 18/129,702 Page 6 Art Unit: 2814 Application/Control Number: 18/129,702 Page 7 Art Unit: 2814
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