Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is in reply to papers filed on 6/15/2023. Claims 1-20 are pending. Claims 1, 10, and 15 is/are independent.
Subject Matter Eligibility
Claims 1-14 recite eligible subject matter. The claims are directed to an improvement to a hashing circuit.
Regarding claim 1, the claim recites a Galois field multiplier, which generates one or more values, and there is a multiplication operation involved, which is a mathematical concept. Alternatively, the claim recites a mental process because a person can also create a value. However, the claim recites a practical application and/or significantly more because the Galois field multiplier is pipelined, which is an improvement based on the description of the problem in the specification at para. 4, which states “individual hash functions may not be pipelined”, and the pipelining is described at para. 28.
Regarding claim 10, claim 10 recites performing multiplication operations, which is reciting a mathematical concept. The storing of the output in the first pipeline stage and the recitation of the transitioning from first pipeline stage to the second pipeline stage reflects the improvement of utilizing the pipelines, which is a practical application and/or significantly more.
Because each of claims 1.and 10 recite a practical application and/or significantly more, the claims are reciting eligible subject matter.
Election/Restrictions
The restriction requirement below is based on the claims originally filed on 3/31/2023.
Restriction to one of the following inventions is required under 35 U.S.C. 121:
Group I or Group II.
• Group I: Claims 1-14, drawn to an integrated circuit and a related method involving an application of the Galois field multiplier and an adder, classified in H04L9/00, H04L9/0637, H04L9/3242, H04L2209/00, H04L2209/12, and H04L2209/125.
• Group II: Claims 15-20, drawn to circuitry of a polynomial multiplier, classified in H04L9/3093 and H04L2209/12.
During a telephone conversation with Applicant's representative (Vanessa Garza, Reg. No. 83491) on January 8, 2026 a provisional election was made without traverse to prosecute the invention of Group I, claims 1-14.
Inventions Group I and Group II are related as combination and subcombination. Group I (integrated circuit) is the combination and Group II is the subcombination. Inventions in this relationship are distinct if it can be shown that (1) the combination as claimed does not require the particulars of the subcombination as claimed for patentability, and (2) that the subcombination has utility by itself or in other combinations (MPEP § 806.05(c)). In the instant case, the combination as claimed does not require the particulars of the subcombination as claimed because the combination only requires a Galois field multiplier and does not require the particular capabilities of polynomial multiplication of the subcombination. The subcombination has separate utility such as performing multiplication of polynomials. The subcombination can also be used in another materially different combination such as with other cryptographic circuitry including circuitry for public-key cryptography. The method claims are related to the integrated circuit and grouped together for examination.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
• the inventions have acquired a separate status in the art in view of their different classification;
• the inventions have acquired a separate status in the art due to their recognized divergent subject matter; and/or
• the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites “wherein the adder provides a summation of the one or more values”. However, the broadest reasonable interpretation of claim 1 includes providing a summation of only one value and it is unclear how a single value can be summed by itself since taking the sum requires two values. For compact prosecution, this is interpreted as performing a summation operation that includes the one or more values.
The dependent claims inherit the limitations of independent claim 1 and is rejected for the same reasons as independent claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claime d invention as a whole would have been obvious before the effective filing date of the claimed invention t/o a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 7, 10-11, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Langhammer et al. U.S. Patent No. 10237066 (hereinafter “Langhammer”) in view of Yankilevich et al. U.S. Publication 20220311598 (hereinafter “Yankilevich”).
As per claim 1, Langhammer discloses
An integrated circuit comprising:
2:39-47 (7) Therefore, in accordance with embodiments of the present invention, systems and methods are provided for processing data using deeply-pipelined algorithms and circuitries. In one embodiment, a scalable and efficient cryptographic architecture may be implemented as circuitry in a fixed logic device, or may be configured into a programmable integrated circuit device. The same top-level design may be used for different choices of data channels, processing depth, parallelism level, and/or system throughput.
selection circuitry [selection circuitries, 1 9:1-23] configurable to provide one of a plurality of powers [ providing channel values H and powers thereof, 9:1-23; providing hash values X and powers thereof, 9:14-15 ] of a hash key;[ combining channel values H and hash values X, 9:1-23; hash subkey value H, 9:24-31; channel values H, 9:1-23; 10:12-14 The authentication pipeline processing block 350 may receive the hash subkey value or power thereof corresponding to the first channel a ]
Langhammer 9:1-23 (30) FIG. 3 is a simplified block diagram of one possible implementation 300 of an authentication key pipeline block according to some embodiments. FIG. 3 describes authentication using a number x of virtual channels for data incoming from 3 physical channels a, b, and c. This exemplary implementation may be used to implement authentication key pipeline block 170 of FIG. 1. Implementation 300 includes an authentication pipeline processing block 350 for combining channel values H and hash values X as explained in more detail below, to generate an authentication tag value. As shown on the right, implementation 300 includes register circuitries 301a, 301b, 301c, through 301x, register circuitries 302a, 302b, 302c, through 302x, and register circuitries 303a, 303b, 303c, through 303x, for providing hash values X and powers thereof. As shown on the left, implementation 300 includes register circuitries 361a, 361b, 361c, through 361x, register circuitries 362a, 362b, 362c, through 362x, and register circuitries 363a, 363b, 363c, through 363x, for providing channel values H and powers thereof. Implementation 300 includes selection circuitries 301, 302, 303, 361, 362, 363, 310, and 370 to implement selection of an appropriate value from the register circuitries to be input to the authentication pipeline processing block 350.
9:24-31 (31) In some authentication algorithms such as the GCM mode of AES, encrypted data, e.g., generated by AES, is repeatedly processed using a hash function to generate a hash (or pre-tag) value X. This hash function may implement multiplication within a binary Galois field, by a hash subkey value H, which is generally though not necessarily constant during an authentication session. The final hash value X is retained as the authentication tag.
Langhammer 10:3-24 (36) Going back to FIG. 3, implementation 300 allows authentication pipeline processing block 350 to assemble the appropriate multiplication operands, e.g., according to at least parts of equation EQ. 1, EQ. 2, and/or EQ. 3 above, in order to generate a final authentication tag. For example, authentication pipeline processing block 350 may receive a hash subkey value H.sub.1 from register circuitry 361a, or a v.sup.th power H.sub.1.sup.v thereof (v=1, . . . , x) from one of register circuitries 361b, 361c, through 361x, all corresponding to channel a. The authentication pipeline processing block 350 may receive the hash subkey value or power thereof corresponding to the first channel a. The authentication pipeline processing block 350 may combine this received hash subkey value or power thereof with an intermediate hash value X.sub.1, received from register circuitry 301a or a power therefor X.sub.1.sup.x, also corresponding to the first channel a, using multiplication, adder and any suitable combination circuitry. The same may be done with authentication parameters for a second channel b (using hash subkey value H.sub.2, intermediate hash value X.sub.2, and/or powers of H.sub.2 and/or X.sub.2) and a third channel c (using hash subkey value H.sub.3 and intermediate hash value X.sub.3, and/or powers H.sub.3 and/or X.sub.3).
a Galois field multiplier [multiplication within a binary Galois field, 9:24-31; Galois field multiplier can be disclosed by authentication pipeline processing block 350, element 50, figure 3; authentication pipeline processing block 350 to assemble the appropriate multiplication operands, e.g., according to at least parts of equation EQ. 1, EQ. 2, and/or EQ. 3 above, in order to generate a final authentication tag, 10:3-7; support complex logic structure (such as 128-bit Galois Field operations) and customizable multiplier input structures, 13:7-11; authentication pipeline processing block 350 may combine… using multiplication, 10:14-19] configurable to receive the one of the plurality [see figure 3 which shows multiple powers (exponents) being received from the hashes H and also the hashes X ] of powers of the hash key [authentication pipeline processing block 350 may receive a hash subkey value H.sub.1 from register circuitry 361a, or a v.sup.th power H.sub.1.sup.v thereof, 10:8-10;10:12-14 The authentication pipeline processing block 350 may receive the hash subkey value or power thereof corresponding to the first channel a; ] and a hash sequence [see all the hashes H, and hashes X being received at authentication pipeline processing block 350, in figure 3; authentication pipeline processing block 350 may receive a hash subkey value H.sub.1, H.sub.1, etc. thereby disclosing hash sequence, 10:3-24] and generate one or more values, [one or more values can be disclosed by the generated authentication tag; The final hash value X is retained as the authentication tag, 9:30-31; combining channel values H and hash values X as explained in more detail below, to generate an authentication tag value, 9:9-10 ] wherein the Galois field multiplier comprises multiple levels of pipeline stages; [see Figure 3 which depicts authentication pipeline processing block 350 with four pipelines (rounds); authentication pipeline processing block 160 may implement an authentication pipeline 165, 5:59-63; figure 1 authentication pipeline processing block 160] and
Langhammer 5:63-6:1 authentication pipeline processing block 160 may implement any suitable authentication process, for example, GCM which takes a plaintext bit string as an input and combines it with an initialization vector (IV) to produce an encrypted bit string (i.e., ciphertext) and an authentication tag,
4:15-24 (8) FIG. 1 is a block diagram of an encryption and authentication core architecture 100 according to some embodiments. Architecture 100 includes an encryption pipeline processing block 130 and an encryption key pipeline block 110. Architecture 100 also includes an authentication pipeline processing block 160 and an authentication key pipeline block 170. As shown, architecture 100 processes data incoming from a plurality of channels 105, of which only three channels are shown as channels a, b, and c.
5:59-63 (17) Turning to the authentication aspect of architecture 100, authentication pipeline processing block 160 may implement an authentication pipeline 165 for authenticating the data block incoming from one of the channels 105 or the encryption pipeline processing block 130.
(11) In some embodiments, the circuitry further includes an authentication pipeline processing block for performing authentication rounds upon said data block. The authentication pipeline processing block may receive a respective hash key value for each authentication round upon said data block. The circuitry may further include an authentication key pipeline block for providing the respective hash key value for each authentication round upon said data block, by selecting, for each authentication round, the respective hash key value from at least a first hash key value corresponding to the first channel and a second hash key value corresponding to the second channel. The authentication key pipeline block may include a first set of storage circuitries for storing a plurality of powers of a first hash key value corresponding to the first channel and a second set of storage circuitries for storing a plurality of powers of a second hash key value corresponding to the first channel.
2:48-52 (8) In one embodiment, circuitry for processing data incoming from at least a first channel and a second channel is provided. The circuitry includes an encryption pipeline processing block for performing rounds of processing upon a block of said data using an encryption process. The encryption pipeline processing block receives a respective round encryption key for each round of processing upon the block of data. The circuitry also includes an encryption key pipeline block for providing the respective round encryption key for each round of processing upon the block of data. The encryption key pipeline block provides a round encryption key by selecting, for each round of processing, the respective round encryption key from at least a first round encryption key corresponding to the first channel and a second round encryption key corresponding to the second channel.
10:3-24 (36) Going back to FIG. 3, implementation 300 allows authentication pipeline processing block 350 to assemble the appropriate multiplication operands, e.g., according to at least parts of equation EQ. 1, EQ. 2, and/or EQ. 3 above, in order to generate a final authentication tag. For example, authentication pipeline processing block 350 may receive a hash subkey value H.sub.1 from register circuitry 361a, or a v.sup.th power H.sub.1.sup.v thereof (v=1, . . . , x) from one of register circuitries 361b, 361c, through 361x, all corresponding to channel a. The authentication pipeline processing block 350 may receive the hash subkey value or power thereof corresponding to the first channel a. The authentication pipeline processing block 350 may combine this received hash subkey value or power thereof with an intermediate hash value X.sub.1, received from register circuitry 301a or a power therefor X.sub.1.sup.x, also corresponding to the first channel a, using multiplication, adder and any suitable combination circuitry. The same may be done with authentication parameters for a second channel b (using hash subkey value H.sub.2, intermediate hash value X.sub.2, and/or powers of H.sub.2 and/or X.sub.2) and a third channel c (using hash subkey value H.sub.3 and intermediate hash value X.sub.3, and/or powers H.sub.3 and/or X.sub.3).
Langhammer 13:7-11 (56) By supporting pipelining and multiplier input structures as described above, systems and methods described herein may support complex logic structure (such as 128-bit Galois Field operations) and customizable multiplier input structures.
However, Langhammer does not expressly disclose an adder configurable to receive the one or more values, wherein the adder provides a summation of the one or more values.
Yankilevich discloses an adder [additive operator 838, para 94] to make a correction to a tag by computing the sum of separate values
[Claim 1 recites “wherein the adder provides a summation of the one or more values”. However, the broadest reasonable interpretation of claim 1 includes providing a summation of only one value and it is unclear how a single value can be summed by itself since taking the sum requires two values. For compact prosecution, this is interpreted as performing a summation operation that includes the one or more values.
]
[0094] The additive operator 838 adds the correction term BxC (from equation (1), above) to the uncorrected final tag 814 (e.g., the sum of the combined multi-segment tag 802 (Â.sub.M) and a term (A, in equation (1) above) that is added by the end-of-record authentication block 836). This process yields the valid, complete authentication tag 820, which may be understood as having characteristics the same or similar to the complete authentication tag 542 of FIG. 5.
[Note also that Yankilevich discloses combining multiple tags para 91 and 7]
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Langhammer with the technique for utilizing an adder to make a correction to a tag by computing the sum of separate values of Yankilevich to include an adder configurable to receive the one or more values, wherein the adder provides a summation of the one or more values.
One of ordinary skill in the art would have made this modification to improve the ability of the system to make a correction to the authentication tag by adding a correction term to the generated authentication tag. The system of the primary reference can be modified to include an additive operator to add a correction term or other adjustment to an authentication tag to generate a proper tag. The value that is added can also be, for example, one of the operands to the addition operation in the equation at Langhammer 9:42, or can also be one of the hash X that is used to update the register and received again at the authentication pipeline processing block. The claim recites the adder provides a summation of the one, so only one of the authentication tag values is required for the adding, which may involve adding the authentication tag to any other value.
As per claim 7, the rejection of claim 1 is incorporated herein.
Langhammer discloses wherein each of the multiple levels of pipeline stages stores an independent hash sequence.[as each round in authentication pipeline processing block 350 receives the respective hash key values, that, at least over time, creates an independent hash sequence being stored; “may receive a respective hash key value for each authentication round” 3:24-25: storage circuitries for storing a plurality of powers of a first hash key value 3:32-34; if a plurality of powers is stored, that means there is a plurality of hashes being stored also]
Langhammer 3:21-36 (11) In some embodiments, the circuitry further includes an authentication pipeline processing block for performing authentication rounds upon said data block. The authentication pipeline processing block may receive a respective hash key value for each authentication round upon said data block. The circuitry may further include an authentication key pipeline block for providing the respective hash key value for each authentication round upon said data block, by selecting, for each authentication round, the respective hash key value from at least a first hash key value corresponding to the first channel and a second hash key value corresponding to the second channel. The authentication key pipeline block may include a first set of storage circuitries for storing a plurality of powers of a first hash key value corresponding to the first channel and a second set of storage circuitries for storing a plurality of powers of a second hash key value corresponding to the first channel.
`
As per claim 10, Langhammer discloses A method [methods for providing encryption and/or authentication architectures for processing data incoming from multiple channels, 2:33-35] comprising:
decomposing a hash sequence, [in figure 3 there is a H hash sequence and also X hash sequence, these hashes are incoming data from one or more channels, 2:33-35; as shown in the figure, the hash values are organized by 4 powers, e.g. powers (exponents) 0-3, therefore disclosing decomposing ] wherein the hash sequence is decomposed into a sum [all the Langhammer grouped hashes together would be the original hash sequence as shown in figure 3] of multiple independent hash sequences;[ multiple independent hash sequences as seen in figure 3, where the hashes are grouped by 4 powers, e.g. powers (exponents) 0-3]
iteratively performing [repeatedly processed to generate a hash or pre-tag value, 9:25-27; the iteration can also read on X (intermediate hash value 10:16-17) being repeatedly applied to combine with H (10:12-24), and then the output X value is written to the registers such as register circuitry 301a in figure 3] Galois field multiplication operations [this hash function may implement multiplication within the binary Galois field, 9:27-28] using integrated circuitry [may be configured into a programmable integrated circuit device 2:44-45] over a plurality of iterations [repeatedly processed to generate a hash or pre-tag value, 9:25-27] on each of the multiple independent hash sequences;[as shown in figure 3, the groupings of hashes H, and the groupings of hashes X, are input into the authentication pipeline processing block 350]
2:42-45 a scalable and efficient cryptographic architecture may be implemented as circuitry in a fixed logic device, or may be configured into a programmable integrated circuit device
after a first of the plurality of iterations has completed, [authentication round generating intermediate hash (or pre-tag) value X 9:32-33] storing a first output of the first of the plurality of iterations in a first pipeline stage; [the authentication rounds generate the intermediate hash (or pre-tag value) 9:32-37; generating will disclose storing the output (intermediate hash (or pre-tag) value X 9:32-33) at least temporarily until the next round. For example, the authentication round 351 as depicted in FIG. 3 generating intermediate hash, the pre-tag (9:32-33).]
after a second [repeatedly processed to generate a hash or pre-tag value, 9:25-27] of the plurality of iterations has completed, [authentication round generating intermediate hash (or pre-tag) value X 9:32-33] storing a second output of the second of the plurality of iterations in the first pipeline stage [repeatedly processed to generate a hash or pre-tag value, 9:25-27; generating will disclose storing the output (Langhammer intermediate hash (or pre-tag) value X 9:32-33) at least temporarily until the next round.], wherein the first output transitions to a second pipeline stage;[ in Langhammer, to generate the pre-tag, which requires addition and multiplication as shown in any one of the equations 1, 2, or 3 at 9:42, 9:51, and 9:63, respectively, the generated output from each of the rounds must move to the next round in order to generate the final authentication tag 10:8; note that all the information from the various rounds must be assembled (10:4), to generate a final authentication tag (10:7)]
However, Langhammer does not expressly disclose
performing addition operations on the first output and the second output.
Yankilevich discloses an adder [additive operator 838, para 94] to make a correction to a tag by computing the sum of separate values
[0094] The additive operator 838 adds the correction term BxC (from equation (1), above) to the uncorrected final tag 814 (e.g., the sum of the combined multi-segment tag 802 (Â.sub.M) and a term (A, in equation (1) above) that is added by the end-of-record authentication block 836). This process yields the valid, complete authentication tag 820, which may be understood as having characteristics the same or similar to the complete authentication tag 542 of FIG. 5.
[Note also that Yankilevich discloses combining multiple tags para 91 and 7]
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Langhammer with the technique for utilizing an adder to make a correction to a tag by computing the sum of separate values of Yankilevich to include performing addition operations on the first output and the second output.
One of ordinary skill in the art would have made this modification to improve the ability of the system to make a correction to the authentication tag, such as a pre-tag, by adding a correction term to the generated authentication tag. The system of the primary reference can be modified to include an additive operator to add a correction term or other adjustment to an authentication tag to generate a proper tag. The limitation performing addition operations on the first output and the second output under the broadest reasonable interpretation does not require add the first output and the second output together, but rather, this can be interpreted to read that an addition operation is performed on the first output, and another separate addition operation is performed on the second output.
As per claim 11, the rejection of claim 10 is incorporated herein.
Langhammer discloses wherein iteratively performing the Galois field multiplication operations is carried out using programmable logic and digital signal processing (DSP) blocks of a field programmable gate array.
2:33-38 (6) The present disclosure relates to systems and methods for providing encryption and/or authentication architectures for processing data incoming from multiple channels. These architectures can be implemented as circuitry in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD).
13:34-45 (59) various elements of this invention can be provided on in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD) in any desired number and/or arrangement. For example, it should be understood that embodiments of the present invention may be used in numerous types of integrated circuits, including field programmable gate array device (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), digital signal processors (DSPs) and application specific integrated circuits (ASICs).
As per claim 13, the rejection of claim 10 is incorporated herein.
Langhammer discloses where a number of iterations of the plurality of iterations is at least four. [repeatedly processed to generate a hash or pre-tag value, 9:25-27; the iteration can also read on X (intermediate hash value 10:16-17) being repeatedly applied to combine with H (10:12-24), and then the output X value is written to the registers such as register circuitry 301a in figure 3; as shown in figure 3, there appears to be a long stream of hashes which would cause the iteration to be greater than four; also hash value X is repeatedly generated and updated in the registries and re-received to regenerate in authentication pipeline processing block 350, as depicted in figure 3]
As per claim 14, the rejection of claim 13 is incorporated herein.
Langhammer discloses wherein a number of pipeline stages corresponds [as shown in Langhammer figure 3, there are 4 pipeline stages (rounds) 351, 252, 353, and 350 inside authentication pipeline processing block 350, also the word corresponds under broadest reasonable interpretation can be just simply that the pipeline stages have some relationship such as interaction with the multiple independent hash sequences;]
to a number of multiple independent hash sequences.
[a number of multiple independent hash sequences can be disclosed by each independent hash sequence is, for example, X with the same subscript and four different exponents: (no exponent), exponent is 1, exponent is 2, and exponent is 3, as these are input into the authentication pipeline processing block 350 ]
Claim 2-5, 8, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Langhammer in view of Yankilevich, further in view of Filseth et al. U.S. Publication 20100057823 (hereinafter “Filseth”).
As per claim 2, the rejection of claim 1 is incorporated herein.
However, the combination of Langhammer and Yankilevich does not expressly disclose wherein the multiple levels of pipelined stages use a plurality of registers, wherein the plurality of registers operate on different clock cycles.
Filseth discloses pipelining with registers to store intermediate results from one clock cycle to the next
[wherein the plurality of registers operate on different clock cycles is disclosed because as the data moves down the pipeline between the registers, the registers each take turns storing the data at a different clock cycle]
[0072] The overall AES calculation is generally a serial process involving hundreds of levels of logic gates, each depending on the previous level. An integrated circuit (die or chip) in which a non-pipelined AES implementation is embedded may therefore be clocked sufficiently slowly for the entire calculation to finish by the combinational propagation of signals. In some embodiments, the circuitry may be pipelined with registers (or flip-flops) included in the data path to store intermediate results from one clock cycle to the next. The registers may be added in sufficient numbers and optimal positions, depending on the clock period and on when various external control signals become available. As shown in FIG. 5, pipeline registers may be added before each alternate Galois Field inversion and after each matrix 1/D multiplication.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Langhammer and Yankilevich with the technique for pipelining with registers to store intermediate results from one clock cycle to the next of Filseth to include wherein the multiple levels of pipelined stages use a plurality of registers, wherein the plurality of registers operate on different clock cycles.
One of ordinary skill in the art would have made this modification to improve the ability of the system to store intermediate results between the stages of the pipeline to implement the pipeline. The system of the primary reference can be modified to include the registers between the pipeline stages to store intermediate results between pipeline stages.
As per claim 3, the rejection of claim 2 is incorporated herein.
Langhammer discloses wherein the multiple levels of pipelined stages corresponds [as shown in Langhammer figure 3, there are 4 pipeline stages (authentication rounds) 351, 252, 353, and 350 inside authentication pipeline processing block 350, and looking at hashes H or X, there are four powers for each hash; also the word corresponds under broadest reasonable interpretation can be just simply that the pipeline stages have some relationship such as interaction with the plurality of powers] to the plurality of powers of the hash key. [authentication pipeline processing block 350 may receive a hash subkey value H.sub.1 from register circuitry 361a, or a v.sup.th power H.sub.1.sup.v thereof, 10:8-10;10:12-14 The authentication pipeline processing block 350 may receive the hash subkey value or power thereof corresponding to the first channel a; ]
As per claim 4, the rejection of claim 3 is incorporated herein.
Langhammer discloses wherein a number of the plurality of powers of the hash key is four. [as shown in Langhammer figure 3, there are 4 pipeline stages 351, 352, 353, and 354 inside authentication pipeline processing block 350, and looking at hashes H or X, there are four powers for each hash]
As per claim 5, the rejection of claim 4 is incorporated herein.
Langhammer discloses wherein a number of the multiple levels of pipelined stages is four. [as shown in Langhammer figure 3, there are 4 pipeline stages 351, 352, 353, and 354 inside authentication pipeline processing block 350]
As per claim 8, the rejection of claim 2 is incorporated herein.
Langhammer discloses wherein the integrated circuit is implemented in programmable logic and digital signal processing (DSP) blocks of a field programmable gate array.
2:33-38 (6) The present disclosure relates to systems and methods for providing encryption and/or authentication architectures for processing data incoming from multiple channels. These architectures can be implemented as circuitry in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD).
13:34-45 (59) various elements of this invention can be provided on in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD) in any desired number and/or arrangement. For example, it should be understood that embodiments of the present invention may be used in numerous types of integrated circuits, including field programmable gate array device (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), digital signal processors (DSPs) and application specific integrated circuits (ASICs).
As per claim 8, the rejection of claim 2 is incorporated herein.
Langhammer discloses wherein the integrated circuit is implemented in programmable logic and digital signal processing (DSP) blocks of a field programmable gate array.
2:33-38 (6) The present disclosure relates to systems and methods for providing encryption and/or authentication architectures for processing data incoming from multiple channels. These architectures can be implemented as circuitry in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD).
13:34-45 (59) various elements of this invention can be provided on in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD) in any desired number and/or arrangement. For example, it should be understood that embodiments of the present invention may be used in numerous types of integrated circuits, including field programmable gate array device (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), digital signal processors (DSPs) and application specific integrated circuits (ASICs).
As per claim 12, the rejection of claim 10 is incorporated herein.
However, the combination of Langhammer and Yankilevich does not expressly disclose wherein the first pipeline stage uses a first register and the second pipeline stage uses a second register.
Filseth discloses pipelining with registers to store intermediate results from one clock cycle to the next
[wherein the first pipeline stage uses a first register and the second pipeline stage uses a second register is disclosed because as the data moves down the pipeline between the registers, the registers each take turns storing the data at a different clock cycle]
[0072] The overall AES calculation is generally a serial process involving hundreds of levels of logic gates, each depending on the previous level. An integrated circuit (die or chip) in which a non-pipelined AES implementation is embedded may therefore be clocked sufficiently slowly for the entire calculation to finish by the combinational propagation of signals. In some embodiments, the circuitry may be pipelined with registers (or flip-flops) included in the data path to store intermediate results from one clock cycle to the next. The registers may be added in sufficient numbers and optimal positions, depending on the clock period and on when various external control signals become available. As shown in FIG. 5, pipeline registers may be added before each alternate Galois Field inversion and after each matrix 1/D multiplication.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Langhammer and Yankilevich with the technique for pipelining with registers to store intermediate results from one clock cycle to the next of Filseth to include wherein the first pipeline stage uses a first register and the second pipeline stage uses a second register.
One of ordinary skill in the art would have made this modification to improve the ability of the system to store intermediate results between the stages of the pipeline to implement the pipeline. The system of the primary reference can be modified to include the registers between the pipeline stages to store intermediate results between pipeline stages.
Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Langhammer in view of Yankilevich, further in view of Mueller et al. U.S. Publication 20240053963 (hereinafter “Mueller”).
As per claim 6, the rejection of claim 1 is incorporated herein.
However, the combination of Langhammer and Yankilevich does not expressly disclose
wherein the Galois field multiplier comprises polynomial multiplication circuitry and modular reduction circuitry.
Mueller discloses wherein the Galois field multiplier comprises polynomial multiplication circuitry and modular reduction circuitry.
[0005] The present disclosure appreciates that multiple commonly used encryption functions, such as AES (Advanced Encryption Standard)-GCM (Galois Counter Mode) and AES-XTS (XEX-based tweaked-codebook mode with ciphertext stealing), utilize Galois multiplication (i.e., carryless multiplication and modular reduction) to logically combine encryption operands. For example, AES-GCM and AES-XTS both use a Galois multiplication in the GF(2{circumflex over ( )}128) field defined by the fixed polynomial g(x)=1+X+x{circumflex over ( )}2+x{circumflex over ( )}7+x{circumflex over ( )}128. In AES-GCM, Galois multiplications are used to generate a signature for an encrypted message, which can be utilized during decryption to detect whether the ciphertext or signature has been tampered with. In AES-XTS, the Galois multiplications are employed as part of the encryption and decryption of the message itself. The present disclosure discloses various embodiments of circuits for implementing Galois multiplication in hardware and an associated Galois multiplication instruction.
[0053] Galois multiplication, for example, as employed in GCM multiply function 524 of FIG. 5, involves a carryless multiply followed by a modular reduction. For example, in one embodiment, a carryless multiplication of two 128-bit input operands A and B produces a 255-bit product P. Modular reduction modulo polynomial g(x) reduces P to a 128-bit number through an iterative process.
[0056] Given this understanding of the process of modular reduction, reference is now made to FIG. 6, which is a block diagram of a modular reduction circuit 600 for performing modular reduction in the Galois Field with polynomial g(x) in accordance with one embodiment.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Langhammer and Yankilevich with the technique for providing circuitry that implements a Galois field multiplier that includes polynomial multiplication and modular reduction of Mueller to include wherein the Galois field multiplier comprises polynomial multiplication circuitry and modular reduction circuitry.
One of ordinary skill in the art would have made this modification to improve the ability of the system to perform polynomial multiplication and modular reduction, to facilitate encryption and other applications. The system of the primary reference can be modified so that the Galois field multiplier (e.g., authentication pipeline processing block 350) can include the multiplication and modular reduction capabilities.
Claim 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Langhammer in view of Yankilevich, in view of Filseth, further in view of Langhammer ‘318 et al. U.S. Publication 20210216318 (hereinafter “Langhammer ‘318”).
As per claim 9, the rejection of claim 8 is incorporated herein.
However, the combination of Langhammer, Yankilevich, and Filseth does not expressly disclose wherein the DSP blocks of the field programmable gate array comprises the plurality of registers.
Langhammer ‘318 discloses wherein the DSP blocks of the field programmable gate array comprises the plurality of registers [wherein the plurality of DSP blocks comprises at least a portion of the plurality of vector registers., para. 545; digital signal processing (DSP) blocks) that are included in an FPGA., Para. 92 ]
[0092] More specifically, this disclosure discusses vector processing systems (e.g., vector processors) that can be implemented on integrated circuit devices, including programmable logic devices such as field-programmable gate arrays (FPGAs). As discussed herein, the vector processing systems may harness hard logic and soft logic of an FPGA to perform vector processing. As used herein, “hard logic” generally refers to portions of an integrated circuit device (e.g., a programmable logic device) that are not programmable by an end user, and the portions of the integrated circuit device that are programmable by the end user are considered “soft logic.” For example, hard logic elements in an FPGA may include arithmetic units (e.g., digital signal processing (DSP) blocks) that are included in an FPGA and unchangeable by the end user. Vector processing units that perform operations (e.g., vector math operations) may be implemented as hard logic on an FPGA that is able to perform the specific operations at a relatively higher efficiency (e.g., compared to performing the operations using soft logic). Values to be processed, such as vectors or scalars, may be read from and stored in memory that is included in the FPGA. That is, an integrated circuit device may include memory that is a “hard” feature, meaning the memory is included on the integrated circuit device (e.g., when provided to an end user). As also discussed below, routing between the vector processing units and memory may be implemented using a combination of hard logic and soft logic. Accordingly, the techniques described below harness the flexibility of soft logic and hard features (e.g., hard logic and memory blocks) of FPGAs to provide customizable and efficient vector processing architectures capabilities.
[0259] Having discussed various memory considerations the compiler 16 may make, the discussion will now turn to intra-lane connectivity patterns and how the compiler 16 may select which patterns will be used in a hardware implementation of a vector processing system 26. For instance, many applications may involve steps in which results are aggregated across lanes 82 of the vector processing system 26. One example from AI applications may include summing together all of the individual lane results (e.g., performing an additive reduction or accumulation) and then selecting the maximum value across the lanes. Another example is combining elements with a bitwise operation (e.g., XOR to compute a summation in a Galois field) or selectively combining elements (e.g., performing a conditional operation to determine a sum if a corresponding flag is present).
[0545] The integrated circuit device of clause 80, comprising a plurality of digital signal processing (DSP) blocks, wherein the plurality of DSP blocks comprises at least a portion of the plurality of vector registers.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Langhammer, Yankilevich, and Filseth with the technique for including registers within DSP blocks of a field programmable gate array of Langhammer ‘318 to include wherein the DSP blocks of the field programmable gate array comprises the plurality of registers.
One of ordinary skill in the art would have made this modification to improve the ability of the system to utilize registers for storing data in the DSP blocks, to facilitate pipelining. The system of the primary reference can be modified to include registers in the DSP blocks of the field programmable gate array.
Conclusion
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/HOWARD H. LOUIE/Examiner, Art Unit 2494
/JUNG W KIM/Supervisory Patent Examiner, Art Unit 2494
1 Emphasis is additional throughout.