CTNF 18/129,748 CTNF 77038 DETAILED ACTION This communication is in response to the application filed on March 21, 2023 in which claims 1-20 are pending in the application. Claims 1 and 8 are in independent form. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on December 22, 205 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 10 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 10 recites “wherein the first host DC offset is different” there is insufficient antecedent basis for this recitation in the claim. Although the claim recites a first host, there is no prior recitation of a DC offset. Examiner suggest changing the language to “wherein the second host has a DC offset different”. Appropriate correction is required. Claim 11 recites “wherein the second host DC offset is different”, there is insufficient antecedent basis for this recitation in the claim. Although the claim recites a second host, there is no prior recitation of a DC offset. Examiner suggest changing the language to “wherein the second host has a DC offset different”. Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-2, 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mayer et al . (US 2020/0065267 A1) and Gopalakrishnan et al. (US 9847839B2) . As per claim 1 , Mayer discloses an apparatus comprising: a physical interface (PHY) to couple to a data signal line, the data signal line to carry a pulse-amplitude modulation (PAM) signal [ Fig. 1 , PHY 105 coupled to channels 115; Para 0038, 0042 , channels 115 may include one or more data (e.g., DQ) channels 190….The data channels 190 may communicate signals that may be modulated using a variety of different modulations schemes (e.g., NRZ, PAM4) ] having a first data eye at a first voltage reference (Vref) level and a second data eye at a second Vref level [ Fig. 3 , eye diagram 300; Para 0066-0067 , The eye of the eye diagram 300 may refer to the space between the traces 310…to distinguish between different levels when decoding a signal reference voltages 315 , 320 , 325 may be positioned between the different levels represented by the traces. ]; and a control circuit to train the PHY, including to adjust the first Vref level for the first data eye and separately adjust the second Vref level for the second data eye [ Para 0069 , These individual training operations may allow a low-level reference voltage 315 of the first unit interval 305 -a to be positionable independent of the low-level reference voltage 315 of the second unit interval 305 -b and/or positionable independent of a mid level reference voltage 320 or a high-level reference voltage 325 . ; Para 0075 , At 420 , the host device or the memory device may perform one or more baseline training operations; Para 0077 , he host device or memory device may adjust one or more of the reference voltages until an error occurs ]. Mayer discloses the claimed invention as detailed above. Mayer does not specifically teach the PHY including transceiver circuitry as recited in the claim. Gopalakrishnan (US9847839B2) discloses a multi-level PAM transceiver [ Fig. 1 , Col. 5, lines 22-27 , As shown in FIG. 1, transceiver 100 is configured to receive data at a high rate (e.g., 10-20 Gb/s). Data transmitted from transceiver 100 can be in various formats, such as NRZ, PAM4, and/or other formats. ] Both Mayer and Gopalakrishnan are in the same field of endeavor as they are both in the pulse-amplitude modulation (PAM) technique art and, therefore, are combinable/modifiable. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Mayer with the teachings of Gopalakrishnan in order to provide a transceiver that includes an input terminal for receiving input data stream. Modification would improve the system by providing transceivers utilizing an integrated voltage gain amplifier that provides equalization functions, thereby eliminating the needs of a separate equalization module, reducing power consumption, and reducing noise. As per claim 2 , Mayer discloses the apparatus of claim 1, wherein the PAM signal comprises a PAM3 signal having three signal levels and two data eyes [ Para 0048, A multi-symbol modulation scheme may be an example of a M-ary modulation scheme where M is greater than or equal to three…A multi-symbol signal (e.g., a PAM4 signal) may be a signal that is modulated using a modulation scheme that includes at least three levels; Para 0066 , The ‘eye’ of the eye diagram 300 may refer to the space between the traces 310 . As the signals converge toward one of the four levels, areas between the levels may be devoid of traces 310 , which may be referred to as eyes of the eye diagram 300 . ]. As per claim 6, Mayer discloses the apparatus of claim 1, wherein the PHY comprises a PHY of a memory controller [ Fig. 1 , memory controller 105; PHY of a memory controller, Para [0015], [0036], [0105]: External memory controller, PHY implied, Memory controller PHY is present ]. As per claim 7, Mayer discloses the apparatus of claim 1, wherein the PHY comprises a PHY of a graphics dynamic random access memory (DRAM) device [ Fig. 1 , memory device 110; Para [0025], GPU; [0062]; [0032], [0035]: DRAM PHY in general, not limited to graphics, but covers memory device PHY ] . 07-21-aia AIA Claim (s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mayer et al . (US 2020/0065267 A1) and Gopalakrishnan et al. (US 9847839B2) and EOM et al . (US 2022/0093161 A1) . As per claim 3, the combination of Mayer and Gopalakrishnan discloses the claimed invention as detailed above for claim 1. Mayer further discloses Vref training codes for adjusting Vref [ Para 0075, 0084 : Training procedures, individual level offsets, pass window, error-based adjustment; Codes or offsets for Vref are disclosed as part of training ]. Mayer and Gopalakrishnan do not specifically teach wherein to adjust the first Vref level and to adjust the second Vref level comprise computation of reference voltage (Vref) training codes. EOM disclose the apparatus of claim 1, wherein to adjust the first Vref level and to adjust the second Vref level comprise computation of reference voltage (Vref) training codes [ Para 0037 , The DQ driving unit 110 may generate an internal code, based on the above-described code and may generate a reference voltage or a reference voltage set, based on the generated internal code. Codes associated with reference voltages of the plurality of data lines DQ 1 to DQn may be determined in the training process for the memory device 100 . ; Para 0045-0046 ]. Both Mayer and Gopalakrishnan and EOM are in the same field of endeavor as they are both in the memory device operation art and, therefore, are combinable/modifiable. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Mayer and Gopalakrishnan with the teachings of EOM in order to adjust Vref levels based on computation of reference voltage (Vref) training codes. Modification would provide a memory device having improved reliability with optimal data integrity or data-eye for each data line is secured as taught by EOM (Para 0119) As per claim 4, Mayer discloses Shmooing Vref to compute training codes [Para 0077, 0084 : Adjusting Vref until errors occur, finding pass window; "Shmooing" = iterative adjustment as disclosed ]. EOM discloses the apparatus of claim 3, wherein the control circuit is to shmoo a Vref voltage level to compute the Vref training codes [ Para 0037 , The DQ driving unit 110 may generate an internal code, based on the above-described code and may generate a reference voltage or a reference voltage set, based on the generated internal code. Codes associated with reference voltages of the plurality of data lines DQ 1 to DQn may be determined in the training process for the memory device 100 . ; Para 0045-0046 ] . 07-21-aia AIA Claim (s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mayer et al . (US 2020/0065267 A1) and Gopalakrishnan et al. (US 9847839B2) and EOM et al . (US 2022/0093161 A1) and further in view of Choudhary et al . (US 20220318111 A1) . As per claim 5, the combination of Mayer and Gopalakrishnan and EOM discloses the claimed invention as detailed above for claims 1 and 3-4. Mayer further discloses [ Para 0073-0085: Training bursts, patterns for different symbols, iterative adjustment, PRBS not explicit; Iterative per-eye training is disclosed; PRBS is not named but general patterns are used ]. The combination does not explicitly teach the apparatus of claim 4, wherein the control circuit is to iteratively train an upper data eye based on a known data pattern, then iteratively train a lower data eye based on a known data pattern, and then provide a pseudorandom binary sequence to test Vref voltage levels for both the upper data eye and the lower data eye. Choudhary discloses the apparatus of claim 4, wherein the control circuit is to iteratively train an upper data eye based on a known data pattern, then iteratively train a lower data eye based on a known data pattern, and then provide a pseudorandom binary sequence to test Vref voltage levels for both the upper data eye and the lower data eye [ Para 0095-0096 , Describes sequential training of each eye (upper/lower/middle), then using PRBS patterns for overall optimization .] Mayer, Gopalakrishnan , EOM and Choudhary are in the same field of endeavor as they are both in the memory device operation art and, therefore, are combinable/modifiable. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Mayer, Gopalakrishnan and EOM with the teachings of Choudhary in order to optimize the system for high bandwidth and low latency with best performance and power efficiency characteristics as taught by Choudhary (Para 0029) . 07-21-aia AIA Claim (s) 8-13, 15-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkatesan et al. (US 10089256 B2) and Mayer et al . (US 2020/0065267 A1) and Gopalakrishnan et al. (US 9847839B2) . As per claim 8 , Venkatesan discloses a system comprising: a memory controller having: a host physical interface (PHY) including transceiver circuitry to couple to a data signal line [ Fig. 5 , Controller 512 on host side including transmitter 502 coupled to signal line 50; Fig. 12 , Controller 1250 in Processing device 1202; Col. 5 , The dual-mode swing support is on transmission levels at the CPHY (controller side) and MPHY (memory side) ], the data signal line to carry a pulse-amplitude modulation (PAM) signal [ Col. 4, lines 7-17 , dual-mode calibration process ]; and a dynamic random access memory (DRAM) device coupled to the memory controller, the DRAM having: a memory physical interface (PHY) including transceiver circuitry to couple to the data signal line to exchange the PAM signal with the memory controller [ Fig. 5 , Memory device 514 coupled to receiver 504 and Vref calibration controller 550 ; Col. 5 , The dual-mode swing support is on transmission levels at the CPHY (controller side) and MPHY (memory side) ]. Venkatesan discloses the claimed invention as detailed above. Venkatesan does not specifically teach a PAM signal having a first host data eye at a first host voltage reference (Vref) level at the host PHY and a second host data eye at a second host Vref level at the host PHY; a control circuit to train the PHY, including to adjust the first Vref level for the first data eye and separately adjust the second Vref level for the second data eye; the PAM signal having a first DRAM data eye at a first DRAM Vref level at the DRAM PHY and a second DRAM data eye at a second DRAM Vref level at the DRAM PHY. Mayer discloses a PAM signal having a first host data eye at a first host voltage reference (Vref) level at the host PHY and a second host data eye at a second host Vref level at the host PHY [ Fig. 3 , eye diagram 300; Para 0066-0067 , The eye of the eye diagram 300 may refer to the space between the traces 310…to distinguish between different levels when decoding a signal reference voltages 315 , 320 , 325 may be positioned between the different levels represented by the traces. ]; a control circuit to train the PHY, including to adjust the first Vref level for the first data eye and separately adjust the second Vref level for the second data eye [ Para 0069 , These individual training operations may allow a low-level reference voltage 315 of the first unit interval 305 -a to be positionable independent of the low-level reference voltage 315 of the second unit interval 305 -b and/or positionable independent of a mid level reference voltage 320 or a high-level reference voltage 325 . ; Para 0075 , At 420 , the host device or the memory device may perform one or more baseline training operations; Para 0077 , he host device or memory device may adjust one or more of the reference voltages until an error occurs; [0015], [0019], [0036], [0035]: Both host and memory device have PHY and can perform training; Both ends can train independently ]; the PAM signal having a first DRAM data eye at a first DRAM Vref level at the DRAM PHY and a second DRAM data eye at a second DRAM Vref level at the DRAM PHY [ Fig. 3 , eye diagram 300; Para 0066-0067 , The eye of the eye diagram 300 may refer to the space between the traces 310…to distinguish between different levels when decoding a signal reference voltages 315 , 320 , 325 may be positioned between the different levels represented by the traces; [0015], [0019], [0036], [0035]: Both host and memory device have PHY and can perform training; Both ends can train independently. ]. Venkatesan and Gopalakrishnan and Mayer are in the same field of endeavor as they are both in the pulse-amplitude modulation (PAM) technique art and, therefore, are combinable/modifiable. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Venkatesan and Meyer to provide PAM having data eye for each Vref level because it would have allowed the system to use the eye diagram to identify different characteristics of communication signals as taught by Mayer (Para 0065). Venkatesan and Meyer disclose the claimed invention as detailed above. Venkatesan and Meyer do not specifically teach the PHY including transceiver circuitry as recited in the claim. Gopalakrishnan (US9847839B2) discloses a multi-level PAM transceiver [ Fig. 1 , Col. 5, lines 22-27 , As shown in FIG. 1, transceiver 100 is configured to receive data at a high rate (e.g., 10-20 Gb/s). Data transmitted from transceiver 100 can be in various formats, such as NRZ, PAM4, and/or other formats. ] Venkatesan, Meyer and Gopalakrishnan are in the same field of endeavor as they are both in the pulse-amplitude modulation (PAM) technique art and, therefore, are combinable/modifiable. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Venkatesan and Mayer with the teachings of Gopalakrishnan in order to provide a transceiver that includes an input terminal for receiving input data stream. Modification would improve the system by providing transceivers utilizing an integrated voltage gain amplifier that provides equalization functions, thereby eliminating the needs of a separate equalization module, reducing power consumption, and reducing noise. As per claim 9 , Mayer discloses the system of claim 8, wherein the PAM signal comprises a PAM3 signal having three signal levels and two data eyes [ Para 0048, A multi-symbol modulation scheme may be an example of a M-ary modulation scheme where M is greater than or equal to three…A multi-symbol signal (e.g., a PAM4 signal) may be a signal that is modulated using a modulation scheme that includes at least three levels; Para 0066 , The ‘eye’ of the eye diagram 300 may refer to the space between the traces 310 . As the signals converge toward one of the four levels, areas between the levels may be devoid of traces 310 , which may be referred to as eyes of the eye diagram 300 . ]. As per claim 10 , Mayer discloses the system of claim 8, wherein the first host DC offset is different in magnitude from the first DRAM Vref level [ Para 0084 , a first individual level training operation may be used to determine a first individualized level offset for the first reference voltage 315 found in the first unit interval 305 -a and a second individual level training operation may be used to determine a second individualized level offset for the second reference voltage 320 found in the first unit interval 305 -a; Para 0087 : Individual level offsets per device/unit interval; Per-device/unit interval offsets supported.] . As per claim 11 , Mayer discloses the system of claim 8, wherein the second host DC offset is different in magnitude from the second DRAM Vref level [ Para 0084 , a first individual level training operation may be used to determine a first individualized level offset for the first reference voltage 315 found in the first unit interval 305 -a and a second individual level training operation may be used to determine a second individualized level offset for the second reference voltage 320 found in the first unit interval 305 -a; Para 0087 : Individual level offsets per device/unit interval; Per-device/unit interval offsets supported.] . As per claim 12 , Mayer discloses the system of claim 8, wherein to adjust the first host Vref level and to adjust the second host Vref level comprise computation of reference voltage (Vref) training codes for the host PHY [ Para 0075, 0084 , 0085 , Host PHY training is disclosed ]. As per claim 13 , Mayer discloses the system of claim 12, wherein the control circuit is to shmoo a Vref voltage level to compute the Vref training codes for the host PHY [Para 0077, 0084 : Adjusting Vref until errors occur, finding pass window; "Shmooing" = iterative adjustment as disclosed ]. As per claim 15 , Mayer discloses the system of claim 8, wherein to adjust the first DRAM Vref level and to adjust the second DRAM Vref level comprise computation of reference voltage (Vref) training codes for the DRAM PHY [ Para 0084, 0087 : Training may be performed by memory device; DRAM PHY training is supported ]. As per claim 16 , Mayer discloses the system of claim 15, wherein the control circuit is to shmoo a Vref voltage level to compute the Vref training codes for the DRAM PHY [Para 0077, 0084 : Adjusting Vref until errors occur, finding pass window; "Shmooing" = iterative adjustment as disclosed ]. As per claim 17 , Mayer discloses the system of claim 16, wherein the memory controller is to iteratively send a known data pattern to the DRAM device, and the DRAM device is to reply to the memory controller with error signals, wherein the control circuit of the memory controller is to compute the Vref training codes for the DRAM PHY in response to the error signals [Para 0090, 0091]: Feedback/error signals used for training; Host-assisted DRAM training with error feedback]. As per claim 20 , Mayer discloses the system of claim 15, wherein the control circuit comprises a host control circuit, the DRAM device comprising: a DRAM control circuit to shmoo a Vref voltage level to compute the Vref training codes for the DRAM PHY [ Para 0035, 0084 : Both host and memory device can have controllers for training | Y | Both ends can perform training ] . 07-21-aia AIA Claim (s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkatesan et al. (US 10089256 B2) and Mayer et al . (US 2020/0065267 A1) and Gopalakrishnan et al. (US 9847839B2) and further in view of Cho et al. (US 20210159271 A1) . As per claim 18 , the combination of Venkatesan, Mayer and Gopalakrishnan discloses the claimed invention as detailed above for claim 1. Mayer further discloses [ Para 0090 : Feedback/error signals, not specifically different DQ lines; Feedback channel is disclosed, may not specify separate DQ, but concept is present ]. Venkatesan, Mayer and Gopalakrishnan do not specifically teach the system of claim 17, wherein the DRAM device is to receive the known data pattern on a first data (DQ) signalline, and reply to the memory controller with the error signals on a second DQ signalline different from the first DQ signalline Cho discloses the DRAM device is to receive the known data pattern on a first data (DQ) signal line, and reply to the memory controller with the error signals on a second DQ signal line different from the first DQ signal line [ Transmit LFSR as known pattern and receives LFSR as expected pattern; DQ write path electrically connected to read path; Error reported as status bits] The combination does not teach different DQ line requirement. Dean-Dexter discloses [Data received on a DQ input can be forwarded to loopback output pins (LBDQ_o), input in one DQ output on different DQ (loopback output pins); No need for a read command; response is immediate to controller/tester; Loopback path is selectable via muxes across different DQ signal paths] . 07-21-aia AIA Claim (s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkatesan et al. (US 10089256 B2) and Mayer et al . (US 2020/0065267 A1) and Gopalakrishnan et al. (US 9847839B2) and further in view of Dean-Dexter et al. (US 11662926 B2) . As per claim 19 , the combination of Venkatesan, Mayer and Gopalakrishnan discloses the claimed invention as detailed above for claim 1. Mayer further discloses Para 0090 : Feedback/error signals, not specifically different DQ lines. Venkatesan, Mayer and Gopalakrishnan do not specifically teach the system of claim 17, wherein the DRAM device is to receive the known data pattern on a data (DQ) signalline, and reply to the memory controller with the error signals on a loopback signal line associated with the DQ signalline. Dean-Dexter discloses wherein the DRAM device is to receive the known data pattern on a data (DQ) signal line, and reply to the memory controller with the error signals on a loopback signal line associated with the DQ signal line [ Para 0048, 0055 : Loopback per DQ for training; Loopback per DQ is present (see Figs. 2, 3, 4, 7, 8)]. Venkatesan, Meyer and Gopalakrishnan are in the same field of endeavor as they are both in the memory and controller interaction art and, therefore, are combinable/modifiable. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Venkatesan, Mayer and Gopalakrishnan with the teachings of Dean-Dexter in order to reduce execution time by removing the need to issue multiple Read commands from the memory array, and can remove the requirement for issuing and managing memory refresh commands as taught by Dean-Dexter (Para 0027) . 07-21-aia AIA Claim (s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkatesan et al. (US 10089256 B2) and Mayer et al . (US 2020/0065267 A1) and Gopalakrishnan et al. (US 9847839B2) and further in view of Choudhary et al . (US 20220318111 A1) . As per claim 14 , the combination of Venkatesan, Mayer and Gopalakrishnan discloses the claimed invention as detailed above for claims 8 and 12-13. Mayer further discloses [ Para 0073-0085: Training bursts, patterns for different symbols, iterative adjustment, PRBS not explicit; Iterative per-eye training is disclosed; PRBS is not named but general patterns are used ]. The combination does not explicitly teach the apparatus of claim 13, wherein the control circuit is to iteratively train an upper host data eye based on a known data pattern, then iteratively train a lower host data eye based on a known data pattern, and then provide a pseudorandom binary sequence to test Vref voltage levels for both the upper host data eye and the lower host data eye. Choudhary discloses the apparatus of claim 13, wherein the control circuit is to iteratively train an upper host data eye based on a known data pattern, then iteratively train a lower host data eye based on a known data pattern, and then provide a pseudorandom binary sequence to test Vref voltage levels for both the upper host data eye and the lower host data eye [ Para 0095-0096 , Describes sequential training of each eye (upper/lower/middle), then using PRBS patterns for overall optimization .] Venkatesan, Mayer, Gopalakrishnan and Choudhary are in the same field of endeavor as they are both in the memory device operation art and, therefore, are combinable/modifiable. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Venkatesan, Mayer, Gopalakrishnan with the teachings of Choudhary in order to optimize the system for high bandwidth and low latency with best performance and power efficiency characteristics as taught by Choudhary (Para 0029) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park (US 2022/0270665 A1) teaches The memory controller exchanges data with the semiconductor memory device by controlling the memory interface. The memory interface includes a training circuit to perform duty training of first data signals and second data signals by adjusting a duty of each of the first data signals with respect to a first reference voltage and adjusting a duty of each of the second data signals with respect to a second reference voltage (Abstract). Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c). When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Pierre M. Vital whose telephone number is (571)272-4215. The examiner can normally be reached Mon-Fri, 8:00a-4:00p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dede Zecher can be reached at (571) 272-7771. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. 5/2/2026 /PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198 Application/Control Number: 18/129,748 Page 2 Art Unit: 2198 Application/Control Number: 18/129,748 Page 3 Art Unit: 2198 Application/Control Number: 18/129,748 Page 5 Art Unit: 2198 Application/Control Number: 18/129,748 Page 6 Art Unit: 2198 Application/Control Number: 18/129,748 Page 7 Art Unit: 2198 Application/Control Number: 18/129,748 Page 8 Art Unit: 2198 Application/Control Number: 18/129,748 Page 9 Art Unit: 2198 Application/Control Number: 18/129,748 Page 10 Art Unit: 2198 Application/Control Number: 18/129,748 Page 11 Art Unit: 2198 Application/Control Number: 18/129,748 Page 12 Art Unit: 2198 Application/Control Number: 18/129,748 Page 13 Art Unit: 2198 Application/Control Number: 18/129,748 Page 14 Art Unit: 2198 Application/Control Number: 18/129,748 Page 15 Art Unit: 2198 Application/Control Number: 18/129,748 Page 16 Art Unit: 2198 Application/Control Number: 18/129,748 Page 17 Art Unit: 2198 Application/Control Number: 18/129,748 Page 18 Art Unit: 2198
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