CTNF 18/130,410 CTNF 81222 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 07-29 AIA 2. The disclosure is objected to because of the following informalities: paragraph 12, line 1 of page 4 recites “PASID” which should be corrected to “process address space identifier (PASID)” . Appropriate correction is required. Claim Objections 3. Claim 7 is objected to because of the following informalities: line 1 recites “PASID” which should be corrected to “process address space identifier (PASID)”. 07-29-01 AIA Claim 20 is objected to because of the following informalities: line 2 recites “IPUs” which should be corrected to “infrastructure processing unit (IPUs)” . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 5. Claim s 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran et al. (US Publication Number 2018/0011651, hereinafter “Sankaran”) in view of Cornett et al. (US Publication Number 2020/0210359, hereinafter “Cornett”) . 6. As per claim 1, Sankaran teaches an apparatus, comprising: a memory management unit (IOMMU, paragraph 20), the memory management unit to receive a memory access request from an accelerator (IOMMU with respect to accelerator, paragraph 31), wherein the memory access request includes a virtual address of a data provided by an application (virtual address for memory request, paragraphs 31, 43, and 68 – 70) that invokes the accelerator to perform a function on the data, wherein, the memory access request also includes an identifier of the application's CPU process (PASID, paragraph 63), the memory management unit to translate the virtual address to a physical address to fetch the data from a location allocated to the application within a memory (figure 4, translation request handling via translation structures, paragraph 58 – 62). Sankaran does not appear to explicitly disclose the data structure is termed a payload, wherein the memory access request includes a virtual address of a payload provided by an application that invokes the accelerator to perform a function on the payload However, Cornett discloses wherein the memory access request includes a virtual address of a payload provided by an application that invokes the accelerator to perform a function on the payload (data exchange packets considered as payload, paragraph 36). Sankaran and Cornett are analogous art because they are from the same field of endeavor data packet processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Sankaran and Cornett before him or her, to modify the memory handling of Sankaran to include the payload flexibility of Cornett because it would enhance memory management. One of ordinary skill would be motivated to make such modification in order to address latency concerns in a parallel processing environment (paragraph 21). Therefore, it would have been obvious to combine Cornett with Sankaran to obtain the invention as specified in the instant claims. 7. As per claim 8, Sankaran an apparatus, comprising: an accelerator (accelerator, paragraph 31), the accelerator to receive a first identifier of an operation to be performed for an application by the accelerator (applications 104, figure 1, paragraph 27), a second identifier of the application's CPU process (PASID, paragraph 49), and a virtual address (virtual address, paragraph 31) used by the application to refer to the operation's data, the accelerator to pass a request to a memory management unit that includes the second identifier and the virtual address (virtual address for memory request, paragraphs 43, and 68 – 70), the request to cause the memory management unit to translate the virtual address to a physical address for the data within a region of a memory allocated to the application (figure 4, translation request handling via translation structures, paragraph 58 – 62). Sankaran does not appear to explicitly disclose the data structure is termed a payload. However, Cornett discloses wherein the data structure is termed a payload (data exchange packets considered as payload, paragraph 36). Sankaran and Cornett are analogous art because they are from the same field of endeavor data packet processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Sankaran and Cornett before him or her, to modify the memory handling of Sankaran to include the payload flexibility of Cornett because it would enhance memory management. One of ordinary skill would be motivated to make such modification in order to address latency concerns in a parallel processing environment (paragraph 21). Therefore, it would have been obvious to combine Cornett with Sankaran to obtain the invention as specified in the instant claims. 8. As per claim 15, Sankaran teaches a data center comprising: a CPU pool (CPU pool 201, figure 2); an application to execute on a process of the CPU pool (application 104 a…n, figure 1); a memory pool (memory pages, paragraphs 26 and 27); and, an acceleration pool comprising an accelerator (accelerator, paragraph 31), the accelerator to receive a first identifier of an operation to be performed for the application by the accelerator (applications 104, figure 1, paragraph 27), a second identifier of the application's CPU process (PASID, paragraph 49), and a virtual address (virtual address, paragraph 31) used by the application to refer to the operation's data, the accelerator to pass a request to a memory management unit that includes the second identifier and the virtual address (virtual address for memory request, paragraphs 43, and 68 – 70), the request to cause the memory management unit to translate the virtual address to a physical address for the data within a region of the memory pool allocated to the application (figure 4, translation request handling via translation structures, paragraph 58 – 62). Sankaran does not appear to explicitly disclose a network; a CPU pool coupled to the network; an application to execute on a process of the CPU pool; a memory pool coupled to the network; and, an acceleration pool coupled to the network and the data structure is termed a payload. However, Cornett discloses wherein a network (network 820, figure 8); a CPU pool coupled to the network (processors 710, coupled to network interface, paragraph 59); an application to execute on a process of the CPU pool; a memory pool coupled to the network (memory 730, coupled to interface, paragraph 61); and, an acceleration pool coupled to the network (accelerators 742 coupled to network interface, paragraph 63) and the data structure is termed a payload (data exchange packets considered as payload, paragraph 36). Sankaran and Cornett are analogous art because they are from the same field of endeavor data packet processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Sankaran and Cornett before him or her, to modify the memory handling of Sankaran to include the payload flexibility of Cornett because it would enhance memory management. One of ordinary skill would be motivated to make such modification in order to address latency concerns in a parallel processing environment (paragraph 21). Therefore, it would have been obvious to combine Cornett with Sankaran to obtain the invention as specified in the instant claims. 9. Sankaran modified by the teachings of Cornett as seen in claim 1 above, as per claim 2, Sankaran teaches an apparatus, wherein the memory management unit is to process (paragraph 34), during the memory management unit's configuration, a page (211, figure 2) within the memory (paragraph 26) that includes the identifier of the application's CPU process and virtual to physical address translation information for the application (paragraphs 32, 33, and 34). 10. Sankaran modified by the teachings of Cornett as seen in claim 1 above, as per claims 3, 10, and 17, Sankaran teaches an apparatus and data center wherein the memory management unit is an I/O memory management unit (IOMMU) (IOMMU, paragraph 34). 11. Sankaran modified by the teachings of Cornett as seen in claim 1 above, as per claims 4 and 11, Cornett teaches an apparatus, wherein the memory management unit is within a same semiconductor chip package as the accelerator (structural configuration, paragraph 69). 12. Sankaran modified by the teachings of Cornett as seen in claim 1 above, as per claims 5 and 12, Cornett teaches an apparatus, wherein the accelerator is a component of a network interface card (NIC) (150, figure 2). 13. Sankaran modified by the teachings of Cornett as seen in claim 1 above, as per claims 6, 13, and 18, Cornett teaches an apparatus and data center wherein the accelerator includes circuitry to perform compression/decompression (compression, paragraph 60). 14. Sankaran modified by the teachings of Cornett as seen in claim 1 above, as per claim 7, Sankaran teaches an apparatus, wherein the application's CPU process is identified with a PASID (PASID, paragraph 53). 15. Sankaran modified by the teachings of Cornett as seen in claim 1 above, as per claims 9 and 16, Cornett teaches an apparatus and data center, wherein the accelerator comprises register space to store the first identifier, the second identifier and the virtual address (paragraph 60, memory structures associated with the accelerator). 16. Sankaran modified by the teachings of Cornett as seen in claim 1 above, as per claims 14 and 19, Cornett teaches an apparatus and data center wherein the accelerator includes circuitry to perform at least one of encryption/decryption and compression/decompression in response to a single invocation (encryption/decryption, compression, paragraph 60). 17. Sankaran modified by the teachings of Cornett as seen in claim 1 above, as per claim 20, Sankaran teaches a data center wherein the CPU pool, memory pool and acceleration pool are coupled to the network through respective IPUs (interfacing processors via 710/712, figure 7) . Conclusion 07-96 AIA 18. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Benisty/Hayes/Pawlowski/Guim/Liu teaches memory management and accelerators utilized in a networked environment . Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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AH /HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184 Application/Control Number: 18/130,410 Page 2 Art Unit: 2184 Application/Control Number: 18/130,410 Page 3 Art Unit: 2184 Application/Control Number: 18/130,410 Page 4 Art Unit: 2184 Application/Control Number: 18/130,410 Page 5 Art Unit: 2184 Application/Control Number: 18/130,410 Page 6 Art Unit: 2184 Application/Control Number: 18/130,410 Page 7 Art Unit: 2184 Application/Control Number: 18/130,410 Page 8 Art Unit: 2184
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