DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species A, in the reply filed on December 17, 2025 is acknowledged. The traversal is on the grounds that the asserted species are not mutually exclusive. Examiner agrees and accordingly withdraws the requirement for Applicant to elect a single species.
Applicant made no arguments about the requirement to elect a single invention from Groups I, II, and III. The requirement to elect a single invention is deemed proper and is therefore made FINAL.
Applicant elected Group I, corresponding to claims 1-13. Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, it is unclear to Examiner what exactly is being claimed. If the second surface is the surface of the integrated circuit package that contacts the upper surface of the card substrate, how is the first surface exposed on the upper surface of the card substrate and the surface on which the plurality of package terminals are exposed?
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 7, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hiew et al. (US 2008/0286990 A1) in view of Gao et al. (CN 111723029 A), hereinafter Hiew and Gao, respectively.
Regarding claim 1, Hiew teaches a memory card (SD device 100) comprising:
a case (casing 150) compliant with a first standard, corresponding to a first protocol (from paragraph 0062: “[M]olded casing 150 has a length L, a width W and a front-end thickness T that are determined according to predetermined standards [e.g., SD or MMC standards].”);
a card substrate (PCB 111) embedded in the case (150);
a plurality of external contact terminals (metal contacts 120) corresponding to the first standard (from paragraph 0059: “Metal contacts 120 are shaped and arranged in a pattern established by the SD specification.”) on an upper surface (upper surface 112) of the card substrate (111; the embodiment shown in Figs. 23-29 has metal contacts 120D disposed on the upper surface 112 of PCB 111), the external contact terminals (120) having at least a portion exposed outwardly of the case (from paragraph 0059: Metal contacts 120 … are exposed through openings 157 defined in molded casing 150.”); and
an integrated circuit package (controller IC die 130 and flash memory dies 135; see paragraph 0109 stating that the controller and flash memories may be fully packaged) attached to the upper surface (112) of the card substrate (111), the integrated circuit package (130 and 135) including a plurality of package terminals (terminals are inherent in any packaged IC),
wherein first external contact terminals among the plurality of external contact terminals (120) are electrically connected to first package terminals among the plurality of package terminals (from paragraph 0061: “IC dies 130 and 135 and metal contacts 120 are operably interconnected by way of metal traces 131 and 136.”)
Hiew lacks the teaching that the integrated circuit package terminals correspond to a
second protocol.
Gao teaches a memory card (memory card 10), compliant with a micro-SD standard (see Figs. 5-6; see also pg. 3, paragraph 5) and SD communication protocol (see pg. 3, paragraph 1), that includes an integrated circuit package (control chip 122) capable of communicating in UFS protocol (see pg. 6, paragraph 11).
Hiew and Gao are considered to be analogous arts because they are in the same field of endeavor as the claimed invention. Therefore it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the present application, to modify the memory card taught by Hiew to include another integrated circuit package capable of communicating in UFS protocol so that the memory card can interface with a host device in either SD protocol or UFS protocol (see Gao pg. 2, paragraph 3). Alternatively, it would also be obvious to modify the memory card of Hiew so that the integrated circuit package and its terminals are capable of communicating in UFS protocol. Doing so would allow the memory card to interface with a host device in UFS protocol even if the host device’s card slot is not sized to fit a standard UFS card (see Gao pg. 2, paragraph 1).
Regarding claim 7, Hiew in view of Gao teaches all of the limitations of claim 1 as
stated above. Hiew in view of Gao further teaches the memory card as claimed in claim 1, wherein:
the first standard is a standard of a secure digital (SD) card (Hiew: from paragraph 0062: “[M]olded casing 150 has a length L, a width W and a front-end thickness T that are determined according to predetermined standards [e.g., SD or MMC standards].”),
the first protocol is an SD bus protocol (Hiew: from paragraph 0059: “Metal contacts 120 are shaped and arranged in a pattern established by the SD specification.”; Gao: see pg. 3, paragraph 1), and
the second protocol is a universal flash storage (UFS) protocol (Gao: see pg. 6, paragraph 11).
Regarding claim 9, Hiew in view of Gao teaches all of the limitations of claim 1 as
stated above. Hiew in view of Gao further teaches the memory card as claimed in claim 1, wherein the external contact terminals (Hiew: 120) include:
first to eighth external contact terminals aligned in a first direction, parallel to the upper surface of the card substrate (see annotated Fig. 25 below); and
a ninth external contact terminal disposed in a direction opposite to the first direction with respect to the first external contact terminal, the ninth external contact terminal having a position that is different from positions of the first to eighth external contact terminals in a second direction parallel to the upper substrate and perpendicular to the first direction (see annotated Fig. 25 below).
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Regarding claim 10, Hiew in view of Gao teaches all of the limitations of claim 9 as stated above. Hiew in view of Gao further teaches that the first package terminals of its integrated circuit package (Gao: 122) include: power supply terminals, a clock terminal, differential signal input terminals, differential signal output terminals, and a hardware reset signal terminal. The integrated circuit package (Gao: 122) is designed to communicate in UFS protocol (Gao: see pg. 6, paragraph 11), so it would need to contain power supply terminals, a clock terminal, differential signal input terminals, differential signal output terminals, and a hardware reset signal terminal in order to communicate in UFS protocol.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Hiew in view of Gao as applied to claim 1 above, and further in view of Lee et al. (US 9,859,660 B2), hereinafter Lee.
Regarding claim 2, Hiew in view of Gao teaches all of the limitations of claim 1 as stated above. Hiew in view of Gao further teaches the memory card as claimed in claim 1, further comprising:
package-side terminals (Hiew: contact pads 119-51 and 119-61) on the upper surface (Hiew: 112) of the card substrate (Hiew: 111); and
interconnection patterns (Hiew: conductive traces 131 and 136) configured to electrically connect the first external contact terminals (Hiew: 120) and the package-side terminals (Hiew: 119-51 and 119-61) to each other, and
wherein the package-side terminals (Hiew: 119-51 and 119-61) and the first package terminals are electrically connected to each other through wires (Hiew: from paragraph 0098: “[C]ontrol IC die 130 [] is connected to contact pads 119-51 by way of wire bonds 180-1, and … flash memory IC dies 135-1 and 135-2 [] are connected to contact pads 199-61 by way of wire bonds 180-1 and 180-2.”).
Hiew in view of Gao lacks the specific teaching that the interconnection patterns are
disposed on the upper surface of the card substrate. Hiew discloses that the interconnection patterns are “sandwiched between multiple layers of an insulating material” (Hiew, paragraph 0060), and Gao is silent with respect to interconnection patterns.
Lee teaches a memory card adaptor (100a) with interconnection patterns (wiring lines 130) disposed on an upper surface (second layer 150b) of a card substrate (PCB 150; see Fig. 8).
Lee is considered to be analogous art because it is in the same field of endeavor as the claimed invention. Therefore it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the present application, to place the interconnection patterns on the upper surface of the card substrate. Placing the interconnection patterns on an upper surface of the card substrate would have been an obvious matter of design choice since Applicant has not disclosed that this solves any stated problem, or is for any particular purpose, and it appears that the invention would perform equally well regardless of where the interconnection patterns are disposed.
Regarding claim 3, Hiew and Gao in view of Lee teaches all of the claim 2 as stated above. In light of the above-mentioned 112(b) issue, Hiew and Gao in view of Lee further teaches the memory card as claimed in claim 2, wherein:
the integrated circuit package (Hiew: 130 and 135) has a first surface, on which the plurality of package terminals are exposed (Hiew: see Fig. 26 showing the top surfaces of 130 and 135 exposing package terminals), and a second surface (Hiew: the bottom surfaces of 130 and 135) on an opposite side of the first surface, and
the second surface contacts the upper surface of the card substrate, and the first surface is exposed on the upper surface of the card substrate (Hiew: see Fig. 26 showing the bottom surfaces of 130 and 135 contacting the upper surface of the PCB and the top surfaces of 130 and 135 exposed).
Regarding claim 4, Hiew in view of Gao teaches all of the limitations of claim 1 as
stated above. Hiew in view of Gao further teaches the memory card as claimed in claim 1, wherein:
the memory card includes package-side terminals (Hiew: contact pads 119-51 and 119-61) on the upper surface (Hiew: 112) of the card substrate (Hiew: 111);
interconnection patterns (Hiew: conductive traces 131 and 136) configured to electrically connect the first external contact terminals (Hiew: 120) and the package-side terminals (Hiew: 119-51 and 119-61) to each other, and
the package-side terminals (Hiew: 119-51 and 119-61) and the first package terminals are soldered to each other to be electrically connected to each other (Hiew: see paragraph 0109 stating that the controller and flash memories may be fully packaged and mounted onto the PCB using standard surface mount technology [SMT] techniques; see paragraph 0061 describing how soldering is part of an SMT process).
Hiew in view of Gao lacks the specific teaching that the interconnection patterns are
disposed on the upper surface of the card substrate. Hiew discloses that the interconnection patterns are “sandwiched between multiple layers of an insulating material” (Hiew, paragraph 0060), and Gao is silent with respect to interconnection patterns.
Lee teaches a memory card adaptor (100a) with interconnection patterns (wiring lines 130) disposed on an upper surface (second layer 150b) of a card substrate (PCB 150; see Fig. 8).
It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the present application, to place the interconnection patterns on the upper surface of the card substrate. Placing the interconnection patterns on an upper surface of the card substrate would have been an obvious matter of design choice since Applicant has not disclosed that this solves any stated problem, or is for any particular purpose, and it appears that the invention would perform equally well regardless of where the interconnection patterns are disposed.
Regarding claim 5, Hiew and Gao in view of Lee teaches all of the limitations of claim 4 as stated above. Hiew and Gao in view of Lee further teaches the memory card as claimed in claim 4, wherein:
the integrated circuit package (Hiew: 130 and 135) includes a first surface on which the plurality of package terminals of the integrated circuit package are exposed (Hiew: see Fig. 26 showing the top surfaces of 130 and 135 exposing package terminals), the first surface opposing the upper surface of the card substrate (Hiew: see Fig. 26 showing the top surfaces of 130 and 135 are opposite upper side 112 of PCB 111), and
the package-side terminals (Hiew: specifically contact pads 119-51) are disposed in same positions as the plurality of package terminals in a first direction, parallel to the upper surface of the card substrate, and in a second direction intersecting the first direction (see annotated Fig. 25 below showing contact pads 119-51 arranged in two perpendicular directions).
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Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hiew and Gao in view of Lee as applied to claim 4 above, and further in view of Maeda et al. (US 2001/0025721 A1), hereinafter Maeda.
Hiew and Gao in view of Lee teaches all of the limitations of claim 4 as stated above. Hiew and Gao in view of Lee lack the specific teaching that the interconnection patterns are insulated from the integrated circuit package. Hiew does teach that its interconnection patterns (130) are “sandwiched between multiple layers of an insulating material” (Hiew, paragraph 0060). However as modified by Lee, its interconnection patterns are now arranged on an upper surface of the card substrate.
Maeda teaches a memory card (IC card module 10) with interconnection patterns (wiring 12) connecting external contact terminals (terminals 18) to an integrated circuit package (semiconductor devices 13, wires 14, resin 16, and connection lands 20). Solder resist covers the entire top surface of a card substrate (printed wiring board 11) except for the external contact terminals (18), lands (19), and connection lands (20; see paragraph 0059).
Maeda is considered to be analogous art because it is in the same field of endeavor as the claimed invention. Therefore it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the present application, to cover the upper surface of the PCB in solder resist to insulate the interconnection patterns from the integrated circuit package. Doing so would help to prevent short circuits.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hiew in view of Gao as applied to claim 7 above, and further in view of Lee et al. (US 9,893,484 B2), hereinafter Lee II.
Hiew in view of Gao teaches all of the limitations of claim 7 as stated above. It is Examiner’s understanding that a standard SD card contains nine terminals, eight of which correspond to the eight terminals of a micro SD card. A standard SD card contains two ground terminals (terminals 3 and 6), however, and a micro SD card contains only one ground terminal (terminal 6). Thus Hiew in view of Gao teaches that the first external contact terminals (terminals 1-2 and 4-9) correspond to a micro SD card standard.
Hiew in view of Gao lacks the specific teaching that, among the plurality of external contact terminals, remaining terminals other than first external contact terminals are insulated from the integrated circuit package.
Lee II teaches a memory card adaptor (100), designed for adapting a UFS card (memory card 10) to a standard SD card form factor, where terminal 3 of the memory card adaptor is insulated from the UFS card (see Fig. 3 showing terminal 3 unconnected).
Lee II is considered to be analogous art because it is in the same field of endeavor as the claimed invention. Therefore it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the present application, to insulate terminal 3 from the integrated circuit package to prevent short circuits.
Claim 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hiew in view of Gao as applied to claim 10 above, and further in view of Hershko et al. (US 9,137,335 B2), hereinafter Hershko.
Regarding claim 11, Hiew in view of Gao teaches all of the limitations of claim 10 as stated above. Hiew in view of Gao lacks the specific teaching that the first and ninth external contact terminals are connected to the differential signal input terminals, the second external contact terminal is connected to the hardware reset signal terminal, the fourth and sixth external contact terminals are connected to the power supply terminals, the fifth external contact terminal is connected to the clock terminal, and the seventh and eighth external contact terminals are connected to the differential signal output terminals.
Hershko discloses using a UFS storage system in conjunction with a memory card having an SD form factor (see Fig. 2E; see col. 10, lines 56-58). First and ninth external contact terminals are mapped to differential signal output, a second external contact terminal is mapped to an optional command response, fourth and sixth external contact terminals are mapped to power supply, a fifth external contact terminal is mapped to clock, and seventh and eight external contact terminals are mapped to differential signal input (see Figs. 2B and 2E, and also Table 4).
Hershko is considered to be analogous art because it is in the same field of endeavor as the claimed invention. Therefore it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the present application, to connect the fourth and sixth external contact terminals to the power supply terminals and the fifth external contact terminal to the clock terminal in order to preserve the purpose of these terminals (see col. 6, lines 65-66; see col. 11, lines 16-21). It would be obvious to connect the second external contact terminal to the hardware reset signal terminal so that there is a way to perform a reset. It would also be obvious to connect the first and ninth external contact terminals to differential signal input terminals and the seventh and eight external contact terminals to the differential signal output terminals. Hershko teaches that “any pins on the memory card form factor can be repurposed to carry the transmitter and receiver differential pairs … [a]s a matter of design choice, it makes more sense to repurpose the data pins from the memory card form factors to act as transmitter and receiver differential pairs.” (see col. 11, lines 8-13). Hershko suggests that there is no particular reason why first and ninth external contact terminals are mapped to differential output rather than differential input, and only notes that it is important that the two terminals of each differential pair are proximate one another while each distinct differential pair is separate from one another (see col. 8, lines 5-12).
Regarding claim 13, Hiew and Gao in view of Hershko teaches all of the limitations of claim 11 as stated above. Hiew and Gao in view of Hershko further teaches the memory card as claimed in claim 11, wherein the power supply terminals include: a first power supply terminal (Hershko: Pin 4) connected to a main power supply of the integrated circuit package (Hershko: see Fig. 2A and Table 4 showing Pin 4 connected to Supply); and a second power supply terminal (Hershko: Pin 6) connected to a ground of the integrated circuit package (see Fig. 2A and Table 4 showing Pin 6 connected to Ground).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hiew and Gao in view of Hershko as applied to claim 11 above, and further in view of Lee II.
Hiew and Gao in view of Hershko teaches all of the limitations of claim 11 as stated above. Hiew and Gao in view of Hershko lacks the specific teaching that the third external contact terminal is electrically insulated from the integrated circuit package.
Lee II teaches a memory card adaptor (100), designed for adapting a UFS card (10) to a standard SD card form factor, where terminal 3 of the memory card adaptor is insulated from the UFS card (see Fig. 3 showing terminal 3 unconnected).
It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the present application, to insulate the third external contact terminal from the integrated circuit package in order to prevent short circuits.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSS TERRY MULARSKI whose telephone number is (571)272-0284. The examiner can normally be reached Monday - Friday, 8:00 am - 5:00 pm EST.
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/R.T.M./Examiner, Art Unit 2841 /IMANI N HAYMAN/Supervisory Patent Examiner, Art Unit 2841