DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 2/25/2026 is acknowledged.
Claims 13-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/25/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 11, 12, 19-21 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamashita (US2006/0169484A1).
Yamashita discloses the claimed invention as follows (refer to Fig. 5):
Claim 1. A circuit board comprising (see Fig. 4(D)):
a first insulating layer (14);
a conductive pad (for claims 1, 2, 10-12 and 19: 20; for claims 3-9: 24) that protrudes above a surface of the first insulating layer; and
a second insulating layer (12) that includes a material different from the first insulating layer, is disposed below the first insulating layer, and includes a reinforcing material (glass cloth; see [0049]),
wherein a corner (at 24s) of the conductive pad has a curved shape.
Claim 2. The circuit board of claim 1, wherein a portion (22) of the conductive pad is buried in the first insulating layer.
Claim 3. The circuit board of claim 1, further comprising:
a first via layer (22) disposed at the first insulating layer;
first circuit wiring (16D) connected to the first via layer;
a second via layer (see the via through layer 12) disposed at the second insulating layer; and
second circuit wiring (16U) connected to the second via layer,
wherein the conductive pad is connected to the first via layer.
Claim 4. The circuit board of claim 3, wherein the corner of the conductive pad having the curved shape is an upper1 corner of the conductive pad, and each of a corner of the first circuit wiring and a corner of the second circuit wiring has an angular shape (see Fig. 5).
Claim 5. The circuit board of claim 3, wherein a radius of curvature of the corner of the conductive pad is greater than a radius of curvature of a corner of the first circuit wiring or a radius of curvature of a corner of the second circuit wiring. See Fig. 5.
Claim 11. The circuit board of claim 1, wherein the first insulating layer does not include the reinforcing material.
Claim 12. The circuit board of claim 1, wherein the corner of the conductive pad having the curved shape protrudes from the first insulating layer, and a radius of curvature of the corner of the conductive pad protruding from the first insulating layer is greater than a radius of curvature of a corner of the conductive pad embedded in the first insulating layer. See Fig. 5.
Claim 19. A circuit board comprising:
a first insulating layer (14); and
a conductive pad (20) including a portion (24) protruding from the first insulating layer and another portion (22) embedded in the first insulating layer, wherein a corner of the portion of the conductive pad protruding from the first insulating layer has a radius of curvature greater than that of a corner of the another portion of the conductive pad embedded in the first insulating layer. See Fig. 5.
Claim 20. The circuit board of claim 19, further comprising:
a second insulating layer (12) disposed below the first insulating layer and including a reinforcing material (glass cloth);
a first via (22) disposed in the first insulating layer;
first circuit wiring (16D) connected to the conductive pad through the first via;
a second via (via through layer 12) disposed in the second insulating layer; and
second circuit wiring(16U) connected to the first circuit wiring through the second via.
Claim 21. The circuit board of claim 20, wherein the radius of curvature of the corner of the portion of the conductive pad protruding from the first insulating layer is greater than a radius of curvature of a corner of the first circuit wiring or a radius of curvature of a corner of the second circuit wiring. See Fig. 5.
Claim 25. The circuit board of claim 20, wherein the first insulating layer does not include the reinforcing material.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 9-12, 19-22, 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Oshima (US2016/0234932A1) in view of Yamashita.
Oshima discloses the claimed invention as follows (refer to Fig. 15; limitations not disclosed by Oshima are crossed out, below):
Claim 1. A circuit board comprising:
a first insulating layer (450 with non-shown solder resist layer; see [0131], especially last sentence);
a conductive pad (460; see last sentence of [0131])
a second insulating layer (22) that includes a material different from the first insulating layer, is disposed below the first insulating layer, and includes a reinforcing material (30),
Claim 2. The circuit board of claim 1, wherein a portion of the conductive pad is buried in the first insulating layer (part of the pad 460 is within the solder resist layer).
Claim 3. The circuit board of claim 1, further comprising:
a first via layer (450x; see [0137]) disposed at the first insulating layer;
first circuit wiring (440; see [0135]) connected to the first via layer;
a second via layer (20x) disposed at the second insulating layer; and
second circuit wiring (40) connected to the second via layer,
wherein the conductive pad is connected to the first via layer.
Claim 4. The circuit board of claim 3, wherein the corner of the conductive pad
Claim 5. The circuit board of claim 3, wherein a radius of curvature of the corner of the conductive pad is greater than a radius of curvature of a corner of the first circuit wiring or a radius of curvature of a corner of the second circuit wiring. See Fig. 5.
Claim 6. The circuit board of claim 3, further comprising a solder resist layer (50) that is disposed below the second insulating layer and has an opening (50x) overlapping the second circuit wiring.
Claim 9. The circuit board of claim 3, wherein a minimum diameter of the second via layer is greater than a minimum diameter of the first via layer. See Fig. 15.
Claim 10. The circuit board of claim 1, wherein the first insulating layer includes a silica filler (see [0132] and [0136]), the second insulating layer includes a silica filler (see [0039]) and the reinforcing material, and the reinforcing material includes a glass cloth (see [0039]).
Claim 11. The circuit board of claim 1, wherein the first insulating layer does not include the reinforcing material.
Claim 12. The circuit board of claim 1, wherein the corner of the conductive pad having the
Claim 19. A circuit board comprising:
a first insulating layer (450 with the not-shown solder resist (see last sentence of [0131]); and
a conductive pad (460; see last sentence of [0131]) including
Claim 20. The circuit board of claim 19, further comprising:
a second insulating layer (22) disposed below the first insulating layer and including a reinforcing material (30);
a first via (450x) disposed in the first insulating layer;
first circuit wiring (440) connected to the conductive pad through the first via;
a second via (20x) disposed in the second insulating layer; and
second circuit wiring (40) connected to the first circuit wiring through the second via.
Claim 21. The circuit board of claim 20,
Claim 22. The circuit board of claim 20, further comprising a solder resist layer (50) disposed below the second insulating layer and having opening (50x) overlapping the second circuit wiring.
Claim 24. The circuit board of claim 20, wherein a minimum diameter of the second via is greater than a minimum diameter of the first via. See Fig. 15.
Claim 25. The circuit board of claim 20, wherein the first insulating layer does not include the reinforcing material.
Oshima discloses the claimed invention, except for the crossed-out limitations.
Yamashita discloses “a printed wiring board having an intensified drop impact resistance of a joint portion between pad and solder. An electrode pad [20] comprises pad portion [24] loaded with solder ball and a cylindrical portion [22] projecting to the solder ball supporting the pad portion. An outer edge of the pad portion extends sideway from a cylindrical portion so that the outer edge is capable of bending. If the outer edge bends when stress is applied to the solder ball 30, stress on the outer edge of the pad portion on which stress is concentrated can be relaxed so as to intensify the joint strength between an electrode pad and solder ball” (see abstract). The portion 24 has a rounded corner 24s.
In Oshima, pads 460 can be used to have solder balls disposed thereon (see 130 in Fig. 18). In view of the teachings of Yamashita, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to form the solder pads 460 of Oshima with a portion embedded within the solder resist layer (corresponding to 22 in Yamashita) and a portion protruding from the solder resist layer (corresponding to 24 in Yamashita), in order to obtain a printed wiring board having an intensified drop impact resistance of a joint portion between pad and solder.
Claim(s) 7, 8 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita in view of Tateiwa (US2011/0227214A1).
Oshima in view of Yamashita renders obvious the claimed invention, except for the limitations of claims 7, 8 and 23.
However, it is known to apply, to pads of a circuit board , surface treatment such as plating with nickel, palladium and gold, to enhance their contact properties (see [0036] and Fig. 6C).
In view of the teachings of Tateiwa, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to form such surface treatment layers on the exposed surface of the pads of modified Oshima, to enhance their contact properties as discussed by Tateiwa. Such surface treatment layers correspond to the claimed auxiliary pads.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIVIUS R CAZAN whose telephone number is (571)272-8032. The examiner can normally be reached Monday - Friday noon-8:30 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hong can be reached at 571-272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LIVIUS R. CAZAN/Primary Examiner, Art Unit 3729
1 The term “upper” is not limiting, as the circuit board can be oriented in any direction.