DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-11, 13, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2021/0006225 A1 to Hatano.
Hatano clearly teaches a low loss temperature compensated surface acoustic wave filter and duplexer, comprising:
a layer of piezoelectric material (12);
a pair of interdigital transducer electrodes (14) disposed on an upper surface of the layer of piezoelectric material, each interdigital transducer electrode including a bus bar (see paragraphs [0044]-[0046]) and a plurality of electrode fingers (16, 18, 24) extending from the bus bar towards an edge region of the interdigital transducer electrode at distal ends of the electrode fingers; and
trench portions (105) located in the upper surface of the layer of piezoelectric material, the trench portions overlapping with the edge regions of the interdigital transducer electrodes (see Figures 2A, 3A, 4A, 4C, and 5B).
With regards to claim 2, Hatano discloses:
the trench portions being located in the areas of the upper surface of the layer of piezoelectric material that are overlapped by the edge regions of the interdigital transducer electrodes and are not covered by the interdigital transducer electrodes (see Figures 2A, 3A, 4A, 4C, and 5B).
With regards to claim 3, Hatano discloses:
the trench portions extend discontinuously in a direction of propagation of an acoustic wave to be generated by the pair of interdigital transducer electrodes (see Figures 2A, 3A, 4A, 4C, and 5B).
With regards to claim 6, Hatano discloses:
the trench portions increasing the effective thickness of the interdigital transducer electrodes within the edge regions.
With regards to claim 7, Hatano discloses:
the electrode fingers of each interdigital transducer electrode interleave with one another in an active region of the pair of interdigital transducer electrodes, and form gap regions between the ends of the fingers of one of the interdigital transducer electrodes and the bus bar of the other interdigital transducer electrode, edge regions of the pair of interdigital transducer electrodes are located within the active region and on opposing sides of the active region, and the active region includes a central region and the edge regions of the interdigital transducer electrodes, each edge region extending from tips of the plurality of electrode fingers of one of the interdigital transducer electrodes towards the center of the central region (see Figures 2A, 3A, 4A, 4C, and 5B).
With regards to claim 8, Hatano discloses:
a duty factor (see paragraphs [0051] and [0058]) of the pair of interdigital transducer electrodes in the edge regions of the interdigital transducer electrodes is less than a duty factor of the pair of interdigital transducer electrodes in the central region of the active region.
With regards to claim 9, Hatano discloses:
the trench portions in the upper surface of the layer of piezoelectric material also overlap with at least part of the gap regions, and the trench portions each have a width in a direction perpendicular to a direction of propagation of an acoustic wave to be generated by the pair of interdigital transducer electrodes that extends from the respective edge region of one interdigital transducer electrode to the bus bar of the other interdigital transducer electrode (see Figures 2A, 3A, 4A, 4C, and 5B).
With regards to claim 10, Hatano discloses:
each of the interdigital transducer electrodes includes a second bus bar that is located within the gap region (see Figures 2A, 3A, 4A, 4C, and 5B).
With regards to claim 11, Hatano discloses:
dummy electrodes (see paragraphs [0044]-[0046]) extending from the second bus bar partially through the gap region toward an adjacent edge region.
With regards to claim 13, Hatano discloses:
each interdigital transducer electrode being formed from one or more lower layers of material and an upper layer of etch resistant material selected from the group consisting of copper (see paragraph [0050]), platinum, tungsten (see paragraph [0050]), molybdenum (see paragraph [0050]), ruthenium, iridium, gold, and silver, the upper layers have lesser maximum widths than the lower layers.
With regards to claim 19, Hatano discloses:
a layer of piezoelectric material (12);
a pair of interdigital transducer electrodes (14) disposed on an upper surface of the layer of piezoelectric material, each interdigital transducer electrode including a bus bar (see paragraphs [0044]-[0046]) and a plurality of electrode fingers (16, 18, 24) extending from the bus bar towards an edge region of the interdigital transducer electrode at the distal ends of the electrode fingers; and
trench portions (105) located in the upper surface of the layer of piezoelectric material, the trench portions overlapping with the edge regions of the interdigital transducer electrodes (see Figures 2A, 3A, 4A, 4C, and 5B).
With regards to claim 20, Hatano discloses:
a layer of piezoelectric material (12);
a pair of interdigital transducer electrodes (14) disposed on an upper surface of the layer of piezoelectric material, each interdigital transducer electrode including a bus bar (see paragraphs [0044]-[0046]) and a plurality of electrode fingers (16, 18, 24) extending from the bus bar towards an edge region of the interdigital transducer electrode at the distal ends of the electrode fingers; and
trench portions (105) located in the upper surface of the layer of piezoelectric material, the trench portions overlapping with the edge regions of the interdigital transducer electrodes (see Figures 2A, 3A, 4A, 4C, and 5B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4, 5, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2021/0006225 A1 to Hatano in view of U.S. Patent Application Publication No. 2021/0126616 A1 to Hiramatsu et al.
Hatano clearly teaches a low loss temperature compensated surface acoustic wave filter and duplexer as described in paragraph 4 above.
However, it fails to discloses the trench portions each have a width in a direction perpendicular to a direction of propagation of an acoustic wave to be generated by the pair of interdigital transducer electrodes of between about 0.5k and 1k, where k is the wavelength of the acoustic wave to be generated.
Hiramatsu et al. discloses an acoustic wave resonator with mass loading strip for suppression of transverse mode, comprising:
trench portions each having a width in a direction perpendicular to a direction of propagation of an acoustic wave to be generated by the pair of interdigital transducer electrodes of between about 0.5 λ and 1 λ, where λ is the wavelength of the acoustic wave to be generated (see paragraphs [0048], [0053], [0058], [0077], [0082], and [0086]).
It would have been obvious to one skilled in the art before the effective filling date of the invention to use the width range of the trench portions disclosed by Hiramatsu et al. on the low loss temperature compensated surface acoustic wave filter and duplexer disclosed by Hatano, for the purpose of “avoiding significant frequency variation” (see paragraph [0048]).
With regards to claim 5, Hiramatsu et al. discloses:
the trench portions each having a depth relative to the upper surface of the layer of piezoelectric material of between about 0.004λ, and 0.02λ, where λ is the wavelength of an acoustic wave generated by the pair of interdigital transducer electrodes during operation (see paragraphs [0048], [0053], [0058], [0077], [0082], and [0086]).
With regards to claim 12, Hiramatsu et al. discloses:
a layer of dielectric material (see paragraphs [0045], [0046], and [0088]), the layer dielectric material having an upper surface disposed against a lower surface of the layer of piezoelectric material, and a carrier substrate, the carrier substrate having an upper surface disposed against a lower surface of the layer of dielectric material.
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2021/0006225 A1 to Hatano in view of U.S. Patent Application Publication No. 2018/0102760 A1 to Inoue et al.
Hatano clearly teaches a low loss temperature compensated surface acoustic wave filter and duplexer as described in paragraph 4 above.
However, it fails to discloses the upper layers have trapezoidal cross- sections.
Inoue et al. discloses slanted apodization for acoustic wave devices, comprising:
upper layers have trapezoidal cross-sections (see paragraph [0042]).
It would have been obvious to one skilled in the art before the effective filling date of the invention to use the trapezoidal shape disclosed by Inoue et al. on the layers of the low loss temperature compensated surface acoustic wave filter and duplexer disclosed by Hatano, for the purpose of providing “adequate performance while reducing the surface area of the interdigital transducer 38 and reflector structures when compared to the interdigital transducer 38 shown in FIG. 4A” (see paragraph [0042]).
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2021/0006225 A1 to Hatano in view of U.S. Patent Application Publication No. 2017/0155370 A1 to Iwasaki et al.
Hatano clearly teaches a low loss temperature compensated surface acoustic wave filter and duplexer as described in paragraph 4 above.
However, it fails to discloses each interdigital transducer electrode including a mask layer on an upper surface of the interdigital transducer electrode.
Iwasaki et al. discloses acoustic wave elements and antenna duplexers, and modules and electronic devices using same, comprising:
each interdigital transducer electrode includes a mask layer on an upper surface of the interdigital transducer electrode (see paragraph [0062] and claim 20).
It would have been obvious to one skilled in the art before the effective filling date of the invention to use the mask layer disclosed by Iwasaki et al. on the low loss temperature compensated surface acoustic wave filter and duplexer disclosed by Hatano, for the purpose of providing the “manufacturing an acoustic wave element includes simultaneously forming a plurality of electrodes on a piezoelectric substrate” (Abstract).
With regards to claim 16, Iwasaki et al. discloses:
the mask layer being a layer of chromium (see paragraphs [0013] and [0047]).
With regards to claim 17, Iwasaki et al. discloses:
a protective layer (see paragraph [0007], [0008], [0010], [0012], [0013], [0015], [0019], [0047], [0048], [0052], [0053], [0058]-[0060], [0064], and [0065]) disposed over upper surfaces of the pair of interdigital transducer electrodes and the layer of piezoelectric material.
With regards to claim 18, Iwasaki et al. discloses:
the protective layer is formed from one or more of the group consisting of silicon nitride (see paragraph [0012] and [0048]), silicon oxynitride, and silicon dioxide.
Conclusion
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/PEDRO J CUEVAS/Primary Examiner, Art Unit 2896 March 5, 2026