Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to under 37 CFR 1.74. “When there are drawings, there shall be a brief description of the several views of the drawings”. The brief descriptions of Figures 1-8 and 10 in paragraphs [0004]-[0011] and [0013] cannot be so broad that several different views share identical descriptions. Examiner suggests using the first sentence of the respective section where each figure is described the detailed description as suitable language for the brief description.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1-5 and 10, the phrase “is to comprise” is future tense, reflects an invention that is yet to occur, and is unclear that the claims portray something in the present.
Examiner suggests replacing all instances of “is to comprise” with the present tense language “comprises”.
Claims 6-9 are rejected by virtue of their dependency on claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7, 9-13 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Aananthakrishnan et al., “PIUMA: Programmable Integrated Unified Memory Architecture”, hereinafter Aananthakrishnan, in view of Ahn et al., “HyperX: Topology, Routing, and Packaging of Efficient Large-Scale Networks”, hereinafter Ahn, and further in view of Knuth, The Art of Computer Programming, Volume 3, Sorting & Merging.
Regarding claim 1, Aananthakrishnan discloses an apparatus, comprising: a network (Section III D).
Aananthakrishnan does not disclose the network comprising a plurality of switches; and a plurality of compute cores coupled to the network, wherein a first switch of the plurality of switches is to comprise circuitry to: receive a first element of a first array and a first element of a second array; determine that the first element of the first array is less than the first element of the second array; and cause the first element of the first array to be stored as a first element of an output array.
Ahn discloses a network comprising a plurality of switches (Figure 3, R); and a plurality of compute cores coupled to the network (Figure 3, T), wherein a first switch of the plurality of switches is to comprise circuitry (Figure 9).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to use the network disclosed by Ahn in the processor architecture disclosed by Aananthakrishnan because the HyperX topology is used by Aananthakrishnan’s PIUMA system (Section III D, ¶ 2).
The combination of Aananthakrishnan and Ahn does not disclose an algorithm to receive a first element of a first array and a first element of a second array; determine that the first element of the first array is less than the first element of the second array; and cause the first element of the first array to be stored as a first element of an output array.
Knuth discloses an algorithm that receives a first element of a first array and a first element of a second array (Algorithm M (p. 158), Step M2 when i = j = 1); determines that the first element of the first array is less than the first element of the second array (Step M2); and causes the first element of the first array to be stored as a first element of an output array (Step M3).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the switching circuitry disclosed by the combination of Aananthakrishnan and Ahn to include the sorting algorithm as disclosed by Knuth because Knuth’s merge algorithm is “essentially the best possible way to merge on a conventional computer” (p. 159).
Regarding claim 2, Knuth discloses the apparatus of claim 1, wherein the first switch of the plurality of switches is to comprise circuitry to: receive a second element of the first array from a first compute core of the plurality of compute cores (Step M2, set i to 2); determine the first element of the second array is less than the first element of the first array (Step M2, “otherwise, go to M5”); and cause the first element of the second array to be stored as a second element of the output array (Step M5).
Regarding claim 3, Knuth discloses the apparatus of claim 1, wherein the first switch of the plurality of switches is to comprise circuitry to: receive, from a first compute core of the plurality of compute cores, an indication that no additional elements of the first array remain (Step M3, i ≤ m is false); and cause the first element of the second array to be stored as a second element of the output array (Step M4).
Regarding claim 5, Knuth discloses the apparatus of claim 1, wherein the first switch of the plurality of switches is to comprise circuitry to: receive, via a second switch of the plurality of switches, a first element of a third array (p. 252, Step 2, 154); determine the first element of the second array is less than the first element of the third array (Id.); and cause the first element of the second array to be stored as a second element of the output array (Id.).
Regarding claim 7, Ahn discloses the apparatus of claim 1, wherein the first switch causes the first element of the first array to be stored as the first element of the output array via a first output port of a plurality of output ports of the first switch (Section 3.3, ¶ 4), wherein the first output port is based on a configuration of the first switch (Id.).
Regarding claim 9, Knuth discloses the apparatus of claim 1, wherein a configuration of the first switch defines at least a portion of a tree to generate the output array (p. 252, “two-level selection tree”).
Regarding claim 10, Aananthakrishnan discloses the apparatus of claim 1, wherein the network is to comprise a Programmable and Integrated Unified Memory Architecture (PIUMA) network (Abstract).
Regarding claims 11-13, they are method claims that correspond to apparatus claims 1-3, respectively, and are rejected for the same reasons.
Regarding claims 15 and 16, they are method claims that correspond to apparatus claims 5 and 10, respectively, and are rejected for the same reasons.
Regarding claims 17-19, they are media claims that correspond to apparatus claims 1-3, respectively, and are rejected for the same reasons.
Claims 4, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Aananthakrishnan, Ahn and Knuth as applied to claim 1 above, and further in view of Intel 64 and IA-32 Architectures Software Developer’s Manual, hereinafter Intel ISA.
Regarding claim 4, Knuth discloses a modification to Algorithm M wherein the first switch of the plurality of switches is to comprise circuitry to: receive, from a second compute core of the plurality of compute cores, an indication that no additional elements of the second array remain (p. 159, add ∞ as a sentinel).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to include the modification as disclosed by Knuth to the system disclosed by Aananthakrishnan, Ahn and Knuth because adding a sentinel to the end of the arrays allows the algorithm to “be made slightly simpler without much loss of efficiency” (p. 159)
The combination of Aananthakrishnan, Ahn and Knuth does not disclose returning to a third compute core of the plurality of compute cores, an interrupt to indicate the output array has been sorted.
Intel ISA discloses returning, to a third compute core of the plurality of compute cores, an interrupt to indicate the output array has been sorted (SENDUIPI Instruction).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system as disclosed by Aananthakrishnan, Ahn and Knuth to include inter-processer interrupts (IPI) as disclosed by Intel ISA because IPI are commonly used in both multi-core (Figure 11-1) and multi-processor (Figure 11-2, 11-3) systems and “can be used to distribute interrupts among the processors in the system or to execute system wide functions” (Page 11-1, bullet point 2).
Regarding claims 14, it is a method claim that corresponds to apparatus claims 1, and is rejected for the same reasons.
Regarding claims 20, it is a media claim that corresponds to apparatus claims 1, and is rejected for the same reasons.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Aananthakrishnan, Ahn and Knuth as applied to claim 1 above, and further in view of Giamei et al. (US 10,831,478), hereinafter Giamei.
The combination of Aananthakrishnan, Ahn and Knuth does not disclose wherein the first switch determines to perform a comparison between the first element of the first array and the first element of the second array based on a configuration of the first switch.
Giamei discloses the apparatus of claim 1, wherein the first switch determines to perform a comparison between the first element of the first array and the first element of the second array based on a configuration of the first switch (Figure 3K, 360).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system disclosed by Aananthakrishnan, Ahn and Knuth to include the configuration table as disclosed by Giamei because the configuration allows a quicker fail state for unsupported inputs (Column 12, lines 21-24).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Aananthakrishnan, Ahn and Knuth as applied to claim 1 above, and further in view of Giamei.
The combination of Aananthakrishnan, Ahn and Knuth does not disclose wherein the first element of the first array is received based on an instruction defined by an Instruction Set Architecture (ISA), wherein the first element of the second array is based on the instruction defined by the ISA.
Giamei discloses the apparatus of claim 1, wherein the first element of the first array is received based on an instruction defined by an Instruction Set Architecture (ISA) (Figure 3K, 392), wherein the first element of the second array is based on the instruction defined by the ISA (Figure 3K, 394).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system as disclosed by Aananthakrishnan, Ahn and Knuth to include a single sorting instruction as disclosed by Giamei because “The replacement of those primitive instructions with a single architected instruction reduces program complexity and eliminates the need to include code to optimize the primitive instructions” (Column 1, lines 45-48).
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Giamei in view of Arm Architecture Reference Manual, Armv8, for Armv8-A architecture profile, hereinafter Armv8 ISA.
Regarding claim 21, Giamei discloses a non-transitory computer-readable storage medium, the computer-readable storage medium including instructions that when executed by a processor, cause the processor to: execute a first instruction set architecture (ISA) instruction to initiate a sort operation based on a first input array of a plurality of input arrays (Figure 3K, 392).
Giamei does not disclose a second ISA instruction to receive an output of the sort operation, the output to comprise a sorted array.
Armv8 ISA discloses a second ISA instruction to receive an output of the sort operation, the output to comprise a sorted array (MRRC Instruction).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to modify the instruction as disclosed by Giamei to include the second ISA instruction as disclosed by Armv8 ISA because it would allow the offloading of the expensive sorting operation to another processor asynchronously, allowing the other processor to continue working.
Regarding claim 22, Giamei discloses the computer-readable storage medium of claim 21, wherein the first ISA instruction is to comprise a base memory address of the first input array (Figure 3K, 392), a size of an array element of the first input array (Figure 3K, 370), and a number of elements of the first input array (Figure 3K, 393).
Regarding claim 23, Armv8 discloses the computer-readable storage medium of claim 21, wherein the execution of the second ISA instruction returns a base memory address of the sorted array and a number of elements of the sorted array (MRRC Instruction, Rt1 is base memory address, Rt2 is number of elements).
Discussion of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mao (US 2023/0236794) discloses a system for sorting a single set of numbers by splitting the sets, running a sorting algorithm on the subsets in parallel, and merging the sorted arrays into one complete sorted array. Bajaj (US 10,462,042) discloses a network where data is routed based on a configuration of the switches.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Matthew Strapp whose telephone number is (571)272-9343. The examiner can normally be reached Monday-Friday 8:00 AM-4:00 PM.
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/M.S./
Matthew StrappExaminer, Art Unit 2182 (571)272-9343
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
