Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al. (20170179153) in view of Titus et al. (US 20180331117).
Regarding claim 1, Ogawa (e.g. fig. 29A) teaches a semiconductor device comprising:
a peripheral circuit structure 750 disposed on a lower substrate 9, and including a peripheral pad portion 788 (¶¶0163; 164; 170);
an upper substrate 9 disposed on the peripheral circuit structure;
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a stack structure 132/142 disposed on the upper substrate, and including gate horizontal patterns 142, the gate horizontal patterns being stacked while being spaced apart from each other in a vertical direction perpendicular to an upper surface of the upper substrate 10 (¶¶175-177);
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a vertical channel structure 50 passing through the stack structure in a first region on the upper substrate;
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a vertical support structure 171/271 passing through the stack structure in a second region on the upper substrate 10;
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a separation structure 72, 74,76 passing through the stack structure in the first and second regions (see fig. 26B; ¶198);
a peripheral contact plug 488 electrically connected to the peripheral pad portion, wherein the stack structure has a stepped shape in the second region (see fig. 30; ¶251)
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wherein the vertical channel structure includes a lower channel portion 11, an upper channel portion on the lower channel portion 60, and an intermediate channel portion between the lower channel portion and the upper channel portion (see layer 180), wherein the lower channel portion includes a lower channel side surface having a first slope, wherein the upper channel portion includes an upper channel side surface having a second slope (see also, fig. 24A; 25A showing the sloped via holes and the intermediate hole in layer 180 having a different slope),
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wherein the vertical support structure includes: a lower support portion disposed at the same level as the lower channel portion (bottom portion of 171 located coplanar with 11);
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;
an intermediate support portion disposed at the same level as the intermediate portion (e.g. (lower portion of 271 formed in layer 180);
and an upper support portion (top portion of 171) disposed at the same level as the upper channel portion, and wherein a side surface of the lower support portion, a side surface of the intermediate support portion and a side surface of the upper support portion are aligned with each other (see fig. 29A).
Ogawa does not explicitly teach the details of the intermediate portion. Therefore, it is not disclosed that the intermediate portion includes an intermediate channel portion includes a width variation region.
Nevertheless, Titus (see fig. 13H; ¶0125) teaches a three portion channel for a 3D semiconductor device similar to the semiconductor device disclosed by Ogawa. Titus teaches that the channel includes an intermediate channel portion comprising a semiconductor channel 509 having a conic shape (e.g. a width variation region).
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It would have been obvious to one of ordinary skill in the at the time of the invention was made to make the intermediate channel portion of Ogawa as disclosed by Titus which is formed on the intermediate insulating layer 170/232 and includes a side wall having a conic shape (a width variation) because the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. For example, this type of interconnection will follow a similar outlined disposition as that disclosed by Ogawa without changing its main function “connection the upper channel and the lower channel in a 3D memory device”. Also, this type of intermediate connection provide a more reliable interconnection between upper portion and lower portion of the memory device because it creates a locking structure in the joining insulating layer 1710/232 (see KSR, 550 U.S. at 416, 82 USPQ2d at 1395; MPEP 2143).
Regarding claim 2, Ogawa (e.g. fig. 29A) teaches that the peripheral contact plug 488 includes a lower plug portion disposed at the same level as the lower channel portion (e.g. in layers 52-170); an intermediate plug portion disposed at the same level as the intermediate channel portion (e.g. in layer 180); and an upper plug portion disposed at the same level as the upper channel portion (e.g. in layers 232-270). Also, a side surface of the lower plug portion, a side surface of the intermediate plug portion and a side surface of the upper plug portion are aligned with each other.
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Regarding claim 3, Ogawa in view of Titus (e.g. fig. 29A/13H) teaches that intermediate channel side surface extends from the upper channel side surface to lower channel side surface. Also, that the upper channel side surface is not aligned with the lower channel side surface.
Regarding claim 4, Ogawa in view of Titus (e.g. fig. 29A/13H) teaches that the first slope is substantially the same as the second slope (see also fig. 25A).
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Regarding claim 5, Ogawa (e.g. figs. 25A; 29A) that the gate horizontal patterns include an uppermost gate horizontal pattern 270 and a lowermost gate horizontal pattern 132. The vertical support structure includes an upper portion 271 positioned at the same level as an upper surface of the uppermost gate horizontal pattern and a lower portion positioned 170 at the same level as a lower surface of the lowermost gate horizontal pattern. Also, a width of the upper portion of the vertical support structure is greater than a width of the lower portion of the vertical support structure. As shown in figure, 29A, a width of the vertical support structure 271/171 monotonically changes between the upper portion and the lower portion.
Regarding claim 6, Regarding claim 5, Ogawa (e.g. figs. 25A; 29A; ¶0222) teaches that stack structure includes a lower stack structure (e.g. first tier structure 132, 142, 165, 170) and an upper stack structure ( e.g. second-tier alternating stack (232, 242) on the lower stack structure. The lower stack structure includes a plurality of lower gate horizontal patterns 142 among the gate horizontal patterns, wherein the upper stack structure includes a plurality of upper gate horizontal patterns 242 among the gate horizontal patterns. Also, it is disclosed that the lower channel portion faces the plurality of lower gate horizontal patterns, and that the upper channel portion faces the plurality of upper gate horizontal patterns.
Regarding claim 7, Ogawa (e.g. figs. 25A; 29A; ¶0222) teaches that the lower stack structure comprises a plurality of lower insulating layers 132 alternately stacked with the plurality of lower gate horizontal patterns142 and the upper stack structure further includes a plurality of upper insulating layers 242 alternately stacked with the plurality of lower gate horizontal patterns 232. Also, the stack structure further includes an intermediate insulating layer 180 between a lowermost gate pattern among the plurality of upper gate horizontal patterns and an uppermost gate pattern among the plurality of lower gate horizontal patterns. Also, a portion of the intermediate channel portion faces the intermediate insulating layer.
Regarding claim 8, Ogawa (e.g. fig. 29A) shows that a thickness of the intermediate insulating layer 180 is substantially the same as a thickness of the layer 270.
Regarding claim 9, Ogawa (e.g. figs. 10A; 23; 29A) teaches bit line contact plugs 88 on and electrically connected to the vertical channel structure; and a bit line 103 on and electrically connected to the bit line contact plug 88 (¶¶0251; 0294). Also, the gate horizontal patterns includes include word lines (¶0291). Moreover, the vertical channel structure includes an insulating core pattern 62; a channel layer 60 between the insulating core pattern and the gate horizontal patterns 142/242 (see fig. 10A). Also, Ogawa discloses a pad pattern 602 on the insulating core pattern and electrically connected to the channel layer 601; and a data storage layer 54 between the channel layer 601 and the word lines 2142/242, and wherein the vertical support structure is electrically unconnected to the bit line 103 (¶203, see fig. 23).
Regarding claim 10, Ogawa (e.g. figs. 17C/29A) teaches word lines in the second region have a stepped shape having substantially uniform slope in a first direction. The stepped shape of the word lines is defined by word line pads of the word lines arranged in the first direction. Also, Ogawa discloses that the separation structure 79 has a line shape extending in the first direction in a plan view (see figs. 27A; 26B).
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Regarding claim 11, Ogawa (e.g. fig. 29A) teaches that the upper substrate 10 includes a silicon layer, wherein the vertical channel structure contacts the silicon layer of the upper substrate (¶0169). Also, the vertical support structure 271/171 contacts the silicon layer of the upper substrate and a lower surface of the peripheral contact plug 488 contacts the peripheral pad portion. As shown in figure 29A, the lower surface of the peripheral contact plug is at a lower level than the upper substrate and an upper surface of the peripheral contact plug 488 is at a higher level than an upper surface of the vertical channel structure.
Regarding claim 12, Ogawa (e.g. 29A) teaches that the separation structure 74/76 includes a conductive core pattern 76 and an insulating spacer74 on a side surface of the conductive core pattern (¶¶0234-0236).
Regarding claim 13, Ogawa (e.g. fig. 29A) teaches a semiconductor device comprising:
a peripheral circuit structure 750 disposed on a lower substrate 9, and including a peripheral pad portion 788 (¶¶0163; 164; 170);
an upper substrate 10 disposed on the peripheral circuit structure;
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a stack structure 132/142 disposed on the upper substrate 10, and including gate horizontal patterns 142, the gate horizontal patterns being stacked while being spaced apart from each other in a vertical direction perpendicular to an upper surface of the upper substrate 10 (¶¶175-177);
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a vertical channel structure 50 passing through the stack structure in a first region on the upper substrate;
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a vertical support structure 171/271 passing through the stack structure in a second region on the upper substrate;
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a separation structure 72, 74,76 passing through the stack structure in the first and second regions (see fig. 26B; ¶198);
a peripheral contact plug 488 electrically connected to the peripheral pad portion, wherein the stack structure has a stepped shape in the second region and an upper surface of the peripheral contact plug is at a higher level than an upper surface of the vertical channel structure (see fig. 30; ¶251);
the vertical channel structure (see below) includes a lower channel portion, an upper channel portion on the lower channel portion, and an intermediate channel portion between the lower channel portion and the upper channel portion;
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wherein the lower channel portion includes a lower channel side surface;
wherein the upper channel portion includes an upper channel side surface;
wherein the intermediate channel portion includes an intermediate channel side surface;
wherein the vertical channel structure has an imaginary straight line (axis) extending from a center of a lower surface of the lower channel portion to a center of an upper surface of the upper channel portion, wherein a distance D2/2 between the imaginary straight line and the lower channel side surface adjacent to the intermediate channel side surface is greater than a distance D1/2 between the imaginary straight line and the upper channel side surface adjacent to the intermediate channel side surface;
wherein the vertical support structure 271/171 includes a lower support portion disposed at the same level as the lower channel portion (bottom portion of 171 located coplanar with 11 in fig. 29A);
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an intermediate support portion disposed at the same level as the intermediate portion (e.g. (lower portion of 271 formed in layer 180);
an upper support portion (top portion of 171) disposed at the same level as the upper channel portion, and wherein a side surface of the lower support portion, a side surface of the intermediate support portion and a side surface of the upper support portion are aligned with each other (see fig. 29A);
and wherein the peripheral contact plug 488 includes a lower plug portion disposed at the same level as the lower channel portion (e.g. in layers 52-170); an intermediate plug portion disposed at the same level as the intermediate channel portion (e.g. in layer 180); and an upper plug portion disposed at the same level as the upper channel portion (e.g. in layers 232-270).
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Also Ogawa teaches that a side surface of the lower plug portion, a side surface of the intermediate plug portion and a side surface of the upper plug portion are aligned with each other. Ogawa does not explicitly teach the details of the intermediate portion. Therefore, it is not disclosed that the intermediate portion includes an intermediate channel portion includes a width variation region.
Nevertheless, Titus (see fig. 13H; ¶0125) teaches a three portion channel for a 3D semiconductor device similar to the semiconductor device disclosed by Ogawa. Titus teaches that the channel includes an intermediate channel portion comprising a semiconductor channel 509 having a tapered shape (e.g. a width variation region).
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It would have been obvious to one of ordinary skill in the at the time of the invention was made to make the intermediate channel portion of Ogawa as disclosed by Titus which is formed on the intermediate insulating layer 170/232 and includes a side wall having a tapered shape (a width variation) because the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. For example, this type of interconnection will follow a similar outlined disposition as that disclosed by Ogawa without changing its main function “connection the upper channel and the lower channel in a 3D memory device”. Also, this type of intermediate connection provide a more reliable interconnection between upper portion and lower portion of the memory device because it creates a locking structure in the joining insulating layer 1710/232 (see KSR, 550 U.S. at 416, 82 USPQ2d at 1395; MPEP 2143).
Regarding claim 14, Ogawa (e.g. annotated fig. 29A) teaches that the lower channel portion adjacent to the intermediate channel portion has a first width D2, the upper channel portion adjacent to the intermediate channel portion has a second width D1 and that the intermediate channel portion has a third width D3. Ogawa discloses that the first width is greater than the second width, and wherein the third width is greater than each of the first width and the second width.
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Regarding claim 15, Ogawa (e.g. 25A; 29A; ¶0222) teaches that stack structure includes a lower stack structure (e.g. first tier structure 132, 142, 165, 170) and an upper stack structure ( e.g. second-tier alternating stack (232, 242) on the lower stack structure. The lower stack structure includes a plurality of lower gate horizontal patterns 142 among the gate horizontal patterns, wherein the upper stack structure includes a plurality of upper gate horizontal patterns 242 among the gate horizontal patterns. Also, it is disclosed that the lower channel portion faces the plurality of lower gate horizontal patterns, and that the upper channel portion faces the plurality of upper gate horizontal patterns.
Regarding claim 16 , Ogawa (e.g. Figs. 10A; 23; 29A) teaches bit line contact plugs 88 on and electrically connected to the vertical channel structure; and a bit line 103 on and electrically connected to the bit line contact plug 88 (¶¶0251; 0294). Also, the gate horizontal patterns include word lines (¶0291). Moreover, the vertical channel structure includes an insulating core pattern 62; a channel layer 60 between the insulating core pattern and the gate horizontal patterns 142/242 (see fig. 10A). Also, Ogawa discloses a pad pattern 602 on the insulating core pattern and electrically connected to the channel layer 601; and a data storage layer 54 between the channel layer 601 and the word lines 2142/242, and wherein the vertical support structure is electrically unconnected to the bit line 103 (¶203)see fig. 23).
Regarding claim 17, Ogawa (e.g. fig. 29A) teaches a semiconductor device comprising:
a peripheral circuit structure 750 disposed on a lower substrate 9 , and including a peripheral pad portion 788 (¶¶0163; 164; 170);
an upper substrate 10 disposed on the peripheral circuit structure;
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a stack structure 132/142 disposed on the upper substrate, and including gate horizontal patterns 142, the gate horizontal patterns being stacked while being spaced apart from each other in a vertical direction perpendicular to an upper surface of the upper substrate (¶¶175-177);
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a vertical channel structure 50 passing through the stack structure in a first region on the upper substrate;
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a vertical support structure 171/271 passing through the stack structure in a second region on the upper substrate;
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a separation structure 72, 74,76 passing through the stack structure in the first and second regions (see fig. 26B; ¶198);
a peripheral contact plug 488 electrically connected to the peripheral pad portion, wherein the stack structure has a stepped shape in the second region and an upper surface of the peripheral contact plug is at a higher level than an upper surface of the vertical channel structure, (see fig. 30; ¶251);
the vertical channel structure (see below) includes a lower channel portion, an upper channel portion on the lower channel portion, and an intermediate channel portion between the lower channel portion and the upper channel portion;
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wherein the vertical support structure 271/171 includes a lower support portion disposed at the same level as the lower channel portion (bottom portion of 171 located coplanar with 11 in fig. 29A);
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;
an intermediate support portion disposed at the same level as the intermediate portion (e.g. (lower portion of 271 formed in layer 180);
an upper support portion (top portion of 171) disposed at the same level as the upper channel portion, and wherein a side surface of the lower support portion, a side surface of the intermediate support portion and a side surface of the upper support portion are aligned with each other (see fig. 29A);
and wherein a side surface of the lower channel portion and side surface of the upper channel portion are not aligned with each other.
Ogawa does not explicitly teach the details of the intermediate portion. Therefore, it is not disclosed that the intermediate portion includes an intermediate channel portion includes a width variation region.
Nevertheless, Titus (see fig. 13H; ¶0125) teaches a three portion channel for a 3D semiconductor device similar to the semiconductor device disclosed by Ogawa. Titus teaches that the channel includes an intermediate channel portion comprising a semiconductor channel 509 having a tapered shape (e.g. a width variation region).
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It would have been obvious to one of ordinary skill in the at the time of the invention was made to make the intermediate channel portion of Ogawa as disclosed by Titus which is formed on the intermediate insulating layer 170/232 and includes a side wall having a conic shape (a width variation) because the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. For example, this type of interconnection will follow a similar outlined disposition as that disclosed by Ogawa without changing its main function “connection the upper channel and the lower channel in a 3D memory device”. Also, this type of intermediate connection provide a more reliable interconnection between upper portion and lower portion of the memory device because it creates a locking structure in the joining insulating layer 1710/232 (see KSR, 550 U.S. at 416, 82 USPQ2d at 1395; MPEP 2143).
Regarding claim 18 , Ogawa (e.g. annotated fig. 29A) teaches that the peripheral contact plug 488 includes a lower plug portion disposed at the same level as the lower channel portion (e.g. in layers 52-170); an intermediate plug portion disposed at the same level as the intermediate channel portion (e.g. in layer 180); and an upper plug portion disposed at the same level as the upper channel portion (e.g. in layers 232-270). Also, a side surface of the lower plug portion, a side surface of the intermediate plug portion and a side surface of the upper plug portion are aligned with each other.
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Regarding claim 19, Ogawa (e.g. 25A; 29A; ¶0222) teaches that stack structure includes a lower stack structure (e.g. first tier structure 132, 142, 165, 170) and an upper stack structure ( e.g. second-tier alternating stack (232, 242) on the lower stack structure. The lower stack structure includes a plurality of lower gate horizontal patterns 142 among the gate horizontal patterns, wherein the upper stack structure includes a plurality of upper gate horizontal patterns 242 among the gate horizontal patterns. Also, it is disclosed that the lower channel portion faces the plurality of lower gate horizontal patterns, and that the upper channel portion faces the plurality of upper gate horizontal patterns.
Regarding claim 20, Ogawa (e.g. Figs. 10A; 23; 29A) teaches bit line contact plugs 88 on and electrically connected to the vertical channel structure; and a bit line 103 on and electrically connected to the bit line contact plug 88 (¶¶0251; 0294). Also, the gate horizontal patterns include word lines (¶0291). Moreover, the vertical channel structure includes an insulating core pattern 62; a channel layer 60 between the insulating core pattern and the gate horizontal patterns 142/242 (see fig. 10A). Also, Ogawa discloses a pad pattern 602 on the insulating core pattern and electrically connected to the channel layer 601; and a data storage layer 54 between the channel layer 601 and the word lines 2142/242, and wherein the vertical support structure is electrically unconnected to the bit line 103 (¶203)see fig. 23).
Allowance over the Prior Art
Claims 21-31 are allowed over the prior art of record.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEONARDO ANDUJAR whose telephone number is (571)272-1912. The examiner can normally be reached Monday to Thursday 10 AM to 8 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patricia Engle can be reached at (571)272-6660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEONARDO ANDUJAR/Primary Examiner, Art Unit 3991
Conferees:
/ELIZABETH L MCKANE/Specialist, Art Unit 3991
/Patricia L Engle/SPRS, Art Unit 3991