DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on Kim et al. 20220005903 applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Amended claim 24 does not overcome Seo et al. 20220029130. Note claim 15 was indicate as allowable subject matter to claim 1, not to claim 24. As such claim 24 is anticipated by Seo et al. 20220029130.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 12-14, 16-17, 20 and 30-32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. 20220005903.
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Regarding claim 1, figs. 2 and 8 of Kim discloses a display device, comprising:
a substrate 100 including an active area DA having a hole OA, and a non-active area NDA1;
a first transistor TFT disposed in the active area, the first transistor including a first source electrode, a first semiconductor pattern, and a first drain electrode;
a second transistor TFTO disposed in the active area, the second transistor including a second source electrode, a second semiconductor pattern, and a second drain electrode;
a passivation layer 209a disposed on the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode;
an encapsulation layer 300 disposed on the passivation layer; and
a dam 240 and a plurality of patterns 810 located in the non-active area,
wherein at least two of the plurality of patterns are disposed within the encapsulation layer.
Regarding claim 2, fig. 8 of Kim discloses further comprising: a first inorganic layer 207b disposed on the substrate;
a separation element 242 (242 separate 241 from 243) which is disposed adjacent to the hole in an open area (top surface of 207b is open area for placing 241) of the first inorganic layer which is partially open in the non-active area; and
a dam 240 disposed adjacent to the hole on the first inorganic layer of the first non-active area, wherein the separation element is disposed in the dam.
Regarding claim 3, fig. 8 of Kim discloses further comprising:
a second inorganic layer 209 (par [0099] 209 may include an inorganic insulating material) disposed on the first inorganic layer, and a first organic layer 211 and a second organic layer 213 disposed on the second inorganic layer 209, wherein the dam includes:
a first sub dam 241 formed of the same material as the second inorganic layer (par [0142]);
a second sub dam 242 formed of the same material as the first organic layer (par [0142]); and
a third sub dam 243 formed of the same material as the second organic layer, and
wherein the separation element 242 is the second sub dam.
Regarding claim 4, fig. 8 of Kim discloses wherein an upper surface (top surface) and a portion of a side surface (bottom side is a side as element has many sides) of the separation element are disposed to be covered by the third sub dam.
Regarding claim 12, fig. 8 of Kim discloses further comprising a plurality of second patterns 810 / DL) disposed to enclose the hole on the first inorganic layer of the non-active area, wherein the plurality of second patterns is disposed between the hole and the separation element and between the separation element and the active area (DL is as claim), in plurality, respectively.
Regarding claim 13, fig. 1 of Kim discloses wherein the active area is configured to enclose the non-active area, and the dam is configured to enclose the hole.
Regarding claim 14, fig. 8 of Kim discloses wherein the separation element is disposed on the substrate exposed from the first inorganic layer.
Regarding claim 16, fig. 8 of Kim discloses wherein the first inorganic layer has a disconnected structure (region under 241 is a disconnected structure because it from the environment) by the separation element.
Regarding claim 17, fig. 8 of Kim discloses wherein the separation element is formed of an organic material.
Regarding claim 20, par [0068] of Kim discloses wherein the hole is disposed so as to correspond to at least one of a camera, a light sensor, a distance sensing sensor, and a face recognition sensor.
Regarding claim 30, fig. 1 of Kim discloses wherein the non-active area comprises: a first non-active area NDA1 in which the hole is disposed; and a second non-active area NDA2 enclosing the active area.
Regarding claim 31, fig. 8 of Kim discloses further comprising: a first organic layer 211 and a second organic layer 213 disposed on the passivation layer and disposed below the encapsulation layer, wherein the plurality of patterns are separated apart from the first organic layer and the second organic layer.
Regarding claim 32, fig. 8 of Kim discloses wherein the second semiconductor pattern A2 is disposed above the first semiconductor pattern A1.
Claims 24-25 and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo et al. 20220029130.
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Regarding claim 24, fig. 6 of Seo discloses a display device, comprising: a substrate 100 including a first non-active area MA in which a hole is disposed, and an active area DA adjacent to the first non-active area;
a first inorganic layer 201/203/205 disposed on the substrate;
a first transistor TFT and a second transistor (another TFT of a different pixel) disposed on the first inorganic layer in the active area;
a second inorganic layer 207 and a first organic layer 209 disposed on the first transistor and the second transistor;
a dam PW2 which is disposed adjacent to the hole on the first inorganic layer in the first non-active area and formed by sequentially laminating the same material as the second inorganic layer and the first organic layer (see fig. 9A showing step of sequentially laminating the same material as the second inorganic layer and the first organic layer before PW2 is formed as such meets the forming step as claimed); and
a separation element 1220 which is disposed in the dam and is formed of the same material as the first organic layer 209,
wherein the separation element 1220 is disposed in an open area of the first inorganic layer which is partially open (see region of MA where there is no first inorganic layer which is etched away and as such is partially open), and
wherein the first inorganic layer comprises at least one of a buffer layer 201, a first gate insulating layer 203 and a first interlayer insulating layer 205 of the first transistor disposed in the active area, an upper buffer layer, a second gate insulating layer and a second interlayer insulating layer of the second transistor disposed in the active area.
Regarding claim 25, fig. 6 of Seo discloses wherein the dam includes: a first sub dam 201 formed of the same material as the second inorganic layer; a second sub dam 1220 formed of the same material as the first organic layer 209; and a third sub dam 1240 disposed on the second sub dam, and the separation element 1220 is the second sub dam 1220.
Regarding claim 29, fig. 6 of Seo discloses wherein the active area DA is disposed to enclose the first non-active area, the dam is disposed to enclose the hole, and the separation element is disposed on the substrate exposed from the first inorganic layer.
Allowable Subject Matter
Claim 5 is allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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